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1
Yang, Xi S. M. Massachusetts Institute of Technology. "Design of a continuous-time bandpass delta-sigma modulator." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87939.
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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 103-105).<br>An 8th-order continuous-time (CT) bandpass delta-sigma modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signal-to- noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order system, achieving a maximum stable input range of -1.9 dBFS. A 2.5-V/1.2-V dual-supply loop filter with a feed-forward coupling path has been proposed to suppress noise and distortion. On the transistor level, a 5th -order dual-supply feed-forward operational amplifier (op amp) and a 4th-order single-supply feed-forward op amp have been designed to enable high modulator linearity and coefficient accuracy.<br>by Xi Yang.<br>S.M.
2
Liu, Xuemei. "Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3257.
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Bandpass sigma-delta modulators combine oversampling and noise shaping to get
very high resolution in a limited bandwidth. They are widely used in applications that
require narrowband high-resolution conversion at high frequencies. In recent years interests
have been seen in wireless system and software radio using sigma-delta modulators to
digitize signals near the front end of radio receivers. Such applications necessitate clocking
the modulators at a high frequency (MHz or above). Therefore a loop filter is required in
continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime
circuits (e.g., using switched capacitors) where the maximum clocking rate is limited
by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry.
In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking
at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new
calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the
modulator. The continuous-time loop filter is based on Gm-C resonators. A novel
transconductance amplifier has been developed with high linearity at high frequency. Qfactor
of filter is enhanced by tunable negative impedance which cancels the finite output
impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal
standard analog CMOS technology. Postlayout simulation in CADENCE
demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1
MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ±
1.65V.
3
Mariano, André Augusto. "Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13644/document.
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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz<br>Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz
4
Mahmoud, Doaa. "Convertisseur analogique-numérique de type Sigma-Delta Passe-Bande avec résonateurs à un et deux amplificateurs." Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS288.
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Le récepteur radio logicielle (SDR) est une technique prometteuse pour les futurs récepteurs adaptés à une variété de protocoles. Il numérise le signal RF directement en basse fréquence. Nous proposons un récepteur SDR basé sur un modulateur sigma-delta à temps continu passe-bande (CT BP ). Nous nous concentrons sur les résonateurs RC actifs pour diminuer la surface du circuit. Nous ciblons les applications au voisinage de 400 MHz, à savoir Advanced Research and Global Observation Satellite (ARGOS), Medical Implant Communication Service (MICS), Automobile Keyless system et Industrial, Scientific and Medical (ISM). Nous présentons une nouvelle comparaison détaillée entre le modulateur CT BP à résonateur à deux amplificateurs et le modulateur CT BP à résonateur à un amplificateur. Les deux modulateurs sont conçus à l'aide de transistors MOS en technologie FDSOI-28nm, où nous utilisons la polarisation du caisson pour compenser les variations de processus, de tension et de température<br>Software defined radio receiver is a promising technique for future receivers which provides a variety of protocols. It digitizes the RF signal directly to low-frequency. We propose an SDR receiver based on a bandpass sigma delta modulator. The most essential element is the loop filter, there are two main configurations, an LC tank resonator and an active RC resonator. We focus on the active RC resonators for a low chip area. We target applications in the vicinity of 400 MHz, namely Advanced Research and Global Observation Satellite, Medical Implant Communication Service. We introduce a new comparison between the two-op-amp resonator CT BP sigma delta modulator and the one-op-amp resonator CT BP sigma delta modulator. We study the sensitivity of the quality factor and the signal to noise ratio to the DC-gain op-amps in two-op-amp resonator sigma delta modulator. It also shows how, in one-op-amp resonator sigma delta modulator, the quality factor and the signal to noise ratio, are very sensitive to any variations in the capacitors values for limited DC-gain op-amps. We establish a mathematical model of the thermal-noise behaviour for two-op-amp resonator CT BP sigma delta modulator. This model matches the circuit simulator results with a good accuracy. Furthermore, we demonstrate that a high quality factor (>100) of the two-op-amp resonators can be achieved by selecting the proper value of the integrator gain at a moderate DC-gain op-amp (35dB). Both sigma delta modulators are designed using flipped-well devices on fully depleted silicon on insulator technology, where we use body biasing to compensate the process, voltage and temperature variations
5
Ali, Furrookh. "Noise-shaping enhancement in continuous-time delta-sigma modulators." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66679.
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A technique is presented for designing high-order continuous-time (CT) delta-sigma modulators with noise-transfer-function (NTF) enhancement. This enhancement is achieved by injecting the quantization noise into the forward path of the CT delta-sigma modulator, through a passive CT filter. This passive filter introduces a real pole-zero pair into the NTF. Thus, the order of the NTF is increased, without affecting the signal transfer function (STF). The proposed NTF-enhancement technique is applied to a CT delta-sigma modulator with a capacitive-feedforward architecture, where all feedforward paths are summed within the last integrator of the delta-sigma loop filter. This eliminates the need for an analog summation amplifier at the output of the delta-sigma loop filter. Behavioral and circuit-level simulation results confirm that the proposed feedforward CT delta-sigma modulator with NTF enhancement has improved noise-shaping and stability characteristics, as compared to classical CT delta-sigma modulators.<br>Une technique est présentée pour la conception du modulateur delta-sigma en temps continu (CT) ordre-haut avec amélioration de la fonction de transfert du bruit (NTF). Cette amélioration est obtenue par injection du bruit de quantification dans la chemin feedforward du modulateur delta-sigma CT, via un filtre passif CT. Ce filtre passif introduit une paire de pôle-zéro réel dans la NTF. Donc, l'ordre de la NTF est augmenté, sans affecter la fonction de transfert du signal (STF). La technique proposé pour l'amélioration de la NTF est appliquée à un modulateur delta-sigma CT avec une architecture feedforward-capacitive, où tous les chemins feedforward sont ajoutée dans le dernier intégrateur du filtre de boucle delta-sigma . Ceci élimine la nécessité d'un amplificateur de sommation analogique à la sortie du filtre de boucle delta-sigma. Les résultats de simulation du comportement et niveau circuit confirment que la proposition du modulateur delta-sigma CT feedforward avec amélioration de la NTF a permis d'améliorer le bruit-façonnement et les caractéristiques de stabilité, par rapport aux modulateurs delta-sigma CT classiques.
6
Zare-Hoseini, Hashem. "Continuous-Time Delta-Sigma Modulators with Immunity to Clock-Jitter." Thesis, University of Westminster, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500545.
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Jiang, Yang. "Clock-jitter insensitive circuit techniques in continuous-time sigma-delta modulators." Thesis, University of Macau, 2012. http://umaclib3.umac.mo/record=b2590641.
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Lee, Hyunjoo Jenny. "The effects of excess loop delay in continuous-time sigma-delta modulators." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/36787.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 79-80).<br>Continuous-time sigma-delta (CT-Sigma Delta) modulators have recently received great attention in the academia as well as in the industry. Despite the improved understanding of the operation of CT-Sigma Delta modulators, the problem due to excess loop delay that arises from timing mismatch and parasitic delay still remains unsolved. Thus, the thesis investigates the effects of the excess loop delay. In specific, the sensitivity of various CT-Sigma Delta topologies to the excess loop delay is explored by converting the CT modulators to its DT equivalents and realizing loop filters in state-space representations in MATLAB ©.<br>by Hyunjoo Jenny Lee.<br>M.Eng.
9
Thandri, Bharath Kumar. "Design of RF/IF analog to digital converters for software radio communication receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.
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Software radio architecture can support multiple standards by performing analogto-
digital (A/D) conversion of the radio frequency (RF) signals and running
reconfigurable software programs on the backend digital signal processor (DSP). A
slight variation of this architecture is the software defined radio architecture in which the
A/D conversion is performed on intermediate frequency (IF) signals after a single down
conversion.
The first part of this research deals with the design and implementation of a
fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters
for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC
architecture is proposed which uses only non-return to zero feedback digital to analog
converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz
and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ±
1.25 V supply.
The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF
digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA
architecture combines both cross coupling and source degeneration in order to obtain
good IM3 performance. A system level digital tuning scheme is proposed to tune the
ADC performance over process, voltage and temperature variations. The output bit
stream of the ADC is captured using an external DSP, where a software tuning algorithm
tunes the ADC parameters for best SNR performance. The IF ADC was designed in
TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V
supply.
10
Cherry, James A. "Theory, practice, and fundamental performance limits of high-speed data conversion using continuous-time delta-sigma modulators." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ37061.pdf.
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Amayreh, Mohammad Abdeljaleel [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "Sub-pA fully integrated CMOS current-mode continuous-time delta-sigma modulators for biological nanopore read-out." Freiburg : Universität, 2019. http://d-nb.info/1191689492/34.
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PATEL, VIPUL J. "BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.
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Samid, Lourans. "The design of low power and low voltage continuous time sigma-delta modulators with single bit and multibit quantizer /." [S.l. : s.n.], 2004. http://swbplus.bsz-bw.de/bsz115637230abs.htm.
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Atac, Aytac [Verfasser], Stefan [Akademischer Betreuer] Heinen, and Jürgen [Akademischer Betreuer] Oehm. "Design of Low Power Reconfigurable Continuous Time Quadrature Bandpass $\Delta$ $\Sigma$ ADCs for Multi-Standard SoC / Aytac Atac ; Stefan Heinen, Jürgen Oehm." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1157016251/34.
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Lu, Cho-Ying. "Calibrated Continuous-Time Sigma-Delta Modulators." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7914.
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To provide more information mobility, many wireless communication systems such
as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication
networks have been recently developed. Recent efforts have been made to build the allin-
one next generation device which integrates a large number of wireless services into a
single receiving path in order to raise the competitiveness of the device. Among all the
receiver architectures, the high-IF receiver presents several unique properties for the
next generation receiver by digitalizing the signal at the intermediate frequency around a
few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols,
equalization, etc., are all determined in a software platform that runs in the digital signal
processor (DSP) or FPGA. The specifications for most of front-end building blocks are
relaxed, except the analog-to-digital converter (ADC). The requirements of large
bandwidth, high operational frequency and high resolution make the design of the ADC
very challenging.
Solving the bottleneck associated with the high-IF receiver architecture is a major
focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to
accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture
employs an 800 MHz clock frequency. By making use of a unique software-based
calibration scheme together with the tuning properties of the bandpass filters developed
under the umbrella of this project, the ADC performance is optimized automatically to
fulfill all requirements for the high-IF architecture.
In a separate project, other critical design issues for continuous-time sigma-delta
ADCs are addressed, especially the issues related to unit current source mismatches in
multi-level DACs as well as excess loop delays that may cause loop instability. The
reported solutions are revisited to find more efficient architectures. The aforementioned
techniques are used for the design of a 25MHz bandwidth lowpass continuous-time
sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX
applications. The prototype is designed by employing a level-to-pulse-width modulation
(PWM) converter followed by a single-level DAC in the feedback path to translate the
typical digital codes into PWM signals with the proposed pulse arrangement. Therefore,
the non-linearity issue from current source mismatch in multi-level DACs is prevented.
The jitter behavior and timing mismatch issue of the proposed time-based methods are
fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak
SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts
and effectiveness of time-based quantization and feedback.
Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS
0.18um technologies, which are the most popular in today?s consumer electronics
industry.
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Tu, Ming-Hung, and 杜明鴻. "A 138.24MHz Continuous Time BandPass Sigma-Delta Modulator For Digital IF Application." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/94155799931582976824.
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碩士<br>淡江大學<br>電機工程學系<br>92<br>Analog to digital converters have been widely used in digital signal processing, and over-sampling and sigma-delta modulation techniques are used in analog to digital conversion interface of modern very large scaled integrated circuits. Due to over-sampling characteristics, the sigma-delta modulators usually are limited on the application of voice band signals. As the integrated circuit process improvement, it makes many researches transfer to applications of wide-bandwidth gradually, such as xDSL, Bluetooth, GSM ,and WCDMA.
Since cellular telephony made the transition from the first-generation analog systems to the second—generation (2G) digital systems less than a decade ago, mobile telecommunications have experienced tremendous growth. Today, several different 2G standards are used worldwide, of which the global system for mobile communication (GSM) has highest penetration. Driven by market forces, the number of second-generation subscribers is expected to increase further in the next few years. On the other hand, the demand for higher system capacity and data rates has led to the development of third-generation (3G) systems, which are in their final stage of standardization now and will be deployed in many parts of the world in the next couple of years. Dictated by the continuing popularity of exisited 2G services and the time needed to build up equivalent coverage, quality, and variety of service, a 3G cellular network requires multi-standard mobile terminals, to take advantage of both 2G and 3G services during the transition period.
In this thesis, we want to design a band-pass sigma-delta modulator suitable for WCDMA application. The center frequency is 100MHz, and the bandwidth is 3.84MHz.Because of the limitation on sampling frequency of the traditional switched-capacitor circuit (usually below 100MHz), even though double sampling or pseudo two-path techniques are used, the band-pass sigma-delta modulator’s center frequency is still below 50MHz.Therefore we use another approach continuous time circuit, to design the sigma-delta modulator. The impulse time invariant transformation is used to transfer the discrete time filter transfer function to the continuous-time filter transfer function. The continuous-time filter uses transconductance-capacitance circuits to fulfill the implementation. Its advantage is that it can work at a higher frequency band. In this manner, it can compensate the switched-capacitor circuit which cannot work at high the frequency band. Our circuit architecture is with multiple-feedback, its structure has two different one-bit digital-to-analog converters to control the feedback current.
Our proposed band-pass sigma-delta modulators for wireless receiver application whose operating voltage is 1.8V；the center frequency is 138.24MHz；the sampling frequency is 553MHz, and the oversampling ratio is 72. The simulation result show that the bandwidth is 3.84MHz；the sampling frequency is 553MHz；the dynamic input range is 60dB and the maximum signal to noise ratio is 56 dB. Its input signal is 0.2V；the effective resolution is 9.5bits, and the total power dissipation is 75mW.
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Chu, Hung-Yuan, and 瞿鴻遠. "Design Methodology and Verification of a Continuous-Time Bandpass Delta-Sigma Modulator." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/21214096656339513926.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>In the design flow of circuits, building the behavior models is very important. The behavior of the system can be simulated and the result can be verified in a short time by using a higher level platform and the simpler user interface. Designing the circuit after confirming the simulation results of a behavior model helps the designers avoid making too many mistakes.
From the searched literatures for the design of CT BP delta-sigma modulator, we found that some of them only focused on building a behavior model and others focused only on the circuit implementation. Almost none was found to consider both the behavior model and the physical implementation at the same time. Hence, we develop a top-down design flow using Simulink and Verilog-A for it to facilitate the design work.
This paper presents a design methodology of a continuous-time(CT) Band-pass(BP) delta-sigma modulator which can simplify the design procedure. The models were built in SIMULINK and Cadence’ s Spectre environment. Finally, the flow is used in the design of a CT BP delta-sigma modulator which is applied to a WCDMA communication system. The center frequency of this modulator is at 100MHz and the internal quantizer operated at 400MHz clock frequency. The modulator is simulated in TSMC 0.35μm CMOS technology, at a supply voltage of 3.3V. The maximum SNR is 38.6dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.
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Kim, Song-Bok [Verfasser]. "A contribution to continuous time quadrature bandpass sigma-delta modulators for low-IF receivers / vorgelegt von Song-Bok Kim." 2009. http://d-nb.info/994623410/34.
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Wang, Chi-Yun, and 王麒雲. "A Fourth-Order Continuous-Time Bandpass RF Delta-Sigma Modulator for GPS L1 Band Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19253569830398418196.
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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>This thesis describes the procedures from the system-level synthesis and design to circuit-level simulation and implementation of a fourth-order single-bit continuous-time bandpass RF delta-sigma ADC for GPS L1 band application. At least a 1.5-clock-cycle time slot is preserved in the modulator feedback path in the system-level design to relieve the speed requirements of quantizer comparison and DAC feedback. Thus, the excess loop delay and quantizer metastability issues usually occurred in GS/s-sampling delta sigma ADCs are both alleviated. Furthermore, only non-return-to-zero (NRZ) DACs are used in the modulator, the effect of clock jitter is mitigated. This ADC applies for direct digitization of the 1.57542-GHz GPS L1 band RF signal with a 6.297-GS/s sampling clock. A prototype ADC is fabricated in 65-nm SP CMOS technology. The circuit-level simulation results of the proposed ADC show a 61-dB signal-to-noise ratio (SNR) and a 62-dB input dynamic range (DR) over a 2-MHz signal bandwidth centered at 1.57542 GHz. The whole ADC consumes 29.85 mW under a 1-V supply voltage.
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Caldwell, Trevor C. "Time-interleaved continuous-time delta-sigma modulators." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=95010&T=F.
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Pulincherry, Anurag. "A continuous time frequency translating delta Sigma Modulator." Thesis, 2002. http://hdl.handle.net/1957/30250.
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This thesis presents a continuous time bandpass delta sigma modulator with
frequency translation inside the delta sigma loop. The input IF signal is down
converted to baseband after amplification by a low Q, wideband bandpass
resonator. The down converted IF signal is digitized by a continuous time, second
order lowpass delta sigma modulator. The output of the lowpass delta sigma
modulator is upconverted and fedback in to the low Q wideband bandpass
resonator. Unlike the conventional delta sigma modulators, sinusoidal pulses are
used for feedback. The system level design of the frequency translating delta sigma
modulator is discussed. A prototype frequency translating delta sigma modulator to
digitize IF signals at 100 MHz was designed in CMOS 0.35 μm process. Transistor
level simulation shows that 80 dB SNR is achievable at a power dissipation of 100
mW. The frequency translating delta sigma modulator is less sensitive to time delay
jitter in the DAC feedback pulse. If we use edge triggered sinusoid pulses for
feedback, the DAC jitter performance of frequency translating delta sigma
modulator will be better than that of conventional bandpass delta sigma modulator.<br>Graduation date: 2003
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"High performance ultra-low voltage continuous-time delta-sigma modulators." Thesis, 2011. http://library.cuhk.edu.hk/record=b6075115.
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Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply.<br>Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply.<br>In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise.<br>The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions.<br>The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C.<br>Chen, Yan.<br>Adviser: Kong Pang Pun.<br>Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: .<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.<br>Includes bibliographical references (leaves 127-135).<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Abstract also in Chinese.
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Weng, Chan-Hsiang, and 翁展翔. "Design of Continuous-Time Delta-Sigma Modulators for Wireless Applications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/72068133171218991762.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>96<br>In the first work, a dual-mode second-order continuous-time delta-sigma ADC is designed and implemented. In order to achieve low-voltage, and low-power design, the sliding quantizer is implemented to save the number of the comparator. The resonator is also included to adjust the center frequency of the signal to achieve low-pass and band-pass operation. This modulator is implemented in the TSMC 0.13-μm COMS process. The simulated peak SNR of the proposed modulator achieves more than 60-dB with 1-MHz bandwidth at a 60-MHz sampling rate. The center frequency is about 0 MHz (low-pass mode) and 2 MHz (band-pass mode). The implemented modulator consumes 2 mW from a 1.2-V supply.
Designed for a wide-band application, a second-order multi-bit continuous-time delta-sigma modulator is presented in the second part of this thesis. In the modulator, in order to compensate for the excess loop delay, a passive compensation technique is proposed. The additional compensation path in the modulator can compensate for the movement of poles and zeros that caused by excess loop delay. The fast compensation circuits stabilize the system when the modulator operates in high speed state. This delta-sigma modulator is implemented in the TSMC 0.13-μm COMS process. The proposed modulator achieves a 36-dB peak SNR with a 15-MHz bandwidth at a 500-MHz sampling rate and has a 38-dB dynamic range. The implemented modulator consumes 36 mW from a 1.2-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless wideband systems.
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Weng, Chan-Hsiang, and 翁展翔. "Design of Highly Energy-Efficient Continuous-Time Delta-Sigma Modulators." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/08204348140793390453.
Full textAbstract:
博士<br>國立臺灣大學<br>電子工程學研究所<br>103<br>To achieve highly energy-efficient designs of continuous-time delta-sigma modulators (CTDSMs), the thesis proposes several new techniques and applies those to the loop filter, quantizer and linearization circuits used in the feedback DAC. In the first part of the thesis, a power-efficient CTDSM employing a single-amplifier biquad (SAB)-based loop filter topology and a time-domain quantizer is proposed. With single amplifier and the modified twin-T passive feedback network, the proposed SAB-based loop filter can achieve 2nd-order resonating function and feedforward path concurrently. By choosing the feedback node properly, the excess loop delay compensation path can be realized without additional hardware. Meanwhile, to resolve the nonlinearity issue of feedback DAC and lower the power consumption of the quanitzer, a time-domain quantizer embedded with data-weighted-averaging (DWA) function is proposed to replace a flash-type quantizer and DWA shuffling logics. The proposed quantizer can digitize the analog output signal of the loop filter and linearize the feedback digital-to-analog converter concurrently. Based on the first design, the second part of the thesis proposed a CTDSM employing a 2-step time-domain quantizer to further reduce the power consumption and hardware cost. In the third part of the thesis, the CTDSM adopted two SAB-baed filters with two different T networks to achieve the 4th-order noise shaping. A flash-type quantizer with the interpolating technique is used to digitize output of the loop filter. Furthermore, a random-skipped incremental data weighted averaging (RS-IDWA) function is proposed to address the linearity issue of quantizer and feedback DAC.
Fabricated in 90-nm CMOS and operated at 300MHz, 256MHz and 320MHz, the proposed CTDSMs can achieve peak SNDR of 67.2 dB, 69.6 dB, and 68.1 dB over a 8.5 MHz, 8 MHz and 13 MHz signal bandwidth, respectively.
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Weng, Chan-Hsiang. "Design of Continuous-Time Delta-Sigma Modulators for Wireless Applications." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2801200815362500.
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Zhang, Bo. "Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs." Thesis, 1996. http://hdl.handle.net/1957/34675.
Full textAbstract:
Delta-sigma modulators are currently a very popular technique for making high-resolution
analog-to-digital and digital-to-analog converters. These oversampled data
converters have several advantages over conventional Nyquist-rate converters, including
an insensitivity to many analog component imperfections, a simpler antialiasing filter and
reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma
modulators were in the audio field, the development of bandpass modulators opened
up the application range to radar systems, digital communication systems and instruments
which convert IF, or even RF, analog signals directly to digital form.
This thesis presents a method used to analyze and synthesize continuous-time
delta-sigma modulators for given specifications. A fourth-order prototype continuous-time
bandpass delta-sigma modulator employing g[subscript m]-LC resonator structure is demonstrated on
a PCB board and measurement results corroborate the theory. To allow the construction of
very high performance delta-sigma modulators, this thesis presents an architecture for a
multibit DAC constructed from unit elements which shapes element mismatches. Theoretical
analysis and simulation shows that this architecture greatly increases the noise attenuation
in the band-of-interest and facilitates the use of multibit quantization in delta-sigma
modulators. The methods presented in this thesis will allow high-frequency wideband
bandpass delta-sigma modulators to be constructed.<br>Graduation date: 1996
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Gao, Xiaoran. "A survey on continuous-time [delta sigma] modulators : theory, designs and implementations /." 2008. http://hdl.handle.net/1957/8386.
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Lin, Yen-Jung, and 林彥榕. "The Continuous-Time Capacitive Feedforward Sigma-Delta Modulators Chip Design for Wireless Communication." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/qjjhs7.
Full textAbstract:
碩士<br>國立臺灣科技大學<br>電子工程系<br>99<br>With increasing development of wireless communication systems, there is a large demand in the wireless communication for analog-to-digital converters (ADCs) that require signal bandwidths of several megahertz. Sigma-delta modulators (ΣΔ modulators) are ideally suitable for such applications. Compared to the discrete-time switched capacitor circuit implementations, continuous-time (CT) ΣΔ modulators have the potentials for wider bandwidth and are also inherent anti-aliasing.
In this thesis, two CT ΣΔ modulators were designed and fabricated. The first one is the complex bandpass ΣΔ modulator for WiMAX application. Capacitive feedforward are employed for frequency compensation. Capacitive feedforward is a simple solution compared to conventional CIFF (chain of integrators with weighted feedforward summation) topology. Clock at 160 MHz, The modulator achieved a measured dynamic range of 46 dB over a 10 MHz signal bandwidth, SNDR of 37 dB, IM3 of -44 dB. The measured power dissipation is 41.5 mW from a 1.8 V supply voltage. Including pads, the chip occupies 1.7947 (1.31 x 1.37) mm2.
Although ΣΔ modulators tolerate to imperfection of analog circuit, the decimation and filtering of the output stream of ΣΔ modulators are necessary. In addition, the performance of bandpass ΣΔ modulators is not interfered by low frequency noise, however, downconversion of the output stream in digital domain is needed. To demonstrate a complete complex bandpass ΣΔ ADC, decimation filter for complex bandpass ΣΔ modulator is designed and simulation results are given.
The second modulator chip is the CT ΣΔ modulator with a hybrid active-passive loop filter for WCDMA application. This 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. Also, to erase the summation amplifier used in the CIFF topology, the capacitive feedforward structure is also employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 um 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of -48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 x 0.6) mm2
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Huang, Bi-Ching, and 黃必青. "Design of Continuous-Time Delta-Sigma Modulators with SAR Quantizers Employing Noise-Shaping Concept." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/79404175661356201193.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>101<br>This thesis consists of two works. The first work is a low-power continuous-time delta-sigma modulator (CTDSM), which consists of a 3rd-order feed-back and feed-forward combined loop filter structure, a 5-bit quantizer with 2 bits truncated by a truncator and embedded with a noise-shaping mechanism. The second work presents a CTDSM with a 2nd-order feed-forward loop filter structure and a 3-bit noise-shaped SAR quantizer, leading to an equivalent 3rd-order noise shaping, which improves the overall resolution of the modulator.
A 5-bit, low-power CTDSM embedded with a noise-shaped and truncated SAR quantizer is proposed in the first work. The bit truncation reduces the number of feedback DAC cells and relaxes the implementation of DEM circuit while the delay introduced by the 2-LSB signal is swallowed by the truncation process. Implemented in a 90-nm CMOS process, the measured performance shows a peak SNDR of 67.23 dB over a signal bandwidth of 1.92 MHz with 61.44 MHz sampling frequency. This modulator consumes a total power of 2.25 mW, resulting in an FoM of 312 fJ/Conversion-Step.
A low-power CTDSM with a 3-bit noise-shaped SAR quantizer is studied in the second work. The noise-shaped quantizer gives an extra-order of noise shaping to the modulator, resulting in a 3-bit 3rd-order delta-sigma modulator. This modulator was realized in a 0.18-um CMOS technology. Under a power supply of 1.8 V and a sampling frequency of 32 MHz, the measured performance shows a peak SNDR of 70.23 dB over a signal bandwidth of 1 MHz and an FoM of 470 fJ/Convsion-Step. The modulator consumes a total power of 2.47 mW.
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Gadde, Venkata Veera Satya Sair. "Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC." 2009. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7430.
Full textAbstract:
Continuous-time filters are critical components in the implementation of large bandwidth, high frequency, and high resolution continuous-time (CT) sigma-delta (ΣΔ) analog-to-digital converters (ADCs). The loop filter defines the noise-transfer function (NTF) and hence the quantization noise-shaping behavior of the ΣΔ modulator, and becomes the most critical performance determining part in ΣΔ ADC.
This thesis work presents the design considerations for the loop filter in low-pass CT ΣΔ ADC with 12-bits resolution in 25MHz bandwidth and low power consumption using 0.18μm CMOS technology. Continuous-time filters are more suitable than discrete-time filters due to relaxed amplifier bandwidth requirements for high frequency ΣΔ ADCs. A fifth-order low-pass filter with cut-off frequency of 25 MHz was designed to meet the dynamic range requirement of the ADC. An active RC topology was chosen for the implementation of the loop filter, which can provide high dynamic range required by the ΣΔ ADC. The design of a summing amplifier and a novel method for adjusting the group delay in the fast path provided by a secondary feedback DAC of the ΣΔ ADC are presented in detail. The ADC was fabricated using Jazz 0.18μm CMOS technology.
The implementation issues of OTAs with high-linearity and low-noise performance suitable for the broadband ADC applications are also analyzed in this work. Important design equations pertaining to the linearity and noise performance of the Gm-C biquad filters are presented. A Gm-C biquad with 100MHz center frequency and quality factor 10 was designed as a prototype to confirm with the theoretical design equations. Transistor level circuit implementation of all the analog modules was completed in a standard 0.18μm CMOS process.
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Song, Tongyu. "Design trade-off of low power continuous-time [Sigma Delta] modulators for A/D conversions." Thesis, 2007. http://hdl.handle.net/2152/3698.
Full textAbstract:
The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.
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Cheng, Fu-Yuan, and 鄭富元. "Improved Stability of High-Order Continuous-Time Sigma-Delta Modulators with Modified Loop Filters and Efficient Synthesis." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/62926402145784929388.
Full textAbstract:
碩士<br>國立中正大學<br>電機工程研究所<br>103<br>The continues-time sigma-delta convertor has advantages on wideband applications. Noise shaping can be obviously observed by increasing the order and obtained a high resolution with a low oversampling rate. On the other hand, higher order systems suffer from stability problems and the system performance may compromised especially that the continues-time sigma-delta modulator has to consider the excess loop delay.
The thesis presented a continuous-time delta-sigma modulator with 10MHz bandwidth. The structure of continuous-time delta-sigma modulator included 4th order active rc integrator and 4bits quantizer. This thesis improves the stability of the continuous-time sigma-delta modulator. First of all, the coefficients are efficiency synthesized and compensated in the S domain based on the out of band gain and root locus modification. The stability and the dynamic range are improved.
To compensate the excess delay on the analog integrator in the loop filter, the modified stack structure is proposed. The internal differential path in the loop filter is utilized for the excess loop delay compensation for the DAC. The coefficient zero compensate is employed to fulfill the ELD compensating coefficients degraded on the differential path of the resonator. The sampling rate is 280MHz and the SNDR is 83.635dB. The chip is fabricated in TSMC 0.18um process.
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Wang, Yan. "Design techniques for wideband low-power Delta-Sigma analog-to-digital converters." Thesis, 2009. http://hdl.handle.net/1957/13664.
Full textAbstract:
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT
structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart.
In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth.
For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications.
For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications.
Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected.<br>Graduation date: 2010
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"An IF-input quadrature continuous-time multi-bit [delta][sigma] modulator with high image and non-linearity suppression for dual-standard wireless receiver application." 2008. http://library.cuhk.edu.hk/record=b5896763.
Full textAbstract:
Ko, Chi Tung.<br>On t.p. "delta" and "sigma" appear as the Greek letters.<br>Thesis submitted in: December 2007.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.<br>Includes bibliographical references.<br>Abstracts in English and Chinese.<br>Abstract --- p.1<br>摘要 --- p.3<br>Acknowledgements --- p.4<br>Table of Contents --- p.5<br>List of Figures --- p.8<br>List of Tables --- p.13<br>Chapter Chapter 1 --- Introduction --- p.14<br>Chapter 1.1 --- Motivation --- p.14<br>Chapter 1.2 --- Objectives --- p.17<br>Chapter 1.3 --- Organization of the Thesis --- p.17<br>References --- p.18<br>Chapter Chapter 2 --- Fundamentals of Delta-sigma Modulators --- p.20<br>Chapter 2.1 --- Delta-sigma Modulator as a Feedback System --- p.20<br>Chapter 2.2 --- Quantization Noise --- p.22<br>Chapter 2.3 --- Oversampling --- p.23<br>Chapter 2.4 --- Noise Shaping --- p.25<br>Chapter 2.5 --- Performance Parameters --- p.27<br>Chapter 2.6 --- Baseband Modulators vs Bandpass Modulators --- p.27<br>Chapter 2.7 --- Discrete-time Modulators vs Continuous-time Modulators --- p.28<br>Chapter 2.8 --- Single-bit Modulators vs Multi-bit Modulators --- p.29<br>Chapter 2.9 --- Non-linearity and Image Problems in Multi-bit Delta-sigma Modulators --- p.29<br>Chapter 2.9.1 --- Non-linearity Problem --- p.29<br>Chapter 2.9.2 --- Image Problem --- p.31<br>Reference --- p.36<br>Chapter Chapter 3 --- Image Rejection and Non-linearity Suppression Techniques for Quadrature Multi-bit Δ¡♭ Modulators --- p.38<br>Chapter 3.1 --- Quadrature DEM Technique --- p.38<br>Chapter 3.1.1 --- Introduction and Working Principle --- p.38<br>Chapter 3.1.2 --- Behavioral Simulation Results --- p.42<br>Chapter 3.2 --- IQ DWA Technique --- p.44<br>Chapter 3.2.1 --- Introduction and Working Principle --- p.44<br>Chapter 3.2.2 --- Behavioral Simulation Results --- p.49<br>Chapter 3.3 --- DWA and Bit-wise Data-Dependent DEM --- p.52<br>Chapter 3.3.1 --- Introduction and Working Principle --- p.52<br>Chapter 3.3.2 --- Behavioral Simulation Results --- p.54<br>Chapter 3.4 --- Image Rejection Technique for Quadrature Mixer --- p.61<br>Chapter 3.5 --- Conclusion --- p.63<br>Reference --- p.64<br>Chapter Chapter 4 --- System Design of a Multi-Bit CT Modulator for GSM/WCDMA Application --- p.65<br>Chapter 4.1 --- Objective of Design and Design Specification --- p.65<br>Chapter 4.2 --- Topology Selection --- p.65<br>Chapter 4.3 --- Discrete-time Noise Transfer Function Generation --- p.66<br>Chapter 4.4 --- Continuous-time Loop Filter Transfer Function Generation --- p.69<br>Chapter 4.5 --- Behavioral Model of Modulator --- p.69<br>Chapter 4.6 --- Dynamic Range Scaling --- p.75<br>Chapter 4.7 --- Behavioral Modeling of Operational Amplifiers --- p.77<br>Chapter 4.8 --- Impact of RC Variation on Performance --- p.85<br>Chapter 4.9 --- Loop Filter Component Values --- p.88<br>Chapter 4.10 --- Summary --- p.90<br>Reference --- p.90<br>Chapter Chapter 5 --- Transistor-level Implementation of Modulators --- p.92<br>Chapter 5.1 --- Overview of Design --- p.92<br>Chapter 5.2 --- Design of Operational Transconductance Amplifiers (OTAs) --- p.94<br>Chapter 5.2.1 --- First Stage --- p.94<br>Chapter 5.2.2 --- Second and Third Stages --- p.98<br>Chapter 5.3 --- Design of Feed-forward Transconductance (Gm) Cells --- p.101<br>Chapter 5.4 --- Design of Quantizer --- p.102<br>Chapter 5.4.1 --- Reference Ladder Design --- p.102<br>Chapter 5.4.2 --- Comparator Design --- p.104<br>Chapter 5.5 --- Design of Feedback Digital-to-Analog Converter (DAC) --- p.106<br>Chapter 5.5.1 --- DWA and DEM Logic --- p.107<br>Chapter 5.5.2 --- DAC Circuit --- p.109<br>Chapter 5.6 --- Design of Integrated Mixers --- p.111<br>Chapter 5.7 --- Design of Clock Generators --- p.112<br>Chapter 5.7.1 --- Master Clock Generator --- p.112<br>Chapter 5.7.2 --- LO Clock Generator --- p.114<br>Chapter 5.7.3 --- Simulation Results --- p.116<br>Reference --- p.125<br>Chapter Chapter 6 --- Physical Design of Modulators --- p.127<br>Chapter 6.1 --- Floor Planning of Modulator --- p.127<br>Chapter 6.2 --- Shielding of Sensitive Signals --- p.130<br>Chapter 6.3 --- Common Centroid Layout --- p.130<br>Chapter 6.4 --- Amplifier Layout --- p.132<br>Reference --- p.137<br>Chapter Chapter 7 --- Conclusions --- p.138<br>Chapter 7.1 --- Conclusions --- p.138<br>Chapter 7.2 --- Future Works --- p.138<br>Appendix A Schematics of Building Blocks --- p.140<br>First Stage Operational Amplifier --- p.140<br>First Stage Amplifier Local Bias Circuit --- p.140<br>Second and Third Stage Operational Amplifier --- p.141<br>Second and Third Stage Local Bias Circuit --- p.141<br>CMFB Circuit (First Stage) --- p.142<br>CMFB Circuit (Second Stage) --- p.142<br>Gm-Feed-forward Cells --- p.143<br>Gm Feed-forward Cell Bias Circuit --- p.143<br>Reference Ladder Circuit --- p.144<br>Pre-amplifier Circuit --- p.145<br>Latch Circuit --- p.145<br>DAC Circuit (Unit Cell) --- p.146<br>Author's Publications --- p.147
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Ahmed, Ramy 1981. "Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers." Thesis, 2012. http://hdl.handle.net/1969.1/148047.
Full textAbstract:
The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (ΔƩ) ADCs show up as an attractive option. CT ΔƩ ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ΔƩ ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ΔƩ modulators in presence of OOB blockers. Also, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock.
In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ΔƩ modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn’t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719µwatts from 1.3V supply.