Relevant bibliographies by topics / Continuous-time Delta-Sigma modulator

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Continuous-time Delta-Sigma modulator'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

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Journal articles on the topic "Continuous-time Delta-Sigma modulator"

1

Zorn, C., T. Brückner, M. Ortmanns, and W. Mathis. "State scaling of continuous-time sigma-delta modulators." Advances in Radio Science 11 (July 4, 2013): 119–23. http://dx.doi.org/10.5194/ars-11-119-2013.

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Abstract. In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the maximum out-of-band gain directly in continuous time. In addition, the input amplitude distribution between each quantization level of multi bit sigma-delta modulator can be adapted.
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Le Guillou, Y., and H. Fakhoury. "Elliptic filtering in continuous-time sigma-delta modulator." Electronics Letters 41, no. 4 (2005): 167. http://dx.doi.org/10.1049/el:20057874.

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Colodro, F., A. Torralba, and M. Laguna. "Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 3 (April 2008): 775–85. http://dx.doi.org/10.1109/tcsi.2008.919764.

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Tamaddon, Mohsen, and Mohammad Yavari. "An NTF-enhanced time-based continuous-time sigma-delta modulator." Analog Integrated Circuits and Signal Processing 85, no. 2 (May 24, 2015): 283–97. http://dx.doi.org/10.1007/s10470-015-0562-7.

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Keller, M., A. Buhmann, M. Kuderer, and Y. Manoli. "On the synthesis and optimization of cascaded continuous-time Sigma-Delta modulators." Advances in Radio Science 4 (September 6, 2006): 293–97. http://dx.doi.org/10.5194/ars-4-293-2006.

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Abstract. Up to now, there exist two completely different approaches for the synthesis of cascaded CT Sigma-Delta modulators. While the first method is based on a DT prototype and thus on the application of a DT-to-CT transformation, the second one is entirely performed in the CT domain. In this contribution, the method of lifting will be applied to overcome the disadvantages afflicted with the first method (e.g. less ideal anti-aliasing filter performance, increased circuit complexity) and to establish a time efficient DT simulation model for the second method. Thereby, optimal modulator coefficients as well as optimal digital cancellation filters for an arbitrary cascaded CT modulator can be simulated in an efficient and rapid manner. For illustrative purposes, the complete synthesis procedure is demonstrated by the example of a 2-1-1 cascaded CT modulator.
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Zhao, Feng, Hong Gao, Lin Xing, Yasunori Kobori, Shu Wu, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker, and Nobukazu Takai. "Continuous-Time Delta-Sigma Controller for DC-DC Converter." Key Engineering Materials 643 (May 2015): 53–59. http://dx.doi.org/10.4028/www.scientific.net/kem.643.53.

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This paper describes applications of a Delta-Sigma (ΔΣ) modulator to control a DC-DC converter. We propose to use a continuous-time (CT) feed-forward (FF) ΔΣ controller in a DC-DC converter and show that its transient response is faster than discrete-time (DT) and/or feedback-type (FB) ΔΣ controllers. We have also performed experiments of a DC-DC converter with a first-order continuous-time feedback ΔΣ controller and show its results.
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Lee, Kwangchun, Bonghyuk Park, Seunghyun Jang, Jaeho Jung, and Kyoungrok Cho. "Tunable continuous-time ^|^Delta;^|^Sigma; modulator for switching power amplifier." IEICE Electronics Express 9, no. 22 (2012): 1714–19. http://dx.doi.org/10.1587/elex.9.1714.

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Ucar, Alper, Ediz Cetin, and Izzet Kale. "A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers." IEEE Transactions on Circuits and Systems II: Express Briefs 59, no. 5 (May 2012): 272–76. http://dx.doi.org/10.1109/tcsii.2012.2190860.

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Chavoshisani, Reza, and Omid Hashemipour. "Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator." Journal of Low Power Electronics 13, no. 2 (June 1, 2017): 249–54. http://dx.doi.org/10.1166/jolpe.2017.1481.

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Gupta, Anshu, Lalita Gupta, and R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.
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Dissertations / Theses on the topic "Continuous-time Delta-Sigma modulator"

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Yang, Xi S. M. Massachusetts Institute of Technology. "Design of a continuous-time bandpass delta-sigma modulator." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87939.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 103-105).
An 8th-order continuous-time (CT) bandpass delta-sigma modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signal-to- noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order system, achieving a maximum stable input range of -1.9 dBFS. A 2.5-V/1.2-V dual-supply loop filter with a feed-forward coupling path has been proposed to suppress noise and distortion. On the transistor level, a 5th -order dual-supply feed-forward operational amplifier (op amp) and a 4th-order single-supply feed-forward op amp have been designed to enable high modulator linearity and coefficient accuracy.
by Xi Yang.
S.M.
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Ding, Chongjun [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "Design study of high-speed continuous-time delta-sigma modulator." Freiburg : Universität, 2016. http://d-nb.info/1122647026/34.

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Juang, Philip Weimin 1978. "A continuous time sigma-delta modulator for digitizing carrier band measurements." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86681.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 135-136).
by Philip Weimin Juang.
M.Eng.
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Chu, Chao [Verfasser]. "A high speed/high linearity continuous-time delta-sigma modulator / Chao Chu." Ulm : Universität Ulm, 2017. http://d-nb.info/1147848033/34.

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Chi, Jiazuo. "Micro-Power Inverter-Based Continuous-Time Sigma-Delta Modulator for Biosensor Applications." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177367.

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Biosensor applications have made promising progress during the last decade, presenting potentials and challenges at the same time. Meanwhile, digital signal processing (DSP) has become even more powerful than before, due to Moore's Law. Bridging the biosensor applications and the digital circuits, analog-to-digital converters (ADCs) are a critical block that inuences the performance of the entire system, in terms of speed, accuracy and power. Particularly, incremental ΣΔ (IΣΔ) ADCs have recently received increasing research interest because of their high-resolution feature and the ability to time-multiplex different channels of input signals, making them especially suitable for neuro-science studies and brain-computer-interface (BCI). However, IΣΔ ADCs are less power-ecient than traditional ΣΔ ADCs. To improve the power eciency and reduce the chip size, an inverter-based continuous-time (CT) Sigma-Delta (ΣΔ) modulator is proposed, to be integrated in a two-step I(ΣΔ) ADC previously designed. Inverter-based operational transconductance amplifers (OTA) have recently demonstrated their high power efficiency in multiple ΣΔ modulators, most of which are discrete-time (DT) implementation. CT implementation is investigated in this thesis for the possibility to further reduce power consumption, due to its more relaxed requirements on bandwidth and settling compared to the DT counterpart. In the circuit implementation of the modulator, fully-differential topology is used in inverter-based CT ΣΔ ADCs for the rst time. Compared to pseudo-differential topology, fully-differential topology has more precise control on the operating point and the quiescent power. The post-layout simulation result shows that the modulator achieves a peak SNDR of 58.1 dB, and a dynamic range of 65.9 dB. The entire modulator consumes 1.28 μW from a 1.2 V supply voltage, on a chip area of only 0.07 mm2. This corresponds to a FoM of 243 fJ/(conv. step).
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Yoon, Do Yeon. "A continuous-time multi-stage noise-shaping delta-sigma modulator with analog delay." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75689.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 73-75).
A new continuous-time multi-stage noise-shaping delta-sigma modulator has been designed. This modulator provides high resolution and robust stability characteristics which are the primary advantages of the conventional multi-stage noise-shaping architecture. At the same time, previous critical challenges that degraded the overall performance of multi-stage noise-shaping delta-sigma modulators are eliminated through several unique techniques. Additionally, these techniques relax the requirements of each component of the proposed delta-sigma modulator. As a result, this new delta-sigma modulator architecture can provide several advantages that are not obtainable in other modulator architectures.
by Do Yeon Yoon.
S.M.
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7

Pěček, Lukáš. "Návrh Sigma Delta AD převodníku pro senzorové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-317221.

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This diploma thesis deals with the design of a sigma delta AD converter for a sensor application of junction temperature measurement in the automotive environment. A modified continuous time current mode modulator structure was designed. Its advantage lies in shifting and extending an input voltage range to work with signals from 0 V to 1,2 with a high impedance input and a relatively low hardware complexity. The functionality was verified by a behavioral model in the Simulink environment and then by transistor level simulation in CADENCE environment using ONC18/I4T technology.
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Liu, Xuemei. "Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3257.

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Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.
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Melo, João Luís Alvernaz de. "Design of a Continuous-Time (CT) Sigma-Delta modulator for class D audio power amplifiers." Master's thesis, Faculdade de Ciências e Tecnologia, 2010. http://hdl.handle.net/10362/13154.

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Yoon, Do Yeon. "A continuous-time multi-stage noise-shaping delta-sigma modulator for next generation wireless applications." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99854.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 115-121).
A continuous-time (CT) delta-sigma ([delta][sigma]) modulator for modern wireless communication applications is investigated in this thesis. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function (NTF). In order to increase the effective order of the NTF, a 2-loop sturdy multi-stage noise-shaping (SMASH) architecture is utilized. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of the DT implementation. Furthermore, the proposed CT SMASH architecture provides a better quantization noise suppression capability than the DT SMASH architecture by more completely canceling the quantization noise from the first loop. The CT SMASH architecture is implemented with several circuit techniques suitable for high operation speed. These circuit techniques allow the proposed CT [delta][sigma] modulator to achieve wide bandwidth, high resolution, and low power consumption for modern wireless communication applications. As a result, the prototype fabricated in 28nm CMOS achieves DR of 85dB, peak SNDR of 74.9dB, SFDR of 89.3dBc and Schreier FOM of 172.9dB over a 50MHz bandwidth at a 1.8GHz sampling frequency.
by Do Yeon Yoon.
Ph. D.
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Books on the topic "Continuous-time Delta-Sigma modulator"

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7.

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1938-, Huijsing Johan H., ed. Continuous-time Sigma-Delta modulation for A/D conversion in radio receivers. Boston: Kluwer Academic Publishers, 2001.

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Cherry, James A. Continuous-time delta-sigma modulators for high-speed A/D conversion: Theory, practice and fundamental performance limits. New York: Kluwer Academic, 2002.

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Cherry, James A. Continuous-time delta-sigma modulators for high-speed A/D/ conversion: Theory, practice, and fundamental performance limits. Boston: Kluwer Academic Pub., 2000.

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Caldwell, Trevor C. Time-interleaved continuous-time delta-sigma modulators. 2004.

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Silva-Martinez, Jose, Qiyuan Liu, Alexander Edward, and Carlos Briseno-Vidrios. Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, 2018.

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Silva-Martinez, Jose, Qiyuan Liu, Alexander Edward, and Carlos Briseno-Vidrios. Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, 2018.

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Breems, Lucien. Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Springer, 2010.

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Zhang, Bo. Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs. 1996.

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Zhang, Bo. Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs. 1996.

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Book chapters on the topic "Continuous-time Delta-Sigma modulator"

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Bolatkale, Muhammed, Lucien J. Breems, and Kofi A. A. Makinwa. "Continuous-Time Delta-Sigma Modulator." In Analog Circuits and Signal Processing, 9–35. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05840-5_2.

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Kunamalla, Sarangam, and Bheema Rao Nistala. "A Low-Power Third-Order Passive Continuous-Time Sigma-Delta Modulator Using FinFET." In Lecture Notes in Electrical Engineering, 395–405. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7031-5_38.

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Huang, Jhin-Fang, Jiun-Yu Wen, and Wei-Chih Chen. "Chip Design of a Continuous-Time 5-MHz Low-Pass Sigma-Delta Modulator." In Proceedings of the 4th International Conference on Computer Engineering and Networks, 925–33. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-11104-9_106.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Delta-Sigma Modulators." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 19–33. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_3.

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van Engelen, Jurgen, and Rudy van de Plassche. "Design of Continuous Time Bandpass SDMS." In Bandpass Sigma Delta Modulators, 107–19. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4586-3_6.

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Xing, Xinpeng, Peng Zhu, and Georges Gielen. "Continuous-Time Delta-Sigma Modulators." In Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems, 37–66. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66565-8_3.

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Arnaldi, Isacco. "Continuous Time Sigma-Delta Modulators." In Design of Sigma-Delta Converters in MATLAB®/Simulink®, 153–80. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91539-5_7.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Design of Continuous-Time Delta-Sigma Modulators." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 35–76. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_4.

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Pereira, Nuno, João L. A. de Melo, and Nuno Paulino. "Design of a 3rd Order 1.5-Bit Continuous-Time Fully Differential Sigma-Delta (ΣΔ) Modulator Optimized for a Class D Audio Amplifier Using Differential Pairs." In IFIP Advances in Information and Communication Technology, 639–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-37291-9_69.

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Liu, Qiyuan, Alexander Edward, Carlos Briseno-Vidrios, and Jose Silva-Martinez. "Design of MASH Continuous-Time Delta-Sigma Modulators." In Design Techniques for Mash Continuous-Time Delta-Sigma Modulators, 77–100. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77225-7_5.

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Conference papers on the topic "Continuous-time Delta-Sigma modulator"

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Wang, Yanchao, Lukang Shi, Tao He, Yi Zhang, Chia-Hung Chen, and Gabor C. Temes. "Robust Continuous-Time MASH Delta Sigma Modulator." In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018. http://dx.doi.org/10.1109/mwscas.2018.8624017.

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Li, Yamei, and Lili He. "First-Order Continuous-Time Sigma-Delta Modulator." In 8th International Symposium on Quality Electronic Design (ISQED'07). IEEE, 2007. http://dx.doi.org/10.1109/isqed.2007.77.

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Lieu, Don T., and Thomas P. Weldon. "A 10MHz continuous time bandpass delta sigma modulator." In SOUTHEASTCON 2012. IEEE, 2012. http://dx.doi.org/10.1109/secon.2012.6196890.

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Nima Maghari, Changsok Han. "Continuous-Time Delta-Sigma Modulator with Time Domain Noise Coupling." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702754.

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Lin, Yung-Chou, Wen-Hung Hsieh, and Chung-Chih Hung. "A continuous-time delta-sigma modulator using feedback resistors." In 2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2009. http://dx.doi.org/10.1109/vdat.2009.5158140.

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Chen, Zong-Yi, and Chung-Chih Hung. "Jitter compensation technique for continuous-time sigma-delta modulator." In 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2014. http://dx.doi.org/10.1109/apccas.2014.7032809.

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Koppula, Rajaram Mohan Roy, Sakkarapani Balagopal, and Vishal Saxena. "Multi-bit continuous-time delta-sigma modulator for audio application." In 2012 IEEE Workshop on Microelectronics and Electron Devices (WMED). IEEE, 2012. http://dx.doi.org/10.1109/wmed.2012.6202620.

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U.K., Vijay, and Amrutur Bharadwaj. "Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture." In 2007 20th International Conference on VLSI Design. IEEE, 2007. http://dx.doi.org/10.1109/vlsid.2007.54.

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Ducu, Dragos, and Anca Manolescu. "A continuous time sigma delta modulator with operational floating integrator." In 2012 International Semiconductor Conference (CAS 2012). IEEE, 2012. http://dx.doi.org/10.1109/smicnd.2012.6400729.

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Liu, Tao, Sihuai Xie, and Peng Luo. "Continuous-Time Sigma-Delta Modulator Using 4-Bit SAR Quantizer." In 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2019. http://dx.doi.org/10.1109/edssc.2019.8753938.

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