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Journal articles on the topic 'Continuous-time Delta-Sigma modulator'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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1

Zorn, C., T. Brückner, M. Ortmanns, and W. Mathis. "State scaling of continuous-time sigma-delta modulators." Advances in Radio Science 11 (July 4, 2013): 119–23. http://dx.doi.org/10.5194/ars-11-119-2013.

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Abstract. In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the maximum out-of-band gain directly in continuous time. In addition, the input amplitude distribution between each quantization level of multi bit sigma-delta modulator can be adapted.

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2

Le Guillou, Y., and H. Fakhoury. "Elliptic filtering in continuous-time sigma-delta modulator." Electronics Letters 41, no. 4 (2005): 167. http://dx.doi.org/10.1049/el:20057874.

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3

Colodro, F., A. Torralba, and M. Laguna. "Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 3 (April 2008): 775–85. http://dx.doi.org/10.1109/tcsi.2008.919764.

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4

Tamaddon, Mohsen, and Mohammad Yavari. "An NTF-enhanced time-based continuous-time sigma-delta modulator." Analog Integrated Circuits and Signal Processing 85, no. 2 (May 24, 2015): 283–97. http://dx.doi.org/10.1007/s10470-015-0562-7.

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5

Keller, M., A. Buhmann, M. Kuderer, and Y. Manoli. "On the synthesis and optimization of cascaded continuous-time Sigma-Delta modulators." Advances in Radio Science 4 (September 6, 2006): 293–97. http://dx.doi.org/10.5194/ars-4-293-2006.

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Abstract. Up to now, there exist two completely different approaches for the synthesis of cascaded CT Sigma-Delta modulators. While the first method is based on a DT prototype and thus on the application of a DT-to-CT transformation, the second one is entirely performed in the CT domain. In this contribution, the method of lifting will be applied to overcome the disadvantages afflicted with the first method (e.g. less ideal anti-aliasing filter performance, increased circuit complexity) and to establish a time efficient DT simulation model for the second method. Thereby, optimal modulator coefficients as well as optimal digital cancellation filters for an arbitrary cascaded CT modulator can be simulated in an efficient and rapid manner. For illustrative purposes, the complete synthesis procedure is demonstrated by the example of a 2-1-1 cascaded CT modulator.

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6

Zhao, Feng, Hong Gao, Lin Xing, Yasunori Kobori, Shu Wu, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker, and Nobukazu Takai. "Continuous-Time Delta-Sigma Controller for DC-DC Converter." Key Engineering Materials 643 (May 2015): 53–59. http://dx.doi.org/10.4028/www.scientific.net/kem.643.53.

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This paper describes applications of a Delta-Sigma (ΔΣ) modulator to control a DC-DC converter. We propose to use a continuous-time (CT) feed-forward (FF) ΔΣ controller in a DC-DC converter and show that its transient response is faster than discrete-time (DT) and/or feedback-type (FB) ΔΣ controllers. We have also performed experiments of a DC-DC converter with a first-order continuous-time feedback ΔΣ controller and show its results.

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7

Lee, Kwangchun, Bonghyuk Park, Seunghyun Jang, Jaeho Jung, and Kyoungrok Cho. "Tunable continuous-time ^|^Delta;^|^Sigma; modulator for switching power amplifier." IEICE Electronics Express 9, no. 22 (2012): 1714–19. http://dx.doi.org/10.1587/elex.9.1714.

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8

Ucar, Alper, Ediz Cetin, and Izzet Kale. "A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers." IEEE Transactions on Circuits and Systems II: Express Briefs 59, no. 5 (May 2012): 272–76. http://dx.doi.org/10.1109/tcsii.2012.2190860.

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9

Chavoshisani, Reza, and Omid Hashemipour. "Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator." Journal of Low Power Electronics 13, no. 2 (June 1, 2017): 249–54. http://dx.doi.org/10.1166/jolpe.2017.1481.

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10

Gupta, Anshu, Lalita Gupta, and R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

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11

Cai, H., H. Petit, and J. F. Naviner. "Reliability aware design of low power continuous-time sigma–delta modulator." Microelectronics Reliability 51, no. 9-11 (September 2011): 1449–53. http://dx.doi.org/10.1016/j.microrel.2011.06.054.

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12

Pavan, Shanthi. "Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 6 (June 2014): 1629–37. http://dx.doi.org/10.1109/tcsi.2013.2290846.

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13

Hernández, L., E. Pun, E. Prefasi, and S. Paton. "Continuous time sigma-delta modulator based on binary weighted charge balance." Electronics Letters 45, no. 9 (2009): 458. http://dx.doi.org/10.1049/el.2009.0323.

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14

Taylor, Gerry, and Ian Galton. "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC." IEEE Journal of Solid-State Circuits 45, no. 12 (December 2010): 2634–46. http://dx.doi.org/10.1109/jssc.2010.2073193.

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15

Cai, Hao, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, and Jean-François Naviner. "Cross-layer investigation of continuous-time sigma–delta modulator under aging effects." Microelectronics Reliability 55, no. 3-4 (February 2015): 645–53. http://dx.doi.org/10.1016/j.microrel.2014.11.015.

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16

Anand, Awinash, Nischal Koirala, Ramesh K. Pokharel, Haruichi Kanaya, and Keiji Yoshida. "Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator." International Journal of Microwave Science and Technology 2013 (March 7, 2013): 1–5. http://dx.doi.org/10.1155/2013/275289.

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Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

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17

Matsukawa, Kazuo, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, and Akira Matsuzawa. "A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator." IEEE Journal of Solid-State Circuits 45, no. 4 (April 2010): 697–706. http://dx.doi.org/10.1109/jssc.2010.2042244.

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18

Yoon, Do-Yeon, Stacy Ho, and Hae-Seung Lee. "A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS." IEEE Journal of Solid-State Circuits 50, no. 12 (December 2015): 2880–90. http://dx.doi.org/10.1109/jssc.2015.2466459.

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19

Shamsi, Alireza, and Esmaeil Najafi Aghdam. "A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1850044. http://dx.doi.org/10.1142/s0218126618500445.

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Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

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20

Pulincherry, A., M. Hufford, E. Naviasky, and Un-Ku Moon. "A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture." IEEE Transactions on Circuits and Systems II: Express Briefs 52, no. 10 (October 2005): 680–84. http://dx.doi.org/10.1109/tcsii.2005.850746.

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21

Mariano, A., D. Dallet, Y. Deval, and J. B. Bégueret. "Top-down design methodology of a multi-bit continuous-time delta–sigma modulator." Analog Integrated Circuits and Signal Processing 60, no. 1-2 (July 25, 2008): 145–53. http://dx.doi.org/10.1007/s10470-008-9206-5.

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22

He, Xiao-yong, Kong-pang Pun, Siu-kei Tang, Chiu-sing Choy, and Peter Kinget. "A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator." Analog Integrated Circuits and Signal Processing 66, no. 2 (August 28, 2010): 255–67. http://dx.doi.org/10.1007/s10470-010-9530-4.

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23

Van Engelen, J. A. E. P., R. J. Van De Plassche, E. Stikvoort, and A. G. Venes. "A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF." IEEE Journal of Solid-State Circuits 34, no. 12 (1999): 1753–64. http://dx.doi.org/10.1109/4.808900.

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24

Gonzalez-Diaz, Victor R., and Fabio Pareschi. "A 65nm Continuous-Time Sigma-Delta Modulator With Limited OTA DC Gain Compensation." IEEE Access 8 (2020): 36464–75. http://dx.doi.org/10.1109/access.2020.2975601.

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25

Yan, Haiyue, Lin He, Yan Ye, and Fujiang Lin. "A second-order continuous-time delta-sigma modulator with double self noise coupling." Analog Integrated Circuits and Signal Processing 99, no. 2 (February 20, 2019): 251–59. http://dx.doi.org/10.1007/s10470-019-01425-x.

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26

Ding, HaiTao, ZhenChuan Yang, ZhanFei Wang, Michael Kraft, and GuiZhen Yan. "MEMS gyroscope control system using a band-pass continuous-time sigma-delta modulator." Science China Information Sciences 56, no. 10 (September 28, 2012): 1–10. http://dx.doi.org/10.1007/s11432-012-4670-z.

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27

Pakniat, Hossein. "Five‐level class‐D amplifier employing fourth‐order continuous‐time sigma‐delta modulator." Electronics Letters 57, no. 4 (January 20, 2021): 175–78. http://dx.doi.org/10.1049/ell2.12004.

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28

Jeong, Donghyeok, and Changsik Yoo. "Voltage-controlled-oscillator based Continuous-time Sigma-delta Modulator Analog-to-digital Converter." Journal of the Institute of Electronics and Information Engineers 58, no. 4 (April 30, 2021): 32–39. http://dx.doi.org/10.5573/ieie.2021.58.4.32.

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29

Radjen, Dejan, Pietro Andreani, Martin Anderson, and Lars Sundström. "A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback." Analog Integrated Circuits and Signal Processing 74, no. 1 (September 14, 2012): 21–31. http://dx.doi.org/10.1007/s10470-012-9960-2.

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30

Dong, Y., M. Kraft, N. Hedenstierna, and W. Redman-White. "Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator." Sensors and Actuators A: Physical 145-146 (July 2008): 299–305. http://dx.doi.org/10.1016/j.sna.2007.10.057.

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31

Ortmanns, M., F. Gerfers, and Y. Manoli. "A case study on a 2-1-1 cascaded continuous-time sigma-delta Modulator." IEEE Transactions on Circuits and Systems I: Regular Papers 52, no. 8 (August 2005): 1515–25. http://dx.doi.org/10.1109/tcsi.2005.852024.

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32

Pavan, Shanthi. "Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 8 (August 2017): 1953–65. http://dx.doi.org/10.1109/tcsi.2017.2682884.

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33

Huang, Qiang, Zhaosheng Teng, Xiang Tang, Haijun Lin, and He Wen. "Mass Measurement Method for the Electronic Balance Based on Continuous-Time Sigma-Delta Modulator." IEEE Transactions on Instrumentation and Measurement 65, no. 6 (June 2016): 1300–1309. http://dx.doi.org/10.1109/tim.2015.2490358.

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34

Zhang, Jinghua, Yong Lian, Libin Yao, and Bo Shi. "A 0.6-V 82-dB 28.6-$\mu$W Continuous-Time Audio Delta-Sigma Modulator." IEEE Journal of Solid-State Circuits 46, no. 10 (October 2011): 2326–35. http://dx.doi.org/10.1109/jssc.2011.2161212.

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35

Ju, Chunge, Xiang Li, Junjun Zou, Qi Wei, Bin Zhou, and Rong Zhang. "An Auto-Tuning Continuous-Time Bandpass Sigma-Delta Modulator with Signal Observation for MEMS Gyroscope Readout Systems." Sensors 20, no. 7 (April 1, 2020): 1973. http://dx.doi.org/10.3390/s20071973.

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This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm2. The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C.

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36

Pavan, Shanthi. "A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time $\Delta\Sigma$ Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 60, no. 2 (February 2013): 81–85. http://dx.doi.org/10.1109/tcsii.2012.2235016.

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37

Kulchycki, Scott D., Roxana Trofin, Katelijn Vleugels, and Bruce A. Wooley. "A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator." IEEE Journal of Solid-State Circuits 43, no. 4 (April 2008): 796–804. http://dx.doi.org/10.1109/jssc.2008.917499.

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38

Colodro, Francisco, and Antonio Torralba. "Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 9 (September 2010): 2413–25. http://dx.doi.org/10.1109/tcsi.2010.2043991.

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39

Zhimin Li and T. S. Fiez. "A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth." IEEE Journal of Solid-State Circuits 42, no. 9 (September 2007): 1873–83. http://dx.doi.org/10.1109/jssc.2007.903086.

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40

de Aguirre, Paulo Cesar C., and Altamiro Amadeu Susin. "A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 10 (October 2018): 1310–14. http://dx.doi.org/10.1109/tcsii.2018.2853088.

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41

Jeong, Donghyeok, and Changsik Yoo. "A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 7 (July 2019): 1124–28. http://dx.doi.org/10.1109/tcsii.2018.2880912.

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42

de Aguirre, Paulo Cesar C., Edoardo Bonizzoni, Franco Maloberti, and Altamiro Amadeu Susin. "A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma–Delta Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 8 (August 2020): 1384–88. http://dx.doi.org/10.1109/tcsii.2019.2939740.

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43

., Soumya Shatakshi Panda. "A 15 BIT THIRD ORDER POWER OPTIMIZED CONTINUOUS TIME SIGMA DELTA MODULATOR FOR AUDIO APPLICATIONS." International Journal of Research in Engineering and Technology 03, no. 27 (December 25, 2014): 99–103. http://dx.doi.org/10.15623/ijret.2014.0327019.

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44

Billa, Sujith, Suhas Dixit, and Shanthi Pavan. "Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator." IEEE Journal of Solid-State Circuits 55, no. 10 (October 2020): 2649–59. http://dx.doi.org/10.1109/jssc.2020.2992891.

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45

Kim, Taewook, Changsok Han, and Nima Maghari. "A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer." IEEE Journal of Solid-State Circuits 52, no. 12 (December 2017): 3248–61. http://dx.doi.org/10.1109/jssc.2017.2734906.

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46

Hwang, Yuh-Shyan, Jiann-Jong Chen, Jyun Yang, and Yitsen Ku. "A Low-EMI Continuous-Time Delta-Sigma-Modulator Buck Converter With Transient Response Eruption Techniques." IEEE Transactions on Industrial Electronics 67, no. 8 (August 2020): 6854–63. http://dx.doi.org/10.1109/tie.2019.2937071.

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47

Sahu, Anil Kumar, Vivek Kumar Chandra, and G. R. Sinha. "Analysis of Quantization Noise and Power Estimation of Continuous-Time Delta Sigma Analog-to-Digital Converter Using Test Enable Feature For 4G Radios." International Journal of Informatics and Communication Technology (IJ-ICT) 7, no. 2 (August 1, 2018): 82. http://dx.doi.org/10.11591/ijict.v7i2.pp82-88.

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<span>This paper presents a novel approach for completely test enable feature and low-voltage delta– sigma analog-to-digital (A/D) converters for cutting edge wireless applications. Oversampling feature of ADCs and DACs is enough to meet the requirement related to in-band and adjacent channel leakage ratio (ACLR) execution of 3G/4G portable radio. The quantization noise which is not filtered in ADC is addressed. We have achieved work power-optimization and test enable feature of oversampling ADC is uses in design and simulation so that the problem of quantization error in continues time sigma delta ADC is solved. This paper suggests support to designer for selecting appropriate topologies with various channel arrangements, number of bits and oversampling issues. A test enable feature of CT A/D is presented introducing the test signal generation (TSG) and the COrdinate Rotation Digital Computer (CORDIC) for evaluating the performance of ADC. This helps in addressing the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta–sigma modulator ADC for 4G radios is studied</span><span lang="IN">.</span>

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48

Chen, Zong-Yi, and Chung-Chih Hung. "A 5.8 mW Continuous-Time $\Delta \Sigma$ Modulator With 20 MHz Bandwidth Using Time-Domain Flash Quantizer." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5, no. 4 (December 2015): 574–83. http://dx.doi.org/10.1109/jetcas.2015.2502167.

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49

Weng, Chan-Hsiang, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, and Tsung-Hsien Lin. "A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer." IEEE Journal of Solid-State Circuits 51, no. 5 (May 2016): 1235–45. http://dx.doi.org/10.1109/jssc.2016.2532345.

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50

Talebzadeh, Jafar, and Izzet Kale. "A novel two-channel continuous-time time-interleaved 3rd-order sigma-delta modulator with integrator-sharing topology." Analog Integrated Circuits and Signal Processing 95, no. 3 (February 14, 2018): 375–85. http://dx.doi.org/10.1007/s10470-018-1125-5.

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