Relevant bibliographies by topics / Conventional folded-cascode operational amplifier

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Academic literature on the topic 'Conventional folded-cascode operational amplifier'

Author: Grafiati
Published: 3 June 2025
Last updated: 23 June 2025

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Journal articles on the topic "Conventional folded-cascode operational amplifier"

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Assaad, Rida, and Jose Silva-Martinez. "Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers." VLSI Design 2009 (July 28, 2009): 1–11. http://dx.doi.org/10.1155/2009/323595.

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Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.
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Akbari, Meysam, and Omid Hashemipour. "Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits." Journal of Circuits, Systems and Computers 25, no. 11 (2016): 1650144. http://dx.doi.org/10.1142/s0218126616501449.

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In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.
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Varsha, S. Bendre, and K. Kureshi A. "Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 2 (2019): 114–18. https://doi.org/10.35940/ijeat.B2995.129219.

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The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.
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Krolák, David, and Pavel Horský. "An EMI susceptibility study of different integrated operational transconductance amplifiers." Journal of Electrical Engineering 74, no. 1 (2023): 13–22. http://dx.doi.org/10.2478/jee-2023-0002.

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Abstract This paper presents a comparative EMI susceptibility study of different integrated operational transconductance amplifier (OTA) topologies. We analyzed conventional well-known amplifier topologies based on the Miller OTA and folded cascode concepts with lower power consumption. The output dc voltage shifts induced by power supply and input common mode high frequency disturbances are presented. On top of the EMI susceptibility comparison, we discuss PSRR and CMRR within large and small excitation signal with a new simulation setup. Even more, the back-gate connections of differential MOS pair in OTA input stage are investigated for EMI susceptibility impact as well.
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Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.
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Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.
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Ahmad, Shadab, Mahaveer Singh Naruka, and Lidia Shanti Singavarapu. "UNVEILING THE POTENTIAL OF AN IMPROVED RECYCLING FOLDED CASCODE AMPLIFIER FOR CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER DESIGN AND OPTIMIZATION." ICTACT Journal on Microelectronics 9, no. 2 (2023): 1557–61. https://doi.org/10.21917/ijme.2023.0271.

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This paper presents the investigation and optimization of a Recycling Folded Cascode Amplifier (RFCA) for designing a highly efficient and high-performance CMOS Operational Transconductance Amplifier (OTA). The proposed RFCA architecture leverages recycling techniques to enhance the overall gain, linearity, and power efficiency of the OTA. By analyzing the operational principles of the RFCA and exploring various optimization strategies, this study unveils the significant potential of this improved architecture in the context of CMOS OTA design. Simulation results demonstrate superior performance metrics, including increased gain, reduced distortion, and improved power consumption compared to conventional OTA designs. The findings of this study not only contribute to the understanding of RFCA-based OTA design but also offer valuable insights into the broader scope of recycling techniques in analog circuit optimization.
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Moosaei, Amir, Mohammad Hossein Maghami, Ali Nejati, Parviz Amiri, and Mohamad Sawan. "A Low-Power, Low-Noise Recycling Folded-Cascode Operational Transconductance Amplifier for Neural Recording Applications." Electronics 14, no. 8 (2025): 1543. https://doi.org/10.3390/electronics14081543.

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We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μVrms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm2. Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µVrms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 Vpp with a total harmonic distortion of −62.68 dB at 1 kHz.
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Durgam, Rajesh, S. Tamil, and Nikhil Raj. "Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier." U.Porto Journal of Engineering 7, no. 4 (2021): 103–10. http://dx.doi.org/10.24840/2183-6493_007.004_0008.

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In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.
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Centurelli, Francesco, Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti, and Alessandro Trifiletti. "A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate." Electronics 10, no. 14 (2021): 1638. http://dx.doi.org/10.3390/electronics10141638.

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A novel architecture and design approach which make it possible to boost the bandwidth and slew-rate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.
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Dissertations / Theses on the topic "Conventional folded-cascode operational amplifier"

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Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.

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Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.
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Books on the topic "Conventional folded-cascode operational amplifier"

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Abu-Dayeh, Mahmoud A. A fast-settling folded-cascode CMOS operational amplifier. 1988.

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Abu-Dayeh, Mahmoud A. A fast-settling folded-cascode CMOS operational amplifier. 1988.

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Book chapters on the topic "Conventional folded-cascode operational amplifier"

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Saranya, M. N., Sriadibhatla Sridevi, and Rajasekhar Nagulapalli. "Gain Enhanced Single-Stage Split Folded Cascode Operational Transconductance Amplifier." In Soft Computing and Signal Processing. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8669-7_50.

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Islam, Mir Bintul, and M. Nizamuddin. "CNTFET Folded Cascode Operational Transconductance Amplifier: Design and Comparative Analysis." In Springer Proceedings in Materials. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-4685-3_45.

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"Design of high performance folded-cascode operational amplifier." In Information Science and Electronic Engineering. CRC Press, 2016. http://dx.doi.org/10.1201/9781315265278-103.

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Marzuki, Arjuna, Mohd Tafir Mustaffa, Norlaili Mohd Noh, and Basir Saibon. "Analog Circuit of Light Detector for CMOS Image Sensor." In Optoelectronics in Machine Vision-Based Theories and Applications. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-5751-7.ch002.

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Plant phenotyping studies represent a challenge in agriculture application. The studies normally employ CMOS optical and image sensor. One of the most difficult challenges in designing the CMOS sensor is the need to achieve good sensitivity while achieving low noise and low power simultaneously for the sensor. At low power, the CMOS amplifier in the sensor is normally having a lower gain, and it becomes even worse when the frequency of the interest is in the vicinity of flicker noise region. Using conventional topology such as folded cascode will result in the CMOS amplifier having high gain, but with the drawback of high power. Hence, there is a need for a new approach that improves the sensitivity of the CMOS sensor while achieving low power. The objective of this chapter is to update CMOS sensors and to introduce a modified light integrating circuit which is suitable for CMOS image sensor.
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Conference papers on the topic "Conventional folded-cascode operational amplifier"

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Anushree, Rupali Singh, and Jasdeep Kaur. "Performance Improvement of Folded Cascode and Recyclic Folded Cascode Operational Amplifier." In 2024 IEEE Region 10 Symposium (TENSYMP). IEEE, 2024. http://dx.doi.org/10.1109/tensymp61132.2024.10752191.

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Yang, Xiao, Yongqiang Chen, Hongrui Liao, and Jiangping He. "A Gain and Slew Rate Enhanced Recycling Folded Cascode Operational Amplifier." In 2024 4th International Symposium on Artificial Intelligence and Intelligent Manufacturing (AIIM). IEEE, 2024. https://doi.org/10.1109/aiim64537.2024.10934431.

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Sergeenko, Marsel A., Vladislav E. Chumakov, and Nikolay N. Prokopenko. "Gallium Arsenide Operational Amplifier Based on a “Folded” Cascode Containing No Current Mirrors." In 2024 IEEE 25th International Conference of Young Professionals in Electron Devices and Materials (EDM). IEEE, 2024. http://dx.doi.org/10.1109/edm61683.2024.10615026.

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Lipka, B., U. Kleine, J. C. Scheytt, and K. Schmalz. "Design of a complementary folded-cascode operational amplifier." In 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398081.

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Vij, Saumya, Anu Gupta, and Alok Mittal. "A Highly Adaptive Operational Amplifier with Recycling Folded Cascode Topology." In Fourth International Conference on Computer Science, Engineering and Applications. Academy & Industry Research Collaboration Center (AIRCC), 2014. http://dx.doi.org/10.5121/csit.2014.4721.

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Sharma, Tripti, and Satwinder Kaur. "Design and implementation of recycling folded cascode operational transconductance amplifier." In PROCEEDINGS OF THE 4TH INTERNATIONAL COMPUTER SCIENCES AND INFORMATICS CONFERENCE (ICSIC 2022). AIP Publishing, 2023. http://dx.doi.org/10.1063/5.0122606.

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Kuznetsov, Dmitry, Alexey Titov, Nikolay Prokopenko, and Nikolay Butyrlagin. "High-Speed Operational Amplifier Based on a Modified “Folded” Cascode." In 2024 IEEE Ural-Siberian Conference on Biomedical Engineering, Radioelectronics and Information Technology (USBEREIT). IEEE, 2024. http://dx.doi.org/10.1109/usbereit61901.2024.10584022.

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Gupta, Harsh, Gaurav Kumar Mishra, Navaid Zafar Rizvi, and Santosh Kumar Patnaik. "Design of high PSRR folded cascode operational amplifier for LDO applications." In 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE, 2016. http://dx.doi.org/10.1109/iceeot.2016.7755591.

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Nischal, Simran, and Jasdeep Kaur. "Study of a Self Biased High Swing Cascode Current Mirror Based Folded Cascode Operational Amplifier." In 2019 4th International Conference on Information Systems and Computer Networks (ISCON). IEEE, 2019. http://dx.doi.org/10.1109/iscon47742.2019.9036217.

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Stancu, Cristian, Dragos Dobrescu, and Lidia Dobrescu. "Offset Voltage Reduction Methods for a Two-Stage Folded Cascode Operational Amplifier." In 2022 14th International Conference on Electronics, Computers and Artificial Intelligence (ECAI). IEEE, 2022. http://dx.doi.org/10.1109/ecai54874.2022.9847308.

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