Journal articles: 'Conventional folded-cascode operational amplifier'

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Assaad, Rida, and Jose Silva-Martinez. "Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers." VLSI Design 2009 (July 28, 2009): 1–11. http://dx.doi.org/10.1155/2009/323595.

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Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

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Akbari, Meysam, and Omid Hashemipour. "Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits." Journal of Circuits, Systems and Computers 25, no. 11 (2016): 1650144. http://dx.doi.org/10.1142/s0218126616501449.

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In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

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Varsha, S. Bendre, and K. Kureshi A. "Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 2 (2019): 114–18. https://doi.org/10.35940/ijeat.B2995.129219.

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The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

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Krolák, David, and Pavel Horský. "An EMI susceptibility study of different integrated operational transconductance amplifiers." Journal of Electrical Engineering 74, no. 1 (2023): 13–22. http://dx.doi.org/10.2478/jee-2023-0002.

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Abstract This paper presents a comparative EMI susceptibility study of different integrated operational transconductance amplifier (OTA) topologies. We analyzed conventional well-known amplifier topologies based on the Miller OTA and folded cascode concepts with lower power consumption. The output dc voltage shifts induced by power supply and input common mode high frequency disturbances are presented. On top of the EMI susceptibility comparison, we discuss PSRR and CMRR within large and small excitation signal with a new simulation setup. Even more, the back-gate connections of differential MOS pair in OTA input stage are investigated for EMI susceptibility impact as well.

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Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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Ahmad, Shadab, Mahaveer Singh Naruka, and Lidia Shanti Singavarapu. "UNVEILING THE POTENTIAL OF AN IMPROVED RECYCLING FOLDED CASCODE AMPLIFIER FOR CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER DESIGN AND OPTIMIZATION." ICTACT Journal on Microelectronics 9, no. 2 (2023): 1557–61. https://doi.org/10.21917/ijme.2023.0271.

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This paper presents the investigation and optimization of a Recycling Folded Cascode Amplifier (RFCA) for designing a highly efficient and high-performance CMOS Operational Transconductance Amplifier (OTA). The proposed RFCA architecture leverages recycling techniques to enhance the overall gain, linearity, and power efficiency of the OTA. By analyzing the operational principles of the RFCA and exploring various optimization strategies, this study unveils the significant potential of this improved architecture in the context of CMOS OTA design. Simulation results demonstrate superior performance metrics, including increased gain, reduced distortion, and improved power consumption compared to conventional OTA designs. The findings of this study not only contribute to the understanding of RFCA-based OTA design but also offer valuable insights into the broader scope of recycling techniques in analog circuit optimization.

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Moosaei, Amir, Mohammad Hossein Maghami, Ali Nejati, Parviz Amiri, and Mohamad Sawan. "A Low-Power, Low-Noise Recycling Folded-Cascode Operational Transconductance Amplifier for Neural Recording Applications." Electronics 14, no. 8 (2025): 1543. https://doi.org/10.3390/electronics14081543.

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We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μVrms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm2. Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µVrms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 Vpp with a total harmonic distortion of −62.68 dB at 1 kHz.

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Durgam, Rajesh, S. Tamil, and Nikhil Raj. "Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier." U.Porto Journal of Engineering 7, no. 4 (2021): 103–10. http://dx.doi.org/10.24840/2183-6493_007.004_0008.

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In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

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Centurelli, Francesco, Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti, and Alessandro Trifiletti. "A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate." Electronics 10, no. 14 (2021): 1638. http://dx.doi.org/10.3390/electronics10141638.

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A novel architecture and design approach which make it possible to boost the bandwidth and slew-rate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

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Kim, Hyeon-June, Younghoon Park, Kyungsik Eom, and Sung-Yun Park. "An Area- and Energy-Efficient 16-Channel, AC-Coupled Neural Recording Analog Frontend for High-Density Multichannel Neural Recordings." Electronics 10, no. 16 (2021): 1972. http://dx.doi.org/10.3390/electronics10161972.

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We present an AC-coupled modular 16-channel analog frontend with 1.774 fJ/c-s∙mm2 energy- and area-product for a multichannel recording of broadband neural signals including local field potentials (LFPs) and extracellular action potentials (EAPs). To achieve such a small area- and energy-product, we employed an operational transconductance amplifier (OTA) with local positive feedback, instead of a widely-used folded cascode OTA (FC-OTA) or current mirror OTA for conventional neural recordings, while optimizing the design parameters affecting performance, power, and area trade-offs. In addition, a second pole was strategically introduced in the LNA to reduce the noise bandwidth without an in-channel low-pass filter. Compared to conventional works, the presented method shows better performance in terms of noise, power, and area usages. The performance of the fabricated 16-channel analog frontend is fully characterized in a benchtop and an in vitro setup. The 16-channel frontend embraces LFPs and EAPs with 4.27 μVrms input referred noise (0.5–10 kHz) and 53.17 dB dynamic range, consuming 3.44 μW and 0.012 mm2 per channel. The channel figure of merit (FoM) of the prototype is 147.87 fJ/c-s and the energy-area FoM (E-A FoM) is 1.774 fJ/c-s∙mm2.

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Hashmi, Faraz, M. Nizamuddin, and Wakeel Ahmad. "A Novel Carbon Nanotube Field Effect Transistors Based Triple Cascode Operational Transconductance Amplifier: An Optimum Design." Journal of Nanoelectronics and Optoelectronics 18, no. 5 (2023): 534–46. http://dx.doi.org/10.1166/jno.2023.3432.

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This paper discusses a triple-cascode operational transconductance amplifier (TCOTA) circuit’s design and modeling. These proposed TCOTAs are constructed using 45 nm Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Carbon Nanotube Field Effect Transistors (CNTFETs). At the 45 nm technology node, three distinct varieties of CNT-based TCOTAs have been designed and contrasted with conventional CMOS-based TCOTAs. The performance of the CNT-based TCOTAs, particularly a pure CNT-TCOTA, has significantly improved, according to the assessment of the fundamental aspects of all the devices. The DC gain has been enhanced by 73% when contrasting the pure CNT-TCOTA to the conventional CMOS-TCOTA, the CMRR has improved by 28%, and the power consumption has been reduced by 100.63%. Furthermore, in pure CNT-TCOTA, (FOM)1 and (FOM)2 have increased by 194% and 173%, respectively. It has also been investigated thoroughly how CNT-based OTAs perform by adjusting the CNT diameter (DCNT), pitch (S), and number of CNTs (N) at CL = 0.01 pF and 0.9 V power supply. It has been determined that using optimum CNT quantity, the pitch between CNTs, and diameter values can further enhance their performance. The simulation and comparative studies of all circuit structures have reported that novel and remarkable improvement is distinguished in CNT-based TCOTA. According to simulation and comparative assessments of all circuit structures, CNT-based TCOTA exhibits a novel and noteworthy improvement. Moreover, when compared to the conventional CMOS-TCOTA, the pure CNT-TCOTA has shown significant enhancement of 11.1% and 10.24% in GM and PM, respectively. Pure CNT-TCOTA has been demonstrated to be highly stable by the stability analysis.

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Kotha, Sreeteja Reddy, Karuppanan P, Abhay Kumar Gautam, and Manmath Suryavanshi. "A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications." Journal of Integrated Circuits and Systems 16, no. 3 (2021): 1–9. http://dx.doi.org/10.29292/jics.v16i3.498.

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This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.

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E.L, Pankratov. "On Optimization of Manufacturing of a Conventional Folded Cascode Operational Amplifier Based on Heterostructures to Increase Density of their Elements. Influence of Missmatch Induced Stress and Porosity of Materials on Technological Process." International Journal on Organic Electronics 7, no. 2 (2018): 01–19. http://dx.doi.org/10.5121/ijoe.2018.7201.

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Song, Ming Xin, Yue Li, and Meng Meng Xu. "Design of High Gain CMOS Folded Cascode Operational Amplifier." Applied Mechanics and Materials 389 (August 2013): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.389.573.

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A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

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Anvekar, Shreya, A. D. Anusha, Goutam Giriraddi, Bhargav Hegde, and Sujata Kotabagi. "Single Stage Folded-Cascode Operational Amplifier." International Journal of Microsystems and IoT 2, no. 4 (2024): 745–52. https://doi.org/10.5281/zenodo.11654752.

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This paper mainly concentrates on designing a single-stage folded cascode op-amp with UMC 180nm technology. The amplifier operates seamlessly within the confines of a 1.8V power supply, shows a DC gain of 55dB, a phase margin of 66.87 degrees, and the amplifier’s bandwidth is reported at 222kHz (-3dB) for a 1pF load. It works with ICMR range from 1.6V-0.8V. The proposed structure yields medium gain and wide output swing ranging from 300mV to 1.4V.

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Vasudeva, G., and Mandar Jatkar. "Design of High Performance Operational Transconductance Amplifier." ACS Journal for Science and Engineering 3, no. 2 (2023): 21–30. http://dx.doi.org/10.34293/acsjse.v3i2.81.

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Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all the transistors are in saturation regime. Furthermore, in an effort to reduce costs and integrate analog and digital circuits onto a single chip, the analog designer must often face the challenges using CMOS processes. This paper covers the design and implementation of a novel CMOS folded cascode OTA designed in 1m technology. Covered topic include current source and sinks, differential amplifier, compensation techniques, two stage compensated OTA and cascode OTA. Our design emphasis is on practical design where power consumption and speed are critical. The OTA has very low settling time and can be used for high speed applications, such Analog-to–Digital converters, high speed Sigma-delta ADC.

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Yavari, Mohammad. "A new class AB folded-cascode operational amplifier." IEICE Electronics Express 6, no. 7 (2009): 395–402. http://dx.doi.org/10.1587/elex.6.395.

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Yao, Peiyuan. "A High-Performance CMOS Operational Amplifier Design." Applied and Computational Engineering 147, no. 1 (2025): 197–202. https://doi.org/10.54254/2755-2721/2025.22724.

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This paper presents the design of a high-performance two-stage folded cascode operational amplifier based on the TSMC 180nm CMOS process. The input stage adopts a folded cascode structure, which not only achieves a high DC gain but also enhances the suppression of common-mode noise. The output stage uses a common-source structure to ensure the output swing. To ensure the stability of the operational amplifier, a Miller capacitor is used to compensate the output stage amplifier, ensuring sufficient phase margin. The design and simulation of the circuit were completed using Cadence software. Simulation results under a 1.8V supply voltage and a 2pF load capacitance show that the DC gain of the operational amplifier is no less than 84dB, the common-mode rejection ratio (CMRR) is greater than 130dB, and the power supply rejection ratio (PSRR) is greater than 114dB under various temperature and process corners. At room temperature, the quiescent power consumption is 1.5mW, and the circuit demonstrates good robustness. The circuit has low power consumption and has significant application value in bandgap reference circuits and active filter circuits.

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Su, C., B. J. Blalock, S. K. Islam, L. Zuo та L. M. Tolbert. "A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (2010): 000083–88. http://dx.doi.org/10.4071/hitec-csu-ta26.

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The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI processes offer several orders of magnitude smaller junction leakage current than bulk-CMOS processes at temperatures beyond 150°C. This amplifier is designed for a high temperature linear voltage regulator; the higher open-loop gain of this amplifier will enhance the overall performance of a linear regulator. In addition, the lower current consumption of the OTA is critical for improving the current efficiency of the linear regulator and reducing the power dissipation at elevated temperature. A PMOS input pair folded cascode OTA topology had been selected in this work, PMOS input pair offers wider ICMR (input common-mode range) and empirically lower flicker noise compared to its NMOS counterpart. By cascoding current mirror load at the output node, the folded cascode OTA obtains higher voltage gain than the symmetrical OTA topology. The PSRR (power supply rejection ratio) is also improved. A on-chip temperature stable current reference is employed to bias the amplifier. The amplifier consumes less than 65μA bias current at 175°C. The core layout area of the amplifier is 0.16mm2 (400 μm × 400 μm).

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Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

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Bendre, Varsha S., A. K. Kureshi, and Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier." Journal of Nanotechnology 2018 (December 4, 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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Yosefi, Ghader. "The high recycling folded cascode (HRFC): A general enhancement of the recycling folded cascode operational amplifier." Microelectronics Journal 89 (July 2019): 70–90. http://dx.doi.org/10.1016/j.mejo.2019.04.016.

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Wang, Zhe Fei, Yi Jiang Cao, and Ju Meng Feng. "A Design of High Performance CMOS Folded Cascode Operational Amplifier." Advanced Materials Research 981 (July 2014): 31–35. http://dx.doi.org/10.4028/www.scientific.net/amr.981.31.

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This paper describes a kind of folded cascode amplifier, which not only has high gain, large output swing characteristics, and its outputs can be self-compensation, it has a strong suppression capability with voltage noise. Based on a 0.5μm CMOS process uses two operational amplifiers. Through software emulation corrected the error which was caused by theoretical calculation. Has good performance in gain, noise, swing, phase margin, common mode rejection ratio and other parameters.

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Chan, P. K., L. S. Ng, L. Siek, and K. T. Lau. "Designing CMOS folded-cascode operational amplifier with flicker noise minimisation." Microelectronics Journal 32, no. 1 (2001): 69–73. http://dx.doi.org/10.1016/s0026-2692(00)00105-1.

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Sarin, Mythry, A.Gayathri, Farheen Saieemah, N.Jeenath, M.Sowmya, and P.Sahith. "Design of Low Power Operational Transconductance Amplifier for Biomedical Applications." International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE) 3, no. 2 (2020): 15–21. https://doi.org/10.5281/zenodo.3975519.

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This paper presents the design of folded cascode operational transconductance amplifier (OTA). This design has been implemented in 0.18um CMOS Technology using Cadence. Spectre simulation shows that the OTA has flat gain of 47dB from 1Hz to 100 KHz frequency, indicating stability of OTA, noise ranges as 22.49769nV/ at 10Hz to 66.89128fV/ at 1MHz and average power as 0.770mW. In this paper, we will be studying the design concepts, analysis of operational transconductance amplifier which is used for recording the bio signals. This paper plays a key role in real time applications for equipment designing of ECG, EEG, EMG, ENG devices. It is also used in recording and also for treatment of Paralysis, Epilepsy, Neuro diseases etc.,

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Cui, Lin Hai, Rui Xu, Zhan Peng Jiang, and Chang Chun Dong. "Design of a Low-Voltage Low-Power CMOS Operational Amplifier." Applied Mechanics and Materials 380-384 (August 2013): 3283–86. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3283.

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A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

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Khade, Amitkumar S., Sandeep Musale, Ravikant Suryawanshi, and Vibha Vyas. "A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier." Analog Integrated Circuits and Signal Processing 107, no. 1 (2021): 227–38. http://dx.doi.org/10.1007/s10470-021-01809-y.

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Kaur, Jasbir, and Neha Shukla. "Analysis of Two Stage Folded Cascode Operational Amplifier in 90nm Technology." IJIREEICE 5, no. 6 (2017): 149–56. http://dx.doi.org/10.17148/ijireeice.2017.5626.

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30

Mallya, S., and J. H. Nevin. "Design procedures for a fully differential folded-cascode CMOS operational amplifier." IEEE Journal of Solid-State Circuits 24, no. 6 (1989): 1737–40. http://dx.doi.org/10.1109/4.45013.

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31

Vij, Saumya, Anu Gupta, and Alok Mittal. "An Operational Amplifier with Recycling Folded Cascode Topology and Adaptive Biasing." International Journal of VLSI Design & Communication Systems 5, no. 4 (2014): 33–46. http://dx.doi.org/10.5121/vlsic.2014.5403.

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32

Wang, Lin Feng, Qiao Meng, and Hao Zhi. "Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth." Applied Mechanics and Materials 614 (September 2014): 237–40. http://dx.doi.org/10.4028/www.scientific.net/amm.614.237.

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This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.

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33

Zhong, Yi, Faming Yang, Wanjun Yin, and Qing Liu. "A Time-Interleaved Charge Pump Internal Power Supply Generation Circuit." Journal of Physics: Conference Series 2356, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2356/1/012015.

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A charge pump internal power supply generation circuit for rail-to-rail operational amplifier is proposed, which combines a non-overlapping clock signal and a time-interleaved boost charge pump to achieve an internal power supply which is higher than the power supply voltage. A voltage follower is used to avoid glitch during time-interleaving switching. The charge pump internal power supply circuit is realized by 0.5μm CMOS process. The simulation results show that the internal power supply circuit of the charge pump can generate an internal power supply signal which is 1.8V higher than the power supply voltage. After applying this internal power supply to the PMOS input folded cascode operational amplifier, the operational amplifier achieves the rail-to-rail input, and the unity gain bandwidth and phase margin are stable.

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Idros, Norhamizah, Zulfiqar Ali Abdul Aziz, and Jagadheswaran Rajendran. "A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier." Microelectronics International 37, no. 4 (2020): 205–13. http://dx.doi.org/10.1108/mi-05-2020-0030.

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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35

Kang, Kit. "Design and Analysis of High Efficiency Operational Transconductance Amplifier." Applied and Computational Engineering 168, no. 1 (2025): 55–62. https://doi.org/10.54254/2755-2721/2025.24250.

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High efficiency operational transconductance amplifier is an important analog circuit designed to optimize the balance between power consumption and performance. This amplifier is suitable for mobile devices, sensor interfaces, and other low-power applications due to its high gain and low power consumption characteristics. This article provides a design for implementing a high-efficiency operational transconductance amplifier, which achieves higher gain and bandwidth on the basis of traditional common source and common gate. A recycling folded cascode amplifier with bias circuit was designed using Cadence 0.18 m CMOS technology. The power consumption and load capacitance of the two circuits were the same and the various parameters of the two circuits were simulated and verified. Sacrificing some phase margin under small signal conditions increased the gain by 6dB, bandwidth by 1.89 times, and the speed of the operational amplifier was accelerated; The slew rate under high signal is 1.5 times faster than before, and the setup time is shorter. The CMRR and PSRR have both been improved.

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36

Ibarra, F. Sandoval, V. H. Arzate Palma, and S. D. Cárdenas Castellón. "Design of a Fully Differential CMOS OTA Folded Cascode for Modulation." International Journal of Emerging Technology and Advanced Engineering 10, no. 11 (2020): 1–6. http://dx.doi.org/10.46338/ijetae1120_01.

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In this paper, the design and experimental results of a fully-differential folded-cascode operational amplifier of transconductance (OTA) is presented. This active circuit is for the use in a  low-pass modulator. The structure of the OTA is for obtaining a transition frequency of 1.0GHz. From the circuit synthesis, the OTA can handle the signals with the peak-to-peak amplitude of 300mV, and consumes 1.5mA from 1.2V supply. The OTA is fabricated in 130nm standard CMOS technology.

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Kartheek, Palagiri. "Implementation of Modified folded Cascode OTA in Different Biasings Voltages." Journal of University of Shanghai for Science and Technology 24, no. 03 (2022): 135–39. http://dx.doi.org/10.51201/jusst/22/0164.

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This paper presents an optimized methodology to modified folded Cascode operational trans conductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the stateof- the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltagecombiners specifically targeting low voltage applications. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The simulation is performed in HSPICE Synopsys Tool and compared with existing designs.

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38

Meysam, Akbari, Biabanifard Sadegh, and Asadi Shahroz. "INPUT REFERRED NOISE REDUCTION TECHNIQUE FOR TRANSCONDUCTANCE AMPLIFIERS." Electrical & Computer Engineering: An International Journal (ECIJ) 4, no. 4 (2015): 11–22. https://doi.org/10.5281/zenodo.3611042.

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In this paper, a useful procedure to design folded cascode (FC) and recycling folded cascode (RFC) OTAs is presented. The proposed procedure is based on a simplified equation of input voltage noise in strong and weak inversion regions. The presented method considerably decreases the input referred noise of amplifiers in weak, moderate and strong inversion. The proposed amplifiers were simulated in 0.18µm CMOS technology, achieving 36% and 25% reduction of input voltage noise @ 1Hz in strong and weak inversion, respectively, compared to the conventional FC, without increasing power consumption and silicon area.

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39

Du, Yiheng, Changde He, Guowei Hao, Wendong Zhang, and Chenyang Xue. "Full-Differential Folded-Cascode Front-End Receiver Amplifier Integrated Circuit for Capacitive Micromachined Ultrasonic Transducers." Micromachines 10, no. 2 (2019): 88. http://dx.doi.org/10.3390/mi10020088.

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This paper describes the design of a front-end receiver amplifier for capacitive micromachined ultrasonic transducer (CMUT). The proposed operational amplifier (op amp) consists of a full differential folded-cascode amplifier stage followed by a class AB output stage. A feedback resistor is applied between the input and the output of the op amp to make a transimpedance amplifier. We analyzed the equivalent circuit model of the CMUT element operating in the receiving mode and obtained the static output impedance and center frequency characteristics of the CMUT. The op amp gain, bandwidth, noise, and power consumption trade-oﬀs are discussed in detail. The amplifier was fabricated using GlobalFoundries 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The open loop gain of the amplifier is approximately 65 dB, and its gain bandwidth product is approximately 29.5 MHz. The measured input reference noise current was 56 nA/√Hz@3 MHz. The amplifier chip area is 325 μm × 150 μm and the op amp is powered by 3.3 V, the static power consumption is 11 mW. We verified the correct operation of our amplifier with CMUT and echo-pulse shown that the CMUT center frequency is 3 MHz with 92% fractional bandwidth.

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40

Vasudeva, Gowdagere, and Bidikinamane Venkataramanaiah Uma. "Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 2158–68. https://doi.org/10.11591/ijece.v12i2.pp2158-2168.

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Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.

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41

Lagos-Eulogio, Pedro, Pedro Miranda-Romagnoli, Juan Carlos Seck-Tuoh-Mora, and Norberto Hernández-Romero. "Improvement in Sizing Constrained Analog IC via Ts-CPD Algorithm." Computation 11, no. 11 (2023): 230. http://dx.doi.org/10.3390/computation11110230.

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In this work, we propose a variation of the cellular particle swarm optimization algorithm with differential evolution hybridization (CPSO-DE) to include constrained optimization, named Ts-CPD. It is implemented as a kernel of electronic design automation (EDA) tool capable of sizing circuit components considering a single-objective design with restrictions and constraints. The aim is to improve the optimization solutions in the sizing of analog circuits. To evaluate our proposal’s performance, we present the design of three analog circuits: a differential amplifier, a two-stage operational amplifier (op-amp), and a folded cascode operational transconductance amplifier. Numerical simulation results indicate that Ts-CPD can find better solutions, in terms of the design objective and the accomplishment of constraints, than those reported in previous works. The Ts-CPD implementation was performed in Matlab using Ngspice and can be found on GitHub (see Data Availability Statement).

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42

Gowdagere, Vasudeva, and Uma Bidikinamane Venkataramanaiah. "Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 2158. http://dx.doi.org/10.11591/ijece.v12i2.pp2158-2168.

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<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

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43

Mo, Xiaorui, Jiayu Zhu, Hanxiao Lu, and Xu Liu. "Design and simulation of a bioimpedance detection analog front-end targeting medical applications." Theoretical and Natural Science 39, no. 1 (2024): 112–20. http://dx.doi.org/10.54254/2753-8818/39/20240615.

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This paper presents the design of a bio-impedance detection analog front-end system, which is critical for continuous monitoring of physiological signals in the prevention and treatment of diseases such as coronary heart disease in the context of an aging population. The analog front-end system employs a capacitive-coupled chopper instrumentation amplifier with a fully differentially folded cascode operational amplifier as the core amplifier, and a common-mode feedback loop is introduced to improve the common-mode rejection ratio due to the high requirement for noise suppression. The power supply voltage of the design is 3.3V, achieving a total current consumption of 45uA and a total power consumption of 0.15mW. The core operational amplifier provides a maximum open-loop gain of 58 dB and a -3dB bandwidth of 8.2KHz. The power supply rejection ratio for the positive supply and ground achieved values of 102dB and 108dB, respectively. The common-mode rejection ratio of the chopper instrumentation amplifier can reach 109 dB, which is critical for suppressing common-mode noise.

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Ou, Jack, and Pietro M. Ferreira. "A $g_{m}/I_{D}$-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 10 (2014): 783–87. http://dx.doi.org/10.1109/tcsii.2014.2345297.

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Stancu, Cristian, Andrei Neacsu, Teodora Ionescu, et al. "Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration." Electronics 12, no. 21 (2023): 4534. http://dx.doi.org/10.3390/electronics12214534.

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The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature.

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Guo, Min, Hong Hui Deng, Bo Wen Ding, and Yong Sheng Yin. "Design of a Second-Order Sigma-Delta Modulator." Applied Mechanics and Materials 644-650 (September 2014): 3797–801. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3797.

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A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

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47

Li, Xiang, Bo Hou, Chunge Ju, Qi Wei, Bin Zhou, and Rong Zhang. "A Complementary Recycling Operational Transconductance Amplifier with Data-Driven Enhancement of Transconductance." Electronics 8, no. 12 (2019): 1457. http://dx.doi.org/10.3390/electronics8121457.

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An improved operational transconductance amplifier (OTA) is presented in this work. The fully differential OTA adopts the current recycling technique and complementary NMOS and PMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher current efficiency, a data-driven biasing circuit was developed to dynamically adjust the power consumption of the amplifier. Two comparators were added to detect the voltage difference at the input nodes, and when the differential input is large enough to activate either comparator, extra biasing current is activated and poured into the amplifier to enhance its slew rate and gain-bandwidth product (GBW). The threshold voltage of the complementary recycling folded cascode (CRFC)-based comparator is configured to suppress overshoot. Complementary common-mode feedback (CMFB) topology with local CMFB structure is built to acquire high common-mode gain. The OTA was fabricated in SMIC 0.18- μ m CMOS technology. The experimental result based on a capacitive feedback loop shows that the data-driven operation improves the average slew rate of the amplifier from 10.2 V/ μ s to 55.5 V/ μ s while the power only increases by 150%. The OTA has good potential to satisfy the fast settling demands for capacitive sensing circuits.

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48

Kunts, A. V., O. V. Dvornikov, and V. A. Tchekhovski. "Design of BJT-JFET Operational Amplifiers on the Master Slice Array." Doklady BGUIR 21, no. 6 (2024): 29–36. http://dx.doi.org/10.35596/1729-7648-2023-21-6-29-36.

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The use of dual-gate field-effect transistors located on the base matrix crystal MH2XA031, controlled by a p–n junction needed to reduce the input current of operational amplifiers is studied. Typical circuits of operational amplifiers, containing: source repeaters connected to the inputs of the operational amplifier on complementary bipolar transistors; input differential stage on p-JFET with a “current mirror” load on n–p–n-transistors; input differential in the form of a “folded cascode” on a p-JFET are analyzed. To minimize the input current, it is re commended to use bootstrapped feedback to keep the drain-to-source voltage of the input JFETs low, independent of the input common-mode voltage, and to connect only the top gate of the dual-gate JFET to the op-amp input. The electrical circuits for MH2XA031 elements and the results of circuit simulation of the developed amplifiers, called OAmp10J, OAmp11.1, OAmp11.2, are presented. Accounting the established features of the input stages and operating modes of active elements in circuit design will allow to create an operational amplifier with the required combination of basic parameters.

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Khade, Amitkumar S., Vibha Vyas, and Mukul Sutaone. "Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage." Integration 69 (November 2019): 242–50. http://dx.doi.org/10.1016/j.vlsi.2019.04.007.

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50

Wu, Chunkai, Peng Cai, Jinghu Li, Jin Xie, and Zhicong Luo. "Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing." Sensors 25, no. 8 (2025): 2523. https://doi.org/10.3390/s25082523.

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In this paper, we present a novel enhanced recycling folded cascode (ERFC) operational transconductance amplifier (OTA), which exhibits high efficiency and a fast transient response under weak inversion. Our innovative combination of adaptive biasing with nested local feedback (ABNLF) effectively enhances the input transconductance and slew rate (SR), thus improving the transient response. By incorporating coupling capacitors at the output stage, we achieve a stable operating region with large signal responses. Both the traditional RFC OTA and the proposed ERFC OTA were designed in a 0.18 μm CMOS process, operating at a power supply of 1.8 V, with quiescent currents of 8 μA and 10.4 μA, respectively. Post-layout simulations reveal a remarkable enhancement in the proposed ERFC OTA over the traditional RFC OTA, with the SR and gain–bandwidth (GBW) surging by 120- and 5.95-fold, respectively. This advancement boosts the efficiency of the traditional RFC OTA and provides an impressive figure of merit (FoM) of 130.04 (V/μs)·pF/μA.

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Journal articles on the topic 'Conventional folded-cascode operational amplifier'

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