Log in

Relevant bibliographies by topics / Copper interconnect systems / Journal articles

To see the other types of publications on this topic, follow the link: Copper interconnect systems.

Journal articles on the topic 'Copper interconnect systems'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Copper interconnect systems.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Mohammed, Ilyas. "Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)." International Symposium on Microelectronics 2012, no. 1 (2012): 001137–42. http://dx.doi.org/10.4071/isom-2012-thp43.

Full text

Abstract:

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls,

APA, Harvard, Vancouver, ISO, and other styles

2

Das, Debaprasad, and Hafizur Rahaman. "Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650001. http://dx.doi.org/10.1142/s0218126616500018.

Full text

Abstract:

In this work, we have investigated the applicability of graphene nanoribbon (GNR) as the interconnects for 16-nm ITRS technology node. GNR is proposed as the possible alternative to the traditional copper (Cu)-based interconnect systems in nanometer regime. In this paper, we have performed important studies on GNR for its applicability as power and signal interconnects. For the application of power interconnects, we have investigated the power supply voltage drop (IR drop) and simultaneous switching noise (SSN) in graphene-based interconnect system. We have performed crosstalk noise and oversh

APA, Harvard, Vancouver, ISO, and other styles

3

Fury, M. A., D. L. Scherber, and M. A. Stell. "Chemical-Mechanical Planarization of Aluminum-Based Alloys for Multilevel Metallization." MRS Bulletin 20, no. 11 (1995): 61–64. http://dx.doi.org/10.1557/s0883769400045607.

Full text

Abstract:

As recently as 1993, the prevailing presumption among the semiconductor technical community was that then-current development efforts associated with aluminum lines and tungsten damascene vias needed to shift rapidly to copper multilevel interconnect schemes. This is exemplified by the June 1993 issue of the MRS Bulletin, which featured copper metallization as its theme. In the intervening years, however, that same technical community revised the Semiconductor Industry Association (SIA) roadmap and placed renewed emphasis on the use of an all-aluminum interconnect scheme. This was done largely

APA, Harvard, Vancouver, ISO, and other styles

4

Zeng, Hao, Chao Lv, Yan Gao, Ting Yi Dong, Yong Hui Wang, and Xing Quan Wang. "Ultrahigh Purity Copper Alloy Target Used Innanoscale ULSI Interconnects." Materials Science Forum 815 (March 2015): 22–29. http://dx.doi.org/10.4028/www.scientific.net/msf.815.22.

Full text

Abstract:

Current ULSI circuits have features with dimensions in the nanoscale region. As the critical dimension shrinks, Cu BEOL systems face reliability impacts. Alloying has been proved to be a promising technique to retard grain boundary electro-migration (EM). In this paper, dilute Cu Alloys such as Cu-Al, Cu-Mn for dual-damascene interconnect applications have been investigated. The alloy chosen principle for nanoscale interconnects has been discussed. The ultrahigh purity copper alloy target properties including purity, alloy composition, grain size and sputtering performance were investigated, t

APA, Harvard, Vancouver, ISO, and other styles

5

Zama, S., D. F. Baldwin, T. Hikami, and H. Murata. "Flip chip interconnect systems using copper wire stud bump and lead free solder." IEEE Transactions on Electronics Packaging Manufacturing 24, no. 4 (2001): 261–68. http://dx.doi.org/10.1109/6104.980034.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Flinn, Paul A. "Measurement and interpretation of stress in copper films as a function of thermal history." Journal of Materials Research 6, no. 7 (1991): 1498–501. http://dx.doi.org/10.1557/jmr.1991.1498.

Full text

Abstract:

Since copper has some advantages relative to aluminum as an interconnection material, it is appropriate to investigate its mechanical properties in order to be prepared in advance for possible problems, such as the cracks and voids that have plagued aluminum interconnect systems. A model previously used to interpret the behavior of aluminum films proves to be, with minor modification, also applicable to copper. Although the thermal expansion of copper is closer to that of silicon and, consequently, the thermally induced strains are smaller, the much larger elastic modulus of copper results in

APA, Harvard, Vancouver, ISO, and other styles

7

Wang, Shi-Qing. "Barriers Against Copper Diffusion into Silicon and Drift Through Silicon Dioxide." MRS Bulletin 19, no. 8 (1994): 30–40. http://dx.doi.org/10.1557/s0883769400047710.

Full text

Abstract:

The Semiconductor Industry Association (SIA) roadmap calls for the incorporation of Cu plugs (vias) integrated with interconnects in 1997. Copper is being evaluated for ULSI metallization because of its lower bulk electrical resistivity and its superior resistance to electromigration and stress voiding as compared to commonly used aluminum and its alloys. One of the major drawbacks of Cu is its fast diffusion in Si and drift in SiO2-based dielectrics, resulting in the deterioration of devices at low temperatures. Hence a diffusion barrier is necessary between Cu and Si or SiO2. Figure 1 is a c

APA, Harvard, Vancouver, ISO, and other styles

8

Aubel, Oliver, Eberhard Bugiel, Dietmar Krüger, Wolfgang Hasse, and Martina Hommel. "Investigation of the influence of thermal treatment on interconnect-barrier interfaces in copper metallization systems." Microelectronics Reliability 46, no. 5-6 (2006): 768–73. http://dx.doi.org/10.1016/j.microrel.2005.10.010.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Ghannam, Ayad, Alessandro Magnani, David Bourrier, and Thierry Parra. "Wafer Level 3D System Integration using a Novel 3D-RDL Technology." International Symposium on Microelectronics 2015, no. 1 (2015): 000092–97. http://dx.doi.org/10.4071/isom-2015-tp36.

Full text

Abstract:

A new wafer-level 3D system integration process that relies on a novel multi-level 3D redistribution layer technology (3D-RDL) to interconnect chips together as well as to the substrate was developed. The 3D-RDL technology is based on a single electroplating step that allows routing high density, auto-adaptive vertical copper interconnects (20 μm Line/Space “L/S”) at the edge of known-good dies as well as redistribution layer on top of the die and the substrate. Furthermore, this technology enables 3D interconnection of stacked dies using a single 3D-RDL layer. Additionally, high performance 3

APA, Harvard, Vancouver, ISO, and other styles

10

Olivas, Richard, Rudy Salas, Dan Muse, et al. "Structural Electronics through Additive Manufacturing and Micro-Dispensing." International Symposium on Microelectronics 2010, no. 1 (2010): 000940–46. http://dx.doi.org/10.4071/isom-2010-tha5-paper6.

Full text

Abstract:

Implementing electronics systems that are conformal with curved and complex surfaces is difficult if not impossible with traditional fabrication techniques, which require stiff, two dimensional printed circuit boards (PCB). Flexible copper based fabrication is currently available commercially providing conformance, but not simultaneously stiffness. Consequently, these systems are susceptible to reliability problems if bent or stretched repeatedly. The integration of Additive Manufacturing (AM) combined with Direct Print (DP) micro-dispensing can provide shapes of arbitrary and complex form whi

APA, Harvard, Vancouver, ISO, and other styles

11

Tran, Tu Anh, Varughese Mathew, and Harold Downey. "Comparison of Gold and Copper Wire Bonding on Aluminum and Nickel-Palladium-Gold Bond Pads for Automotive Application." International Symposium on Microelectronics 2011, no. 1 (2011): 000589–99. http://dx.doi.org/10.4071/isom-2011-wa4-paper4.

Full text

Abstract:

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new au

APA, Harvard, Vancouver, ISO, and other styles

12

Rambausek, Lina, Bram Van Genabet, Anne Schwarz, Els Bruneel, Isabel Van Driessche, and Lieva Van Langenhove. "Essential Building Blocks of Fibrous Transistors, Part I: Gate Layer." Advances in Science and Technology 80 (September 2012): 83–89. http://dx.doi.org/10.4028/www.scientific.net/ast.80.83.

Full text

Abstract:

Abstract. During the last decade, research on intelligent textile systems progressed steadily. Today, science is focusing on full integration of electronics into textiles. E-textiles function like their rigid electronic companions but keep their textile properties. To interconnect components within the system, textile structures need to be equipped with electro-conductive properties. For flexible solar cells or fibrous transistors, electro-conductive coatings are applied. Transistors, acting as electrical switches, are essential for realizing fully integrated intelligent textile systems. By el

APA, Harvard, Vancouver, ISO, and other styles

13

Fresquet, G., D. Le Cunff, Th Raymond, and D. K. de Vries. "Control of 3D IC process steps by optical metrologies." International Symposium on Microelectronics 2015, no. 1 (2015): 000479–85. http://dx.doi.org/10.4071/isom-2015-wp53.

Full text

Abstract:

This paper evaluates various optical metrology techniques for in-line control of the uniformity of 3D stacked structures. Advanced packaging technologies are rapidly evolving and 3D architectures require very well controlled process steps. Optical metrology techniques are now used for TSV but also for interconnect processing. In engineering mode, at the process implementation step, these techniques must be evaluated and then used to get uniform and repeatable processes. Among the 3D TSV Via middle process flow, the temporary bonding, wafer thinning and TSV reveal are key 3D process steps to ge

APA, Harvard, Vancouver, ISO, and other styles

14

Kilian, Andreas, Michael Fuchs, and Lorenz-Peter Schmidt. "Design considerations for the hot embossing of microstrip antennas on plastic foils." International Journal of Microwave and Wireless Technologies 1, no. 4 (2009): 249–54. http://dx.doi.org/10.1017/s1759078709990213.

Full text

Abstract:

In this contribution, fundamental design considerations for a novel metallization technique to realize millimeter-wave microstrip structures are presented. This hot embossing technology is a fast and economic process originating from the production of three-dimensional molded interconnect devices. Conductive structures are coated onto plastic parts or plastic foils using a heated stamp. This approach shows high potential and therefore will be investigated for the fabrication of low-cost printed antennas at millimeter-wave frequencies. The focus of this contribution is on design guidelines cons

APA, Harvard, Vancouver, ISO, and other styles

15

Christensen, C. Paul. "Miniature MEMS Interface Circuits Using Nanoparticle Conductors and Embedded Components." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 001674–706. http://dx.doi.org/10.4071/2011dpc-wp22.

Full text

Abstract:

MEMS devices are typically used in subsystems comprising the MEMS component and the infrastructure required to support it. This infrastructure – signal processing, communication interface, power supply, and system packaging – often determines the size and cost of the subsystem. This paper describes a new approach to fabrication of highly miniaturized electronic circuitry and packaging that is well-suited to interfacing and support of MEMS components. The fabrication process utilizes nanoparticle silver conductors to connect miniature embedded surface-mount components. Interconnect conductors a

APA, Harvard, Vancouver, ISO, and other styles

16

Rasmussen, David J. "Gold Ball Wire Bonding with Heated Tool for Automotive Microelectronics." International Symposium on Microelectronics 2012, no. 1 (2012): 000410–13. http://dx.doi.org/10.4071/isom-2012-tp44.

Full text

Abstract:

Microelectronics used in automotive applications have grown considerably in the last few years with more high tech electronics controlling more functions in automobiles. In an effort to have more precise control and to reduce vehicle weight manufacturers are integrating more functions into smaller packages. Many of these packages are embedded in molded plastic. This causes challenges when it comes to wirebonding these devices. They often cannot be heated to traditional Gold Ball Thermosonic wirebonding temperatures of 120 – 150C. However, using a heated capillary to bond the parts which remain

APA, Harvard, Vancouver, ISO, and other styles

17

KANG, XIAOXU, QINGYUN ZUO, CHAO YUAN, SHOUMIAN CHEN, and YUHANG ZHAO. "LOW STRESS TaN THIN FILM DEVELOPMENT FOR MEMS/SENSOR ELECTRODE APPLICATION." Journal of Circuits, Systems and Computers 22, no. 09 (2013): 1340017. http://dx.doi.org/10.1142/s0218126613400173.

Full text

Abstract:

TaN \ Ta is the excellent material against copper diffusion, and is widely used as Cu diffusion barrier in Complementary Metal-Oxide-Semiconductor (CMOS) Back End of Line ( Cu -BEOL) process. Due to its good electrical and thermal property, TaN is also evaluated as electrode material for Micro-Electro-Mechanical Systems (MEMS)/sensor application. In this work, CMOS compatible MEMS based bolometer process with post-interconnect CMOS-MEMS single chip integration scheme was developed on 200 mm standard CMOS Cu BEOL, and TaN thin film was used as key electrode material in micro-bridge structure. T

APA, Harvard, Vancouver, ISO, and other styles

18

Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth, and Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.

Full text

Abstract:

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths &lt;100 m with narrow gaps between lines &lt;100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misa

APA, Harvard, Vancouver, ISO, and other styles

19

Kim, Dongjin, Yasuyuki Yamamoto, Shijo Nagao, Naoki Wakasugi, Chuantong Chen, and Katsuaki Suganuma. "Measurement of Heat Dissipation and Thermal-Stability of Power Modules on DBC Substrates with Various Ceramics by SiC Micro-Heater Chip System and Ag Sinter Joining." Micromachines 10, no. 11 (2019): 745. http://dx.doi.org/10.3390/mi10110745.

Full text

Abstract:

This study introduced the SiC micro-heater chip as a novel thermal evaluation device for next-generation power modules and to evaluate the heat resistant performance of direct bonded copper (DBC) substrate with aluminum nitride (AlN-DBC), aluminum oxide (DBC-Al2O3) and silicon nitride (Si3N4-DBC) ceramics middle layer. The SiC micro-heater chips were structurally sound bonded on the two types of DBC substrates by Ag sinter paste and Au wire was used to interconnect the SiC and DBC substrate. The SiC micro-heater chip power modules were fixed on a water-cooling plate by a thermal interface mate

APA, Harvard, Vancouver, ISO, and other styles

20

Tran, Tu Anh, Varughese Mathew, Wen Shi Koh, K. Y. Yow, and Y. K. Au. "Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application." International Symposium on Microelectronics 2012, no. 1 (2012): 001085–96. http://dx.doi.org/10.4071/isom-2012-thp31.

Full text

Abstract:

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new au

APA, Harvard, Vancouver, ISO, and other styles

21

Tran, Tu Anh, Varughese Mathew, Wen Shi Koh, K. Y. Yow, and Y. K. Au. "Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application." International Symposium on Microelectronics 2013, no. 1 (2013): 000657–62. http://dx.doi.org/10.4071/isom-2013-wp24.

Full text

Abstract:

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new au

APA, Harvard, Vancouver, ISO, and other styles

22

MacDonald, Eric, Ryan Wicker, David Espalin, Andy Kwas, and Peter Ruby Craig Kief. "3D Printing of High Voltage Printed Wiring Boards." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (2016): 000542–65. http://dx.doi.org/10.4071/2016dpc-ta34.

Full text

Abstract:

In the last decade, research has focused on 3D printing for not only creating conceptual models but functional end-use products as well. As patents for 3D printing expire, new low cost desktop systems are being adopted more widely. This trend is leading to products being fabricated locally and improving supply chain logistics. However, currently low cost 3D printing is limited in the number of materials used simultaneously in fabrication and consequently is confined to fabricating enclosures and conceptual models. For additively manufactured end-use products to be useful, supplementary feature

APA, Harvard, Vancouver, ISO, and other styles

23

Sahoo, Manodipan, and Hafizur Rahaman. "Modeling of Crosstalk Induced Effects in Copper-Based Nanointerconnects: An ABCD Parameter Matrix-Based Approach." Journal of Circuits, Systems and Computers 24, no. 02 (2014): 1540007. http://dx.doi.org/10.1142/s0218126615400071.

Full text

Abstract:

Aggressive miniaturization has led to severe performance and signal integrity issues in copper-based interconnects in the nanometric regime. As a consequence, development of a proper analytical model for such interconnects is extremely important. In this work, an ABCD parameter matrix-based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper-based nanointerconnect systems. Using the proposed model, the crosstalk delay and noise are estimated in copper based nanointerconnects for intermediate and global interconnects at the future inte

APA, Harvard, Vancouver, ISO, and other styles

24

Efimovskaya, A., and A. M. Shkel. "160 MILLI-OHM ELECTRICAL RESISTANCE THRU-WAFER INTERCONNECTS WITH 10:1 ASPECT RATIO." International Symposium on Microelectronics 2014, no. 1 (2014): 000505–10. http://dx.doi.org/10.4071/isom-wa51.

Full text

Abstract:

We present a novel approach for high-aspect ratio low resistance Thru-Wafer Interconnects for Double-Sided (TWIDS) fabrication of MicroElectroMechanical Systems (MEMS). The interconnects are formed by etching blind via holes in the handle substrate of an SOI (Silicon on Insulator) wafer, followed by filling the holes with copper, using sonic-assisted seedless copper electroplating process. This technique does not require additional conductive layer deposition, but utilizes a highly doped silicon device layer as a seed. The donut-shape gaps are etched around the copper filled vias to provide in

APA, Harvard, Vancouver, ISO, and other styles

25

Patel, Nikita, and Yash Agrawal. "A Literature Review on Next Generation Graphene Interconnects." Journal of Circuits, Systems and Computers 28, no. 09 (2019): 1930008. http://dx.doi.org/10.1142/s0218126619300083.

Full text

Abstract:

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the ov

APA, Harvard, Vancouver, ISO, and other styles

26

Ramm, Peter, Armin Klumpp, Alan Mathewson, Kafil M. Razeeb, and Reinhard Pufall. "The European 3D Heterogeneous Integration Platform (e-BRAINS) - a Particular Focus on Reliability and Low-Temperature Processes for 3D Integrated Sensor Systems." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001847–84. http://dx.doi.org/10.4071/2015dpc-tha11.

Full text

Abstract:

The European 3D heterogeneous integration platform has been established by the consortium of the Integrated Project e-BRAINS [1], where technologies of the following relevant main categories of 3D integration are provided to enable future applications of smart sensor systems:3D System-on-Chip Integration - 3D-SOC: TSV technology for stacking of thinned devices or large IC blocks (global level),3D Wafer-Level-Packaging - 3D-WLP: embedding technology with through-polymer vias (TPV) for stacking of thinned ICs on wafer-level (no TSV), and3D System-in-Package - 3D-SIP: 3D stacking of packaged devi

APA, Harvard, Vancouver, ISO, and other styles

27

Palavesam, Nagarajan, Waltraud Hell, Andreas Drost, Christof Landesberger, Christoph Kutter, and Karlheinz Bock. "Influence of Flexibility of the Interconnects on the Dynamic Bending Reliability of Flexible Hybrid Electronics." Electronics 9, no. 2 (2020): 238. http://dx.doi.org/10.3390/electronics9020238.

Full text

Abstract:

The growing interest towards thinner and conformable electronic systems has attracted significant attention towards flexible hybrid electronics (FHE). Thin chip-foil packages fabricated by integrating ultra-thin monocrystalline silicon integrated circuits (ICs) on/in flexible foils have the potential to deliver high performance electrical functionalities at very low power requirements while being mechanically flexible. However, only very limited information is available regarding the fatigue or dynamic bending reliability of such chip-foil packages. This paper reports a series of experiments w

APA, Harvard, Vancouver, ISO, and other styles

28

Sundaram, Rajyashree M., Atsuko Sekiguchi, Mizuki Sekiya, Takeo Yamada, and Kenji Hata. "Copper/carbon nanotube composites: research trends and outlook." Royal Society Open Science 5, no. 11 (2018): 180814. http://dx.doi.org/10.1098/rsos.180814.

Full text

Abstract:

We present research progress made in developing copper/carbon nanotube composites (Cu/CNT) to fulfil a growing demand for lighter copper substitutes with superior electrical, thermal and mechanical performances. Lighter alternatives to heavy copper electrical and data wiring are needed in automobiles and aircrafts to enhance fuel efficiencies. In electronics, better interconnects and thermal management components than copper with higher current- and heat-stabilities are required to enable device miniaturization with increased functionality. Our literature survey encouragingly indicates that Cu

APA, Harvard, Vancouver, ISO, and other styles

29

Sutherland, L., E. Igras, R. Ulmer, and P. Sargious. "A laboratory for testing the interoperability of telehealth systems." Journal of Telemedicine and Telecare 6, no. 2_suppl (2000): 74–75. http://dx.doi.org/10.1258/1357633001935671.

Full text

Abstract:

Interoperability allows telehealth equipment to interact to achieve predictable results. To address the need for telehealth interoperability, the Alberta Research Council has been working with the Alberta Health and Wellness organization in Canada, and others, to create guidelines and a facility for testing telehealth equipment for compliance with technical interoperability standards. The laboratory consists of two rooms (7m x 7 m) in a new building. The rooms are wired with easy-to-configure copper and fibre networks for telephone, Switch-56, ISDN, ATM, wireless and satellite services. One ro

APA, Harvard, Vancouver, ISO, and other styles

30

Mak, Cecilia Y. "Electroless Copper Deposition on Metals and Metal Silicides." MRS Bulletin 19, no. 8 (1994): 55–62. http://dx.doi.org/10.1557/s0883769400047758.

Full text

Abstract:

Chemical plating techniques have been used in silicon processing for many years for junction delineation and ohmic contact formation. In recent years, interest in this area has been renewed because of the potential use of electroless copper deposition for ultra-large-scale integration (ULSI) metallization and for the formation of thin metal etch masks for deep-ultraviolet lithography. Good deposition selectivity, low operating temperature, high copper purity, good filling characteristics, and planar topography have been among the many advantageous attributes reported from early investigations.

APA, Harvard, Vancouver, ISO, and other styles

31

Egitto, Frank D., Rabindra N. Das, Francesco Marconi, Bill Wilson, and Voya R. Markovich. "Development of Electronic Substrates for Medical Device Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 001527–46. http://dx.doi.org/10.4071/2012dpc-wa23.

Full text

Abstract:

There is a strong desire to develop advanced electronic substrates that can meet the growing demand for miniaturization, high-speed performance, and flexibility for medical devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present study, we are developin

APA, Harvard, Vancouver, ISO, and other styles

32

LAING, MARGARET, and ROGER LASS. "Shape-shifting, sound-change and the genesis of prodigal writing systems." English Language and Linguistics 13, no. 1 (2009): 1–31. http://dx.doi.org/10.1017/s1360674308002840.

Full text

Abstract:

In a series of articles we have looked at individual early Middle English writing systems and explored aspects of multivocal sound/symbol and symbol/sound relationships. This article combines previous observations with new material, and provides insights into the genesis of these relations and how they may interconnect. Since many early Middle English texts survive as copies, not originals, they may give clues to the orthographic systems of their exemplars too.We investigate the ‘extensibility’ of Litteral and Potestatic Substitution Sets. Writing systems may be economical or prodigal. The ‘id

APA, Harvard, Vancouver, ISO, and other styles

33

Georgescu, Simona Roxana, Alina Musetescu, Corina Daniela Ene, et al. "Relationship of Lichen Planus, Hepatitis Virus C and Low Level of Total Antioxidant Capacity." Internal Medicine 15, no. 5 (2018): 23–32. http://dx.doi.org/10.2478/inmed-2018-0035.

Full text

Abstract:

AbstractBased on the latest medical research, it is supposed that lichen planus is an inflammatory disorder, associated with autoimmune diseases, hepatitis C infection, oxidative stress or antioxidant deficiency. The purpose of the present work is to determine a panel of serum antioxidants, possibly involved in the development/persistence of the disease. The determination of extracellular antioxidants (bilirubin, uric acid, albumin, iron, transferrin, ferritin, copper, ceruloplasmin, total antioxidant capacity) in patients with lichen planus during exacerbations have revealed a significant red

APA, Harvard, Vancouver, ISO, and other styles

34

Ofek Almog, Rakefet, Hadar Ben-Yoav, Yelena Sverdlov, Tsvi Shmilovich, Slava Krylov, and Yosi Shacham-Diamand. "Integrated Polypyrrole Flexible Conductors for Biochips and MEMS Applications." Journal of Atomic, Molecular, and Optical Physics 2012 (August 9, 2012): 1–5. http://dx.doi.org/10.1155/2012/850482.

Full text

Abstract:

Integrated polypyrrole, a conductive polymer, interconnects on polymeric substrates were microfabricated for flexible sensors and actuators applications. It allows manufacturing of moving polymeric microcomponents suitable, for example, for micro-optical-electromechanical (MOEMS) systems or implanted sensors. This generic technology allows producing “all polymer” components where the polymers serve as both the structural and the actuating materials. In this paper we present two possible novel architectures that integrate polypyrrole conductors with other structural polymers: (a) polypyrrole em

APA, Harvard, Vancouver, ISO, and other styles

35

Korhonen, M. A., P. Børgesen, and Che-Yu Li. "Mechanisms of Stress-Induced and Electromigration-Induced Damage in Passivated Narrow Metallizations on Rigid Substrates." MRS Bulletin 17, no. 7 (1992): 61–69. http://dx.doi.org/10.1557/s0883769400041671.

Full text

Abstract:

Narrow, passivated metal lines are generally used as interconnects in VLSI microcircuits at the chip level. In most metals, high electric current densities lead to a mass flow of constituent atoms accompanying the current of electrons. Electromigration (EM) has long been considered an important reliability concern in the semiconductor industry because the current-induced atomic fluxes can give rise to void formation and open circuits, or hillock formation and short circuits between nearby interconnects. The problem is exacerbated because of the continued trend of increasing the density of the

APA, Harvard, Vancouver, ISO, and other styles

36

Fiorentzis, Konstantinos, Emmanuel Karapidakis, and Antonios Tsikalakis. "Cost Analysis of Demand-Side Generating Assets Contribution to Ancillary Services of Island Power Systems." Inventions 5, no. 3 (2020): 34. http://dx.doi.org/10.3390/inventions5030034.

Full text

Abstract:

Demand-Side Generating Assets (DSGAs) relate to existing small diesel Gensets serving the critical loads of infrastructures in unexpected electrical network interruptions. This paper investigates the exploitation of DSGA as potential suppliers of ancillary services (AS), especially in the case of isolated or weak interconnected island power systems such as in Crete. In this regard, their impact on substations’ loading reductions and associated copper losses is presented, using a substation as a case study with a typical touristic load in Crete. DSGA’s impact on such a significant part of relia

APA, Harvard, Vancouver, ISO, and other styles

37

Singh, Gurminder, Jean-Michel Missiaen, Didier Bouvard, and Jean-Marc Chaix. "Copper additive manufacturing using MIM feedstock: adjustment of printing, debinding, and sintering parameters for processing dense and defectless parts." International Journal of Advanced Manufacturing Technology 115, no. 1-2 (2021): 449–62. http://dx.doi.org/10.1007/s00170-021-07188-y.

Full text

Abstract:

AbstractIn the present study, an additive manufacturing process of copper using extrusion 3D printing, solvent and thermal debinding, and sintering was explored. Extrusion 3D printing of metal injection moulding (MIM) feedstock was used to fabricate green body samples. The printing process was performed with optimized parameters to achieve high green density and low surface roughness. To remove water-soluble polymer, the green body was immersed in water for solvent debinding. The interconnected voids formed during solvent debinding were favorable for removing the backbone polymer from the brow

APA, Harvard, Vancouver, ISO, and other styles

38

Cho, Sangbeom, Venky Sundaram, Rao Tummala, and Yogendra Joshi. "Multi-scale thermal modeling of glass interposer for mobile electronics application." International Journal of Numerical Methods for Heat & Fluid Flow 26, no. 3/4 (2016): 1157–71. http://dx.doi.org/10.1108/hff-09-2015-0378.

Full text

Abstract:

Purpose – The functionality of personal mobile electronics continues to increase, in turn driving the demand for higher logic-to-memory bandwidth. However, the number of inputs/outputs supported by the current packaging technology is limited by the smallest achievable electrical line spacing, and the associated noise performance. Also, a growing trend in mobile systems is for the memory chips to be stacked to address the growing demand for memory bandwidth, which in turn gives rise to heat removal challenges. The glass interposer substrate is a promising packaging technology to address these e

APA, Harvard, Vancouver, ISO, and other styles

39

Wickham, Martin, Kate Clayton, Ana Robador, and Christine Thorogood. "Organic Hybrids for Circuit Assemblies – Initial environmental testing of a low cost alternative to ceramic substrate based assemblies." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (2018): 000022–27. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000022.

Full text

Abstract:

Abstract There are an increasing number of electronics applications in aerospace, automotive, shale/gas and power management, which are required to operate at or above 200 °C. Organic matrix reinforced substrates such as polyimide, have maximum operating temperatures in the region of 175 °C. Reliable operation of electronics at temperatures higher than this requires a combination of performance improvements in components, interconnects and substrates. Ceramic based substrate options are based on alumina substrates with printed inks fired at ~ 600 °C and can be costly, heavy and prone to mechan

APA, Harvard, Vancouver, ISO, and other styles

40

Bailey, John, Alexander Pfeiffenberger, Charles Ellis, Mike Palmer, Tamara Issac-Smith, and Michael Hamilton. "Thin-Film Signal and Power Redistribution Layers Based on AL-X and Cu." International Symposium on Microelectronics 2012, no. 1 (2012): 000326–33. http://dx.doi.org/10.4071/isom-2012-tp26.

Full text

Abstract:

Use of unpackaged die in advanced integrated systems (i.e., 3-D integrated systems) calls for dense interconnection schemes with controlled impedance for high-speed signal routing and minimal impedance for efficient power distribution. We have evaluated a new material set for use in a thin-film-based redistribution layer (RDL) that consists of Asahi Glass AL-X spin-on low-k dielectric polymer and electroplated copper metallization. This technology allows fan-out and interconnection of high-speed signals and power to/from die pads on pitches sufficiently less than 100 μm directly to companion d

APA, Harvard, Vancouver, ISO, and other styles

41

Kontonikas-Charos, Alkis, Cristiana L. Ciobanu, Nigel J. Cook, et al. "Feldspar mineralogy and rare-earth element (re)mobilization in iron-oxide copper gold systems from South Australia: a nanoscale study." Mineralogical Magazine 82, S1 (2018): S173—S197. http://dx.doi.org/10.1180/minmag.2017.081.040.

Full text

Abstract:

ABSTRACTNanoscale characterization (TEM on FIB-SEM-prepared foils) was undertaken on feldspars undergoing transformation from early post-magmatic (deuteric) to hydrothermal stages in granites hosting the Olympic Dam Cu-U-Au-Ag deposit, and from the Cu-Au skarn at Hillside within the same iron-oxide copper-gold (IOCG) province, South Australia. These include complex perthitic textures, anomalously Ba-, Fe-, or REE-rich compositions, and REE-flourocarbonate + molybdenite assemblages which pseudomorph pre-existing feldspars. Epitaxial orientations between cryptoperthite (magmatic), patch perthite

APA, Harvard, Vancouver, ISO, and other styles

42

Amalu, E. H., N. N. Ekere, R. S. Bhatti, S. Mallik, G. Takyi, and A. O. Akii Ibhadode. "Numerical Investigation of Thermo-Mechanical Behaviour of Ball Grid Array Solder Joint at High Temperature Excursion." Advanced Materials Research 367 (October 2011): 287–92. http://dx.doi.org/10.4028/www.scientific.net/amr.367.287.

Full text

Abstract:

The solder joints of surface mount components (SMCs) experience thermal degradation culminating in creep and plastic shear strain deformation when subjected to cyclic temperature load over time. Degradation at the joints is due to thermal stress induced by the incompatible, differential and nonlinear expansion mismatch of the different bonded materials in the assembly. The stress magnitude influences the strain behaviour. Plastic strain response of solder joint is critical at the materials interface at the lower part of the joint due to the occurrence of wider variation in the coefficient of t

APA, Harvard, Vancouver, ISO, and other styles

43

Liu, Jia-Bao, Hafiz Usman Afzal, and Muhammad Javaid. "Computing Edge Weights of Magic Labeling on Rooted Products of Graphs." Mathematical Problems in Engineering 2020 (September 29, 2020): 1–16. http://dx.doi.org/10.1155/2020/2160104.

Full text

Abstract:

Labeling of graphs with numbers is being explored nowadays due to its diverse range of applications in the fields of civil, software, electrical, and network engineering. For example, in network engineering, any systems interconnected in a network can be converted into a graph and specific numeric labels assigned to the converted graph under certain rules help us in the regulation of data traffic, connectivity, and bandwidth as well as in coding/decoding of signals. Especially, both antimagic and magic graphs serve as models for surveillance or security systems in urban planning. In 1998, Enom

APA, Harvard, Vancouver, ISO, and other styles

44

Sproewitz, Tom, Udayan Banik, Jan-Thimo Grundmann, et al. "Concept for a Gossamer solar power array using thin-film photovoltaics." CEAS Space Journal 12, no. 1 (2019): 125–35. http://dx.doi.org/10.1007/s12567-019-00276-6.

Full text

Abstract:

Abstract In recent years, the German Aerospace Center (DLR) developed Gossamer deployment systems in different projects. As power requirements of spacecraft are getting more and more demanding, DLR recently focused on the development of new deployable photovoltaic (PV) technologies that are suitable for generating 10’s of kW per array. Possible space applications that may also require high power supply are missions using electric propulsion such as interplanetary missions, placing of geostationary (GEO) satellites in their orbit or even more future oriented as space tugs or lightweight power g

APA, Harvard, Vancouver, ISO, and other styles

45

Zhao, Bin, and Maureen Brongo. "Integration of Low Dielectric Constant Materials in Advanced Aluminum and Copper Interconnects." MRS Proceedings 564 (1999). http://dx.doi.org/10.1557/proc-564-485.

Full text

Abstract:

AbstractAdvanced on-chip interconnects using new materials and new integration architectures are necessary for current and future IC chips in order to meet the requirements in performance, reliability and manufacturing cost. Insulating materials with low dielectric constant (low-κ) and conductive materials with low-resistivity have drawn significant attention for their possible applications in IC interconnects. Dual damascene interconnect integration architectures not only offer process simplification and low cost, but also enable the use of low-resistive Cu for interconnect wiring. Use of low

APA, Harvard, Vancouver, ISO, and other styles

46

Zhao, Bin, and Maureen Brongo. "Integration of Low Dielectric Constant Materials in Advanced Aluminum and Copper Interconnects." MRS Proceedings 565 (1999). http://dx.doi.org/10.1557/proc-565-137.

Full text

Abstract:

AbstractAdvanced on-chip interconnects using new materials and new integration architectures are necessary for current and future IC chips in order to meet the requirements in performance, reliability and manufacturing cost. Insulating materials with low dielectric constant (low-κ) and conductive materials with low-resistivity have drawn significant attention for their possible applications in IC interconnects. Dual damascene interconnect integration architectures not only offer process simplification and low cost, but also enable the use of low-resistive Cu for interconnect wiring. Use of low

APA, Harvard, Vancouver, ISO, and other styles

47

Shen, Y. L., та E. S. Ege. "Thermomechanical Stresses in Copper Interconnect/Low-κ Dielectric Systems". MRS Proceedings 812 (2004). http://dx.doi.org/10.1557/proc-812-f6.26.

Full text

Abstract:

AbstractNumerical simulations of thermal stresses in copper interconnect and low-κ dielectric systems are carried out. The analyses include two- and three-dimensional finite element modeling of the interconnect structure. Various combinations of metal, oxide and polymer-based low-κ dielectric schemes are considered in the simulation. The evolution of stresses and deformation pattern in copper, barrier layers, and the dielectrics are critically assessed.

APA, Harvard, Vancouver, ISO, and other styles

48

"Physical properties of ceramic-glass-copper micro-interconnect systems for VLSI/VHSIC packaging applications." Microelectronics Journal 20, no. 3 (1989): 52. http://dx.doi.org/10.1016/0026-2692(89)90025-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Borland, William, and Vincent P. Siuta. "Materials Interactions in the Firing of Copper Thick Film Multilayer Ceramics." MRS Proceedings 108 (1987). http://dx.doi.org/10.1557/proc-108-287.

Full text

Abstract:

ABSTRACTIn recent years, copper thick film materials have gained rapid acceptance in ceramic multilayer interconnect boards because of their ability to meet advanced packaging requirements at reasonable cost. With high volume production, however, problems such as opens, shorts, blisters and porosity have been experienced. Many of these failures may be attributed to undesirable materials interactions caused by reducing conditions which can be caused by incomplete burnout of thick film organics during firing.This paper considers the interactions in current copper thick film material systems. Pri

APA, Harvard, Vancouver, ISO, and other styles

50

Davis, Jeffrey A., John C. Eble, Vivek K. De, and James D. Meindl. "A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)." MRS Proceedings 427 (1996). http://dx.doi.org/10.1557/proc-427-23.

Full text

Abstract:

AbstractBased on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon diox

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!