Relevant bibliographies by topics / Core Reconfiguration / Dissertations / Theses
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Dissertations / Theses on the topic 'Core Reconfiguration'

Author: Grafiati
Published: 9 March 2023
Last updated: 31 July 2025

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1

Ballagh, Jonathan Bartlett. "An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/33649.

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FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process are discussed, including implementation, sim
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2

BALBONI, Marco. "NoC-Centric Partitionin and Reconfiguration Technology for the Efficient Sharing of General-Purose Prorammable Many-core Accelerators." Doctoral thesis, Università degli studi di Ferrara, 2016. http://hdl.handle.net/11392/2403510.

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Negli ultimi decenni si sta assistendo ad una crescita tecnologica senza precedenti al centro dell’affermazione dei sistemi embedded, con la Legge di Moore come fattore dominante nel sostenere questo trend. Al giorno d’oggi, infatti, un sempre maggiore numero di cores può essere integrato nello stesso die, segnando il passaggio dallo Stato dell’Arte rappresentato dai chips multi-core ai nuovi paradigmi di design di chips manycore. Proprio questi chips many-core presentano un duplice scopo: fornire alte performance computazionalieaumentarel’efficienzadell’hardwareinterminidiOPS/Watt. Nonostante la
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3

Khuat, Quang Hai. "Definition and evaluation of spatio-temporal scheduling strategies for 3D multi-core heterogeneous architectures." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S007/document.

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Empilant une couche multiprocesseur (MPSoC) et une couche de FPGA pour former un système sur puce reconfigurable en trois dimension (3DRSoC), est une solution prometteuse donnant un niveau de flexibilité élevé en adaptant l'architecture aux applications visées. Pour une application exécutée sur ce système, l'un des principaux défis vient de la gestion de haut niveau des tâches. Cette gestion est effectuée par le service d'ordonnancement du système d'exploitation et elle doit être en mesure de déterminer, lors de l'exécution de l'application, quelle tâche est exécutée logiciellement et/ou matér
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4

Gammoudi, Aymen. "Stratégie de placement et d'ordonnancement de taches logicielles pour architectures reconfigurables sous contrainte énergétique." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S030/document.

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La conception de systèmes temps-réel embarqués se développe de plus en plus avec l’intégration croissante de fonctionnalités critiques pour les applications de surveillance, notamment dans le domaine biomédical, environnemental, domotique, etc. Le développement de ces systèmes doit relever divers défis en termes de minimisation de la consommation énergétique. Gérer de tels dispositifs embarqués, entièrement autonomes, nécessite cependant de résoudre différents problèmes liés à la quantité d’énergie disponible dans la batterie, à l’ordonnancement temps-réel des tâches qui doivent être exécutées
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5

Fuguet, Tortolero César. "Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente." Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066462/document.

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L'augmentation continue de la puissance de calcul requise par les applications telles que la cryptographie, la simulation, ou le traitement du signal a fait évoluer la structure interne des processeurs vers des architectures massivement parallèles (dites « many-core »). Ces architectures peuvent contenir des centaines, voire des milliers de cœurs afin de fournir une puissance de calcul importante avec une consommation énergétique raisonnable. Néanmoins, l'importante densité de transistors fait que ces architectures sont très susceptibles aux pannes matérielles. L'augmentation dans la variabili
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6

Fuguet, Tortolero César. "Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente." Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066462.

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L'augmentation continue de la puissance de calcul requise par les applications telles que la cryptographie, la simulation, ou le traitement du signal a fait évoluer la structure interne des processeurs vers des architectures massivement parallèles (dites « many-core »). Ces architectures peuvent contenir des centaines, voire des milliers de cœurs afin de fournir une puissance de calcul importante avec une consommation énergétique raisonnable. Néanmoins, l'importante densité de transistors fait que ces architectures sont très susceptibles aux pannes matérielles. L'augmentation dans la variabili
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7

Grand, Michaël. "Conception d’un crypto-système reconfigurable pour la radio logicielle sécurisée." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14388/document.

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Les travaux de recherche détaillés dans ce document portent sur la conception et l’implantation d’un composant matériel jouant le rôle du sous-système cryptographique d’une radio logicielle sécurisée.A partir du début des années 90, les systèmes radios ont peu à peu évolué de la radio classique vers la radio logicielle. Le développement de la radio logicielle a permis l’intégration d’un nombre toujours plus grand de standards de communication sur une même plateforme matérielle. La réalisation concrète d’une radio logicielle sécurisée amène son concepteur à faire face à de nombreuses problémati
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8

Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

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La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion.
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9

Abdelrahman, Tarig. "Evaluation of Wales Postgraduate Medical and Dental Education Deanery outcomes at core and higher general surgery before and after national reconfiguration, enhanced selection, and Joint Committee on Surgical Training defined curricular standards." Thesis, Cardiff University, 2017. http://orca.cf.ac.uk/100975/.

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This thesis examines contemporary outcomes of surgical training in Wales and the UK. The hypotheses tested were: Core Surgical Training (CST) outcome is related to specific curricular defined goals, and themed focused CST rotations improve success at National Training Number (NTN)appointment; CST rotations including rural placements provide training comparable with non-rural placements; General Surgery (GS) Certificate of Completion of Training (CCT) curricular guidelines require focused appraisal and rotation planning; GS Higher Surgical Trainee (HST) indicative procedure targets are not in k
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10

Krill, Benjamin. "A reconfigurable environment for IP cores implementation using dynamic partial reconfiguration." Thesis, University of Ulster, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.556481.

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Hardware acceleration is becoming increasingly important in high performance applications due to their computational complexity. Recently, field programmable gate arrays (FPGAs) have gained popularity as a suitable platform for many high performance applications. FPGAs offer low power, reconfigurability, high performance and low design- turnaround time which enable FPGAs to be used in a number of image and signal processing applications. Due to the increasing complexity of acceleration systems, abstraction of these technologies and power dissipation has become one of the most important challen
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11

GIULIANO, Fabrizio. "Supporting code mobility and dynamic reconfigurations over Wireless MAC Processor Prototype." Doctoral thesis, Università degli Studi di Palermo, 2014. http://hdl.handle.net/10447/91036.

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Mobile networks for Internet Access are a fundamental segment of Internet access net- works, where resource optimization are really critical because of the limited bandwidth availability. While traditionally resource optimizations have been focused on high effi- cient modulation and coding schemes, to be dynamically tuned according to the wireless channel and interference conditions, it has also been shown how medium access schemes can have a significant impact on the network performance according to the application and networking scenarios. This thesis work proposes an architectural solution
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12

CHIESA, DAVIDE. "Development and experimental validation of a Monte Carlo simulation model for the Triga Mark II reactor." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2014. http://hdl.handle.net/10281/50064.

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In recent years, many computer codes, based on Monte Carlo methods or deterministic calculations, have been developed to separately analyze different aspects regarding nuclear reactors. Nuclear reactors are very complex systems, which require an integrated analysis of all the variables which are intrinsically correlated: neutron fluxes, reaction rates, neutron moderation and absorption, thermal and power distributions, heat generation and transfer, criticality coefficients, fuel burnup, etc. For this reason, one of the main challenges in the analysis of nuclear reactors is the coupling o
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13

Arad, Cosmin Ionel. "Programming Model and Protocols for Reconfigurable Distributed Systems." Doctoral thesis, KTH, Programvaruteknik och Datorsystem, SCS, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-122311.

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Distributed systems are everywhere. From large datacenters to mobile devices, an ever richer assortment of applications and services relies on distributed systems, infrastructure, and protocols. Despite their ubiquity, testing and debugging distributed systems remains notoriously hard. Moreover, aside from inherent design challenges posed by partial failure, concurrency, or asynchrony, there remain significant challenges in the implementation of distributed systems. These programming challenges stem from the increasing complexity of the concurrent activities and reactive behaviors in a distrib
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14

Arad, Cosmin. "Programming Model and Protocols for Reconfigurable Distributed Systems." Doctoral thesis, SICS, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:ri:diva-24202.

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Distributed systems are everywhere. From large datacenters to mobile devices, an ever richer assortment of applications and services relies on distributed systems, infrastructure, and protocols. Despite their ubiquity, testing and debugging distributed systems remains notoriously hard. Moreover, aside from inherent design challenges posed by partial failure, concurrency, or asynchrony, there remain significant challenges in the implementation of distributed systems. These programming challenges stem from the increasing complexity of the concurrent activities and reactive behaviors in a distrib
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15

Borde, Etienne. "Configuration et Reconfiguration des Systèmes Temps-Reél Répartis Embarqués Critiques et Adaptatifs." Phd thesis, Télécom ParisTech, 2009. http://pastel.archives-ouvertes.fr/pastel-00563947.

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Aujourd'hui, de plus en plus de systèmes industriels s'appuient sur des applications logicielles temps-réel réparties embarquées (TR2E). La réalisation de ces applications demande de répondre à un ensemble important de contraintes très hétérogènes, voire contradictoires. Pour satisfaire ces contraintes, il est presque toujours nécessaire de fournir à ces systèmes des capacités d'adaptation. Par ailleurs, certaines de ces applications pilotent des systèmes dont la défection peut avoir des conséquences financières - voire humaines - dramatiques. Pour concevoir de telles applic
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16

Hentati, Manel. "Reconfiguration dynamique partielle de décodeurs vidéo sur plateformes FPGA par une approche méthodologique RVC (Reconfigurable Video Coding)." Rennes, INSA, 2012. http://www.theses.fr/2012ISAR0027.

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Les travaux présentés dans cette thèse s'inscrivent dans le cadre de la conception et l'implémentation des décodeurs reconfigurables en utilisant la norme MPEG-RVC. Cette norme est développée par MPEG. Elle permet une grande flexibilité et la réutilisation des normes existantes dans un processus de reconfiguration des solutions de décodage. RVC fournit une nouvelle spécification basée sur une modélisation à flux de données nommée RVC-CAL. Dans ce travail, nous proposons une méthodologie de prototypage rapide permettant une implémentation efficace et optimisée des décodeurs reconfigurables RVC
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17

Constantin, Nicolas 1964. "Analysis and design of a gated envelope feedback technique for automatic hardware reconfiguration of RFIC power amplifiers, with full on-chip implementation in gallium arsenide heterojunction bipolar transistor technology." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=115666.

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In this doctoral dissertation, the author presents the theoretical foundation, the analysis and design of analog and RF circuits, the chip level implementation, and the experimental validation pertaining to a new radio frequency integrated circuit (RFIC) power amplifier (PA) architecture that is intended for wireless portable transceivers.<br>A method called Gated Envelope Feedback is proposed to allow the automatic hardware reconfiguration of a stand-alone RFIC PA in multiple states for power efficiency improvement purposes. The method uses self-operating and fully integrated circuitry compri
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18

Cardoso, Jason Barbosa. "Reconfiguração ótima para cortes de cargas em sistemas de distribuição de energia elétrica." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/18/18154/tde-06092016-104021/.

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Neste trabalho é proposta uma modelagem matemática para a otimização do problema de corte de carga em sistemas de distribuição de energia elétrica radiais. O problema de corte de carga consiste em uma estratégia de reconfiguração topológica da rede elétrica para interrupção do fornecimento de energia elétrica. O objetivo principal é desligar a quantidade mínima de carga do sistema, de forma a manter restrições físicas e operacionais dentro dos limites da rede elétrica. Um segundo objetivo é alterar o mínimo possível a estrutura topológica inicial do sistema. Para isso, é feita a minimização de
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19

Borges, Guilherme Pereira. "Metodologia para planejamento de ações de alívio de carregamento em sistemas de distribuição de energia elétrica em média tensão." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/18/18154/tde-02082017-165127/.

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O objetivo desta tese é desenvolver e implementar em computador uma metodologia para resolver o problema de alívio de carregamento utilizando técnicas de remanejamento ou corte de carga. Tal metodologia, fundamenta-se no Algoritmo Evolutivo Multiobjetivo em Tabelas, que foi desenvolvido inicialmente para o problema de restabelecimento de energia em sistemas de distribuição. Já metodologia desenvolvida nesta tese trata o problema de alívio de carregamento, buscando minimizar o número de consumidores sem fornecimento de energia elétrica e o número de operações de chaveamento. Todavia, é necessár
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20

Annamalai, Arunachalam. "A Dynamic Reconfiguration Framework to Maximize Performance/Power in Asymmetric Multicore Processors." 2013. https://scholarworks.umass.edu/theses/1104.

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Recent trends in technology scaling have shifted the processing paradigm to multicores. Depending on the characteristics of the cores, the multicores can be either symmetric or asymmetric. Prior research has shown that Asymmetric Multicore Processors (AMPs) outperform their symmetric (SMP) counterparts within a given resource and power budget. But, due to the heterogeneity in core-types and time-varying workload behavior, thread-to-core assignment is always a challenge in AMPs. As the computational requirements vary significantly across different applications and with time, there is a need to
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21

Couture, Stéphane. "Le code source informatique comme artefact dans les reconfigurations d'Internet." Thèse, 2012. http://www.archipel.uqam.ca/5210/1/D2415.pdf.

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Cette thèse en communication porte sur le code source informatique. Le code source est l'objet de la programmation informatique et peut être défini comme un ensemble de commandes informatiques humainement lisibles, « écrites » dans un langage de programmation de haut niveau (Krysia et Grzesiek, 2008). Depuis quelques années, le code source fait l'objet d'une signification sociale et politique grandissante. Le mouvement du logiciel libre place par exemple au cœur de sa politique le libre accès au code source. Ce mouvement a d'ailleurs permis l'émergence de nombreux collectifs articulés autour d
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22

Kai-ChunLin and 林楷鈞. "Power-Comparison-based Eavesdropping Detection and Signature Reconfiguration for Optical Code-Division Multiple- Access Networks." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ztpc5a.

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碩士<br>國立成功大學<br>電腦與通信工程研究所<br>106<br>In communication networks, security is traditionally divided into three categories: integrity, confidentiality and availability. Potentially, optical code-division multiple-access (OCDMA) system may provide both confidentiality and availability protection. Therefore, OCDMA has been seen as a superior candidate to offer confidentiality. However, OCDMA techniques still suffer from inherent security disadvantages, such as eavesdropping by an attacker with specific device to intercept and recover the transmitted signals that has been encoded. In this thesis, a
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