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Journal articles on the topic 'Core Reconfiguration'

Author: Grafiati

Published: 9 March 2023

Last updated: 31 July 2025

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1

Wanta, Damian, Waldemar T. Smolik, Jacek Kryszyn, Przemysław Wróblewski, and Mateusz Midura. "A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System." Electronics 11, no. 4 (2022): 545. http://dx.doi.org/10.3390/electronics11040545.

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A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA

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Hou, Bowen, Dali Xu, Fangfa Fu, Bing Yang, and Na Niu. "An Optimized Core Distribution Adaptive Topology Reconfiguration Algorithm for NoC-Based Embedded Systems." Micromachines 16, no. 4 (2025): 421. https://doi.org/10.3390/mi16040421.

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In advanced multicore embedded systems, network-on-chip (NoC) is vital for core communication. With a rise in the number of cores, the incidence of core failures rises, potentially affecting system performance and stability. To address the challenges associated with core failures in network-on-chip (NoC) systems, researchers have proposed numerous topology reconfiguration algorithms. However, these algorithms fail to achieve an optimal balance between topology reconfiguration rate and recovery time. Addressing these issues, we propose an adaptive core distribution optimization topology reconfi

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Abdelrahman, T., C. Thomas, A. Iorwerth, MJ Pollitt, M. Holt, and WG Lewis. "Core surgical training outcome in Wales." Bulletin of the Royal College of Surgeons of England 98, no. 10 (2016): 456–59. http://dx.doi.org/10.1308/rcsbull.2016.457.

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Li, Ji, Huagang Xiong, Qiao Li, Feng Xiong, and Jiaying Feng. "Run-Time Reconfiguration Strategy and Implementation of Time-Triggered Networks." Electronics 11, no. 9 (2022): 1477. http://dx.doi.org/10.3390/electronics11091477.

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Time-triggered networks are deployed in avionics and astronautics because they provide deterministic and low-latency communications. Remapping of partitions and the applications that reside in them that are executing on the failed core and the resulting re-routing and re-scheduling are conducted when a permanent end-system core failure occurs and local resources are insufficient. We present a network-wide reconfiguration strategy as well as an implementation scheme, and propose an Integer Linear Programming based joint mapping, routing, and scheduling reconfiguration method (JILP) for global r

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Suri, Tameesh, and Aneesh Aggarwal. "Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration." International Journal of Parallel Programming 38, no. 3-4 (2010): 203–24. http://dx.doi.org/10.1007/s10766-010-0128-3.

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Soh, Takehide, Tomoya Tanjo, Yoshio Okamoto, and Takehiro Ito. "CoRe Challenge 2022/2023: Empirical Evaluations for Independent Set Reconfiguration Problems (Extended Abstract)." Proceedings of the International Symposium on Combinatorial Search 17 (June 1, 2024): 285–86. http://dx.doi.org/10.1609/socs.v17i1.31583.

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In this extended abstract, we describe CoRe Challenge 2022/2023, an international competition series aiming to construct the technical foundation of practical research for Combinatorial Reconfiguration. This competition series targets one of the most well-studied reconfiguration problems, called the independent set reconfiguration problem under the token jumping model, which asks a step-by-step transformation between two given independent sets in a graph. Theoretically, the problem is PSPACE-complete, which implies that there exist instances such that even a shortest transformation requires su

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Prabhu, Gayathri R., Bibin Johnson, and J. Sheeba Rani. "Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration." International Journal of Reconfigurable Computing 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/243835.

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A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for a

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Zuo, Nianming, Zhengyi Yang, Yong Liu, Jin Li, and Tianzi Jiang. "Core networks and their reconfiguration patterns across cognitive loads." Human Brain Mapping 39, no. 9 (2018): 3546–57. http://dx.doi.org/10.1002/hbm.24193.

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Yi, Lim, Anh Vu Le, Balakrishnan Ramalingam, et al. "Locomotion with Pedestrian Aware from Perception Sensor by Pavement Sweeping Reconfigurable Robot." Sensors 21, no. 5 (2021): 1745. http://dx.doi.org/10.3390/s21051745.

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Regular washing of public pavements is necessary to ensure that the public environment is sanitary for social activities. This is a challenge for autonomous cleaning robots, as they must adapt to the environment with varying pavement widths while avoiding pedestrians. A self-reconfigurable pavement sweeping robot, named Panthera, has the mechanisms to perform reconfiguration in width to enable smooth cleaning operations, and it changes its behavior based on environment dynamics of moving pedestrians and changing pavement widths. Reconfiguration in the robot’s width is possible, due to the scis

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Prasad Acharya, G., and M. Asha Rani. "Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 3 (2018): 160. http://dx.doi.org/10.11591/ijres.v6.i3.pp160-168.

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<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show

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Lyric, Zoairia Idris, Mohammad Sayem Mahmood, and Mohammad Abdul Motalab. "A study on TRIGA core reconfiguration with new irradiation channels." Annals of Nuclear Energy 43 (May 2012): 183–86. http://dx.doi.org/10.1016/j.anucene.2011.12.034.

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12

OKLOPCIC, ZORAN. "Beyond Empty, Conservative, and Ethereal: Pluralist Self-Determination and a Peripheral Political Imaginary." Leiden Journal of International Law 26, no. 3 (2013): 509–29. http://dx.doi.org/10.1017/s0922156513000216.

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AbstractOver the last couple of years, a stream of pluralist theories of international legal order has developed at the intersection of international law and political theory, having immediate implications for conceptualizing self-determination. The understanding of self-determination under the framework ofbounded,constitutional, andradicalpluralism markedly departs from the previous wave of normative theories in the 1990s: self-determination is now evacuated from the field of national pluralism and struggles over territory.This article does not question the thrust of pluralists’ recent work,

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Ma, Hongjia, Qing Sun, Yang Gao, and Yuan Gao. "Resource Integration, Reconfiguration, and Sustainable Competitive Advantages: The Differences between Traditional and Emerging Industries." Sustainability 11, no. 2 (2019): 551. http://dx.doi.org/10.3390/su11020551.

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Emerging industries bear great difference from traditional industries. It is valuable to explore the effectiveness of different resource management methods in the two industries. Based on this, the purposes of this paper are first to define and distinguish two core resource management methods (i.e., resource integration and resource reconfiguration), and second to research the different impact paths of resource integration and resource reconfiguration on the sustainable competitive advantages in different industries. Primarily, in order to achieve these purposes, this paper explores the genera

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Hamman, Joseph J., Bart Nijssen, Theodore J. Bohn, Diana R. Gergel, and Yixin Mao. "The Variable Infiltration Capacity model version 5 (VIC-5): infrastructure improvements for new applications and reproducibility." Geoscientific Model Development 11, no. 8 (2018): 3481–96. http://dx.doi.org/10.5194/gmd-11-3481-2018.

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Abstract. The Variable Infiltration Capacity (VIC) model is a macroscale semi-distributed hydrologic model. VIC development began in the early 1990s and the model has since been used extensively for basin- to global-scale applications that include hydrologic dataset construction, trend analysis of hydrologic fluxes and states, data evaluation and assimilation, forecasting, coupled climate modeling, and climate change impact assessment. Ongoing operational applications of the VIC model include the University of Washington's drought monitoring and forecasting systems and NASA's Land Data Assimil

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Verdoscia, Lorenzo, and Roberto Giorgi. "A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs." Mathematical Problems in Engineering 2016 (May 16, 2016): 1–21. http://dx.doi.org/10.1155/2016/3190234.

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We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly.

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Kurniadi, Kezia Amanda, and Kwangyeol Ryu. "Development of Multi-Disciplinary Green-BOM to Maintain Sustainability in Reconfigurable Manufacturing Systems." Sustainability 13, no. 17 (2021): 9533. http://dx.doi.org/10.3390/su13179533.

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The reconfigurable manufacturing system (RMS) appears to be eco-friendly while coping with rapidly changing market demands. However, there remains a lack of discussion or research regarding sustainability or environment-friendly functions within RMS. In this study, the reconfiguration planning problem is introduced to represent the core issues within the RMS. Reconfiguration occurs depending on new demands or conditions in the company by reconfiguring machines, such as removing, adding, or changing parts, giving considerable consideration to arrangement of machines, known as configurations in

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Shen, Lili, Ning Wu, and Gaizhen Yan. "Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches." Electronics 9, no. 2 (2020): 346. http://dx.doi.org/10.3390/electronics9020346.

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By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that si

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Astarloa, Armando, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, and Jaime Jiménez. "Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs." Journal of Systems Architecture 53, no. 9 (2007): 629–43. http://dx.doi.org/10.1016/j.sysarc.2007.01.011.

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19

Nolting, Stephan, Guillermo Payá-Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, and Christian Müller-Schloer. "Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture." Journal of Parallel and Distributed Computing 133 (November 2019): 391–406. http://dx.doi.org/10.1016/j.jpdc.2017.09.013.

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20

Liu, Fucheng, Yining Liu, Qian Liu, et al. "Tunable annular plasma photonic crystals in dielectric barrier discharge." Plasma Sources Science and Technology 31, no. 2 (2022): 025015. http://dx.doi.org/10.1088/1361-6595/ac4dde.

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Abstract We demonstrate an effective method for realization of robust, tailorable annular plasma photonic crystals (PPC) in dielectric barrier discharge with two water electrodes. Fast reconfiguration between triangular lattice, annular lattice, core-annular lattice and concentric-annular lattice has been achieved. An active control on the structure of plasma elements is realized by solely changing the applied voltage. The changes of photonic band gaps with reconfiguration of different annular PPCs have been studied both experimentally and numerically. The band gaps between 28.0–30.0 GHz for t

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21

Liu, Xiaojian, Shuo Liu, and Hao Lv. "A Dynamic Reconfiguration Scheme for Embedded System Based on Multi-core DSP." Journal of Physics: Conference Series 1802, no. 4 (2021): 042099. http://dx.doi.org/10.1088/1742-6596/1802/4/042099.

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22

Yalcin, Anil O., Bart de Nijs, Zhaochuan Fan, et al. "Core–shell reconfiguration through thermal annealing in FexO/CoFe2O4ordered 2D nanocrystal arrays." Nanotechnology 25, no. 5 (2014): 055601. http://dx.doi.org/10.1088/0957-4484/25/5/055601.

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23

Li, Zheng, and Shuibing He. "Run-time timing prediction for system reconfiguration on many-core embedded systems." Journal of Systems Architecture 95 (May 2019): 47–54. http://dx.doi.org/10.1016/j.sysarc.2019.03.004.

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24

Charles, Subodha, Alif Ahmed, Umit Y. Ogras, and Prabhat Mishra. "Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs." ACM Transactions on Design Automation of Electronic Systems 24, no. 6 (2019): 1–23. http://dx.doi.org/10.1145/3350422.

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25

Pourmohseni, Behnaz, Stefan Wildermann, Michael Glaß, and Jürgen Teich. "Hard real-time application mapping reconfiguration for NoC-based many-core systems." Real-Time Systems 55, no. 2 (2019): 433–69. http://dx.doi.org/10.1007/s11241-019-09326-y.

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26

Koukolová, Lucia. "Variability of Workplace Structures with SCARA Robot for Palletizing and Sorting Objects." Applied Mechanics and Materials 613 (August 2014): 299–303. http://dx.doi.org/10.4028/www.scientific.net/amm.613.299.

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This paper describes the design of palletizing workplace on a modular basis which can be reconfigured. First part of the paper is devoted to the definition of reconfigurable manufacturing systems and its core characteristics. Second part of the paper describes the workplace for palletization on a modular basis, its parts and possibilities of reconfiguration.

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Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumpi

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Cozma, Ana-Maria. "On the discursive construction of the multiple meanings of francophonie/francophone viewed through the prism of argumentative semantics." Kalbotyra 74 (September 15, 2021): 49–71. http://dx.doi.org/10.15388/kalbotyra.2021.74.3.

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This paper addresses the issue of polysemy, and more precisely of multiple meanings in the case of the words francophonie/francophone from the perspective of argumentative semantics. The aim of the paper is to examine the mechanisms that account for the multiple meanings of francophonie/francophone, i.e. the semantic and discursive mechanisms involved in the (re)construction of lexical meaning as the words occur in discourse. The data analysed in this paper consists of a set of discourse fragments about francophone identity, discourses that vary according to the speaker, the geographical locat

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Клименко, Оксана, Oksana Klimenko, Владимир Кулаков, et al. "Specifics of Implementing Project Management in State Authorities." Scientific Research and Development. Russian Journal of Project Management 7, no. 1 (2018): 42–48. http://dx.doi.org/10.12737/article_5ac5db250a3019.43276751.

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The article deals with the possibilities of implementing different management systems in state authorities along with the process of management system reconfiguration. The article defines core benefits and drawbacks of project management and operational management, the specifics of their application in state authorities. Moreover, it evaluates the importance of corporate culture adaptation to the implementation process.

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30

Kirchhoff, Michael, Philipp Kerling, Detlef Streitferdt, and Wolfgang Fengler. "A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor." International Journal of Reconfigurable Computing 2019 (September 22, 2019): 1–14. http://dx.doi.org/10.1155/2019/4723838.

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Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-speci

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Jaworski, Mateusz. "Солипсизм в романной поэтике Виктора Пелевина". Studia Rossica Posnaniensia, № 42 (19 червня 2018): 5–18. http://dx.doi.org/10.14746/strp.2017.42.1.

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The philosophical doctrine of solipsism plays an extremely significant role in Viktor Pelevin’s works as a core idea which undergoes the process of formal modifications. In this paper this process is referred to as “reconfiguration”. The article presents different representations of solipsism in Pelevin’s novels. The analysis is preceded by a brief introduction to the philosophical roots of the doctrine.

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MITTAL, SPARSH, and ZHAO ZHANG. "EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY." Journal of Circuits, Systems and Computers 23, no. 10 (2014): 1450147. http://dx.doi.org/10.1142/s0218126614501473.

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With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic profiling-based cache reconfiguration for saving cache leakage energy. EnCache uses a simple hardware component called profiling cache, which dynamically predicts energy efficiency of an application for 32 possible cache configurations. Using these estimates, system software rec

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Cardona, Luis Andres, and Carles Ferrer. "AC_ICAP: A Flexible High Speed ICAP Controller." International Journal of Reconfigurable Computing 2015 (2015): 1–15. http://dx.doi.org/10.1155/2015/314358.

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The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this

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., C. V. Borkute. "RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS." International Journal of Research in Engineering and Technology 02, no. 12 (2013): 151–54. http://dx.doi.org/10.15623/ijret.2013.0212027.

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Putnik, Goran, Diana Rodrigues, Cátia Alves, Paulo Ávila, Hélio Castro, and Maria Cruz-Cunha. "Analysing meta-organizations with embedded brokering services performance modelled as a call-centre for supporting dynamic reconfigurability of networked and virtual organizations." FME Transactions 48, no. 4 (2020): 725–32. http://dx.doi.org/10.5937/fme2004725p.

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Various companies choose to outsource the delivery of part of their services, so as not to deviate from its core business and improve the service level. This approach leads to a new type of organizations, so-called networked and virtual enterprises, where possibly a great number of companies work together without having direct contact but through a broker, as an intermediary, that streamlines the relationships between them. To enable high level efficiency, as well as some other functional requirements, the meta-organizations and brokering services are conceived as environments and services for

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Kamran, Arezoo, and Zainalabedin Navabi. "Self-Healing Many-Core Architecture: Analysis and Evaluation." VLSI Design 2016 (July 25, 2016): 1–17. http://dx.doi.org/10.1155/2016/9767139.

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More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-

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Seco, João, Ricardo Silva, and Margarida Piriquito. "Component J: A component-based programming language with dynamic reconfiguration." Computer Science and Information Systems 5, no. 2 (2008): 63–86. http://dx.doi.org/10.2298/csis0802063s.

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This paper describes an evolution of the ComponentJ programming language, a component-based Java-like programming language where composition is the chosen structuring mechanism. ComponentJ constructs allow for the high-level specification of component structures, which are the basis for the definition of compound objects. In this paper we present a new language design for ComponentJ which is more flexible and also allows the dynamic reconfiguration of objects. The manipulation of components and composition operations at the programming language level allows for the compile time verification, b

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Uddin, L. Q., K. S. Supekar, S. Ryali, and V. Menon. "Dynamic Reconfiguration of Structural and Functional Connectivity Across Core Neurocognitive Brain Networks with Development." Journal of Neuroscience 31, no. 50 (2011): 18578–89. http://dx.doi.org/10.1523/jneurosci.4465-11.2011.

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Troia, Sebastian, Rodolfo Alvizu, and Guido Maier. "Reinforcement Learning for Service Function Chain Reconfiguration in NFV-SDN Metro-Core Optical Networks." IEEE Access 7 (2019): 167944–57. http://dx.doi.org/10.1109/access.2019.2953498.

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KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structur

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Juárez-Vidales, Josué de Jesús, Jesús Pérez-Ortega, Jonathan Julio Lorea-Hernández, Felipe Méndez-Salcido, and Fernando Peña-Ortega. "Configuration and dynamics of dominant inspiratory multineuronal activity patterns during eupnea and gasping generation in vitro." Journal of Neurophysiology 125, no. 4 (2021): 1289–306. http://dx.doi.org/10.1152/jn.00563.2020.

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By means of multielectrode recordings of preBötC neurons, we evaluated their configuration in normoxia and hypoxia, finding that the preBötC exhibits a scale-free configuration with a rich-club phenomenon. preBötC neurons produce multineuronal activity patterns that are highly stable but change during hypoxia. The preBötC contains a coactivating core network that exhibit a distinctive pattern of coactivation at the beginning of inspirations. These results reveal some network basis of inspiratory rhythm generation and its reconfiguration during hypoxia.

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Ostroumov, Sergey, and Leonidas Tsiopoulos. "Formal Development of Hierarchical Agent-Based Monitoring Systems for Dynamically Reconfigurable NoC Platforms." International Journal of Embedded and Real-Time Communication Systems 3, no. 2 (2012): 40–72. http://dx.doi.org/10.4018/jertcs.2012040103.

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Sophisticated applications deployed on multi-core platforms require many resources as well as dynamic monitoring of the platform to provide efficiently and reliably the needed functionality. In this paper, the authors propose an approach to formal modelling with adequate tool support of an agent-based system whose function is to dynamically monitor the state of the multi-core platform and perform reconfiguration procedures under faults. For this purpose, the authors use the Event-B formalism which allows them to stepwise develop correct-by-construction specifications by mathematical proofs. Fu

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Xie, Chenkun. "Analysis of the impact of digital economy on the reconfiguration of manufacturing supply chain." Highlights in Business, Economics and Management 21 (December 12, 2023): 459–64. http://dx.doi.org/10.54097/hbem.v21i.14534.

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With the rapid development of science, and technology, the transformation and upgrading of the manufacturing supply chain in the era of the digital economy promotes the rapid development of the manufacturing industry., China's transformation is still in the embryonic stage so far. The transformation of the enterprise awareness is weak and lacking motivation. The digital core technology still needs to be researched and developed, so the digital transformation management mode still needs to be explored. However, the research of manufacturing supply chain reconstruction under the background of di

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Zhang, Yi, Chunjie Wang, Yuzhao Yao, Changsong Zhou, and Feiyan Chen. "Adaptive Reconfiguration of Intrinsic Community Structure in Children with 5-Year Abacus Training." Cerebral Cortex 31, no. 6 (2021): 3122–35. http://dx.doi.org/10.1093/cercor/bhab010.

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ABSTRACT Human learning can be understood as a network phenomenon, underpinned by the adaptive reconfiguration of modular organization. However, the plasticity of community structure (CS) in resting-state network induced by cognitive intervention has never been investigated. Here, we explored the individual difference of intrinsic CS between children with 5-year abacus-based mental calculation (AMC) training (35 subjects) and their peers without prior experience in AMC (31 subjects). Using permutation-based analysis between subjects in the two groups, we found the significant alteration of int

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KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel

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Jiexian, Huang, Yasir Khizar, Zain Anwar Ali, Raza Hasan, and Muhammad Salman Pathan. "On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers." PLOS ONE 18, no. 9 (2023): e0291429. http://dx.doi.org/10.1371/journal.pone.0291429.

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Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables—RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive co

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Yang, Zhangsheng, Hirotaka Yoshioka, and John R. McCarrey. "Sequence-specific promoter elements regulate temporal-specific changes in chromatin required for testis-specific activation of the Pgk2 gene." REPRODUCTION 146, no. 5 (2013): 501–16. http://dx.doi.org/10.1530/rep-13-0311.

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The phosphoglycerate kinase-2 (Pgk2) gene is regulated in a tissue-, cell type-, and developmental stage-specific manner during spermatogenesis and is required for normal sperm motility and fertility in mammals. Activation ofPgk2transcription is regulated by testis-specific demethylation of DNA and binding of testis-specific transcription factors to enhancer and core promoter elements. Here, we show that chromatin remodeling including reconfiguration of nucleosomes and changes in histone modifications is also associated with transcriptional activation of thePgk2gene during spermatogenesis. Dev

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Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architecture

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Wang, Ying, Xiaoqing Zhou, Fangbao Jiao, et al. "Constructing core@self-shell structured energetic nanomaterials by autologous surface molecular reconfiguration: The DATNBI case." Chemical Engineering Journal 471 (September 2023): 144415. http://dx.doi.org/10.1016/j.cej.2023.144415.

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Jang, Gunjoo. "Action Plans of Music Education for Enhancing Core Competencies." Korean Society of Music Education Technology 32 (July 16, 2017): 233–55. http://dx.doi.org/10.30832/jems.2017.32.233.

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The purpose of this study is to examine the action (implementation) plans in curriculum reorganization, teaching·learning methods and strategies, and education assessment in order to identify methods of improving music competencies. The result of this study is as follows. First, the curriculum reorganization included the process of setting goals and content configuration, actualizing and specifying music instruction in accordance with the achievement standards, planning teaching methods and materials, and assessment plans and tools. Second, in teaching·learning methods, contents of music

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