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Dissertations / Theses on the topic 'CoreIMS system'

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Published: 30 May 2022
Last updated: 31 July 2025

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1

Ledger, Dan. "Technically superior but unloved : a multi-faceted perspective on multi-core's failure to meet expectations in embedded systems." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/67632.

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Thesis (S.M. in Engineering and Management)--Massachusetts Institute of Technology, Engineering Systems Division, System Design and Management Program, 2011.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 103-106).<br>A growing number of embedded multi-core processors from several vendors now offer several technical advantages over single-core architectures. However, despite these advantages, adoption of multi-core processors in embedded systems has fallen short of expectations and not increased significantly in the last 3-4 years. There are several technic
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2

Jin, Liwu. "Hardware and software co-design in space compaction of cores-based digital circuit." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26670.

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Implementation of fault testing environment for embeded cores-based digital circuits is a challenging endeavor. The subject thesis aims developing techniques in design verification and test architecture utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embeded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design for testability. Specifically, applications of built-in self-test (BIST) methodology in testing embeded cores a
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3

Li, Junfeng. "Improved test efficiency in IP cores using ModelSim verification tool." Thesis, University of Ottawa (Canada), 2008. http://hdl.handle.net/10393/27999.

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The complexity of modern digital circuit has increased enormously particularly in the context of paradigm shift from system-on-board to designs embracing embedded cores-based System-on-Chips (SoCs). This increased complexity of circuits in turn results in a huge challenge of setting up their appropriate fault testing environments. Though lots of efforts have been taken to rapidly test the very large scale integrated (VLSI) circuit chips with very reasonable cost, with advances in technology, new frontiers also emerged. This thesis aims at developing a new technique to verify and test architect
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4

Hopkins, Andrew B. T. "Debug Support Strategy for System-an-Chips with Multiple Processor Cores." Thesis, University of Essex, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.486189.

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Increased integration has resulted in the creation of so called System-onChip (SoC) devices. They ~embed all the essential parts of an advanced computer into a single silicon chip in order to achieve compactness, reduced material cost, higher performance and lower power consumption. An adverse consequence of this integration is that the external interfaces once observed dUring debugging are now inaccessible within the chip, no longer aiding development. Debug support brings back this otherwise lost visibility by providing an observation window into the SoC, the heart of the overall system. Int
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5

Knutsson, Niklas. "An FPGA-based 3D Graphics System." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2822.

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<p>This report documents the work done by the author to design and implement a 3D graphics system on an FPGA (Field Programmable Gate Array). After a preamble with a background presentation to the project, a very brief introduction in computer graphics techniques and computer graphics theory is given. Then, the hardware available to the project, along with an analysis of general requirements is examined. The following chapter contains the proposed graphics system design for FPGA implementation. A broad approach to separate the design and the eventual implementation was used. Two 3D pipelines a
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6

Bartzoudis, Nikolaos. "Using embedded hardware monitor cores in critical computer systems." Thesis, Loughborough University, 2006. https://dspace.lboro.ac.uk/2134/33928.

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The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (s
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7

ARAUJO, Leonardo da Silva. "Estudo da sustentabilidade piscicultura no município de coremas PB." Universidade Federal de Campina Grande, 2015. http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/786.

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Submitted by Deyse Queiroz (deysequeirozz@hotmail.com) on 2018-05-23T14:25:29Z No. of bitstreams: 1 LEONARDO DA SILVA ARAÚJO - DISSERTAÇÃO PPGSA PROFISSIONAL 2015..pdf: 591080 bytes, checksum: dde6ef5013fd4cf765a80f6b6ba9c760 (MD5)<br>Made available in DSpace on 2018-05-23T14:25:29Z (GMT). No. of bitstreams: 1 LEONARDO DA SILVA ARAÚJO - DISSERTAÇÃO PPGSA PROFISSIONAL 2015..pdf: 591080 bytes, checksum: dde6ef5013fd4cf765a80f6b6ba9c760 (MD5) Previous issue date: 2015<br>A piscicultura é uma atividade desenvolvida no mundo há bastante tempo, na América do Sul o primeiro país a introduzir a pisc
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8

Jin, Chuan. "Test implementation of embedded cores-based sequential circuits using Verilog HDL under Altera MAX Plus II development environment." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26669.

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A Verilog HDL digital circuit fault simulator to detect permanent stuck-at logic faults for embedded cores-based synchronous sequential circuits is proposed in this thesis. The fault simulator can emulate a typical built-in self-testing (BIST) environment that utilizes a test pattern generator that sends its outputs to a module under test (MUT), with the resulting output from the MUT being fed into a test data analyzer. A fault is detected if the module response is different from that of the fault-free MUT. The fault simulator is suitable for testing synchronous sequential circuits described a
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9

Hunter, Jill Katherine. "Rapid design of discrete transform cores for multimedia VLSI systems." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301721.

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10

Nanjundappa, Mahesh. "Accelerating Hardware Simulation on Multi-cores." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/33002.

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Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes 2/3rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most
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11

Dahir, Sarmad Jamal. "Functional Self-Test of DSP cores in a SOC." Thesis, KTH, Microelectronics and Information Technology, IMIT, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4612.

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<p>The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals.</p><p>As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur d
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12

Garimella, Srinivas Murthy Stroud Charles E. "Built-in self test for regular structure embedded cores in system-on-chip." Auburn, Ala., 2005. http://repo.lib.auburn.edu/EtdRoot/2005/SPRING/Electrical_and_Computer_Engineering/Thesis/GARIMELLA_SRINIVAS_32.pdf.

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13

Blazevic, Denis Ivan, and Magnus Jansson. "Improving the flexibility of DPDK Service Cores." Thesis, Linköpings universitet, Interaktiva och kognitiva system, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-157631.

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Data Plane Development Kit is a highly used library for creating network applications that can be run on all hardware. Data Plane Development Kit has a component called Service Cores, which allows the main applications to create services that will run independently. These services are manually mapped to specific CPU cores, and are scheduled in a round-robin method. Because of the manual mapping, and the scheduling, the different load for each service can impact the start time for each service. By having services not run when supposed to, the throughput will degrade. In this thesis, we investig
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14

Medina, Roberto. "Deployment of mixed criticality and data driven systems on multi-cores architectures." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT004/document.

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De nos jours, la conception de systèmes critiques va de plus en plus vers l’intégration de différents composants système sur une unique plate-forme de calcul. Les systèmes à criticité mixte permettent aux composants critiques ayant un degré élevé de confiance (c.-à-d. une faible probabilité de défaillance) de partager des ressources de calcul avec des composants moins critiques sans nécessiter des mécanismes d’isolation logicielle.Traditionnellement, les systèmes critiques sont conçus à l’aide de modèles de calcul comme les graphes data-flow et l’ordonnancement temps-réel pour fournir un compo
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15

Medina, Roberto. "Deployment of mixed criticality and data driven systems on multi-cores architectures." Electronic Thesis or Diss., Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT004.

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De nos jours, la conception de systèmes critiques va de plus en plus vers l’intégration de différents composants système sur une unique plate-forme de calcul. Les systèmes à criticité mixte permettent aux composants critiques ayant un degré élevé de confiance (c.-à-d. une faible probabilité de défaillance) de partager des ressources de calcul avec des composants moins critiques sans nécessiter des mécanismes d’isolation logicielle.Traditionnellement, les systèmes critiques sont conçus à l’aide de modèles de calcul comme les graphes data-flow et l’ordonnancement temps-réel pour fournir un compo
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16

Jangid, Anuradha. "Verifying IP-Cores by Mapping Gate to RTL-Level Designs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878.

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17

Jakab, Loránd. "Use of locator/identifier separation to improve the future internet routing system." Doctoral thesis, Universitat Politècnica de Catalunya, 2011. http://hdl.handle.net/10803/80946.

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The Internet evolved from its early days of being a small research network to become a critical infrastructure many organizations and individuals rely on. One dimension of this evolution is the continuous growth of the number of participants in the network, far beyond what the initial designers had in mind. While it does work today, it is widely believed that the current design of the global routing system cannot scale to accommodate future challenges. In 2006 an Internet Architecture Board (IAB) workshop was held to develop a shared understanding of the Internet routing system scalability
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18

Socci, Dario. "Scheduling of certifiable mixed-criticality systems." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM025/document.

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Les systèmes temps-réels modernes ont tendance à obtenir la criticité mixte, dans le sens où ils intègrent sur une même plateforme de calcul plusieurs applications avec différents niveaux de criticités. D'un côté, cette intégration permet de réduire le coût, le poids et la consommation d'énergie. Ces exigences sont importantes pour des systèmes modernes comme par exemple les drones (UAV). De l'autre, elle conduit à des complications majeures lors de leur conception. Ces systèmes doivent être certifiés en prenant en compte ces différents niveaux de criticités. L'ordonnancement temps réel des sy
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19

van, Blarcum Ronald A. "Anthropogenic Impacts as Revealed from Sediment Cores from Punderson Lake Ohio." Cleveland State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=csu1448536586.

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20

Östlund, Johan. "Language Constructs for Safe Parallel Programming on Multi-Cores." Doctoral thesis, Uppsala universitet, Datalogi, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-266795.

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The last decade has seen the transition from single-core processors to multi-cores and many-cores. This move has by and large shifted the responsibility from chip manufacturers to programmers to keep up with ever-increasing expectations on performance. In the single-core era, improvements in hardware capacity could immediately be leveraged by an application: faster machine - faster program. In the age of the multi-cores, this is no longer the case. Programs must be written in specific ways to utilize available parallel hardware resources. Programming language support for concurrent and paralle
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21

Stewart, Andrew John. "Planetary cores : effect and behaviour of minor elements on the Fe-S system to 40 GPa /." Zürich : ETH, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16815.

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22

Baskaran, Muthu Manikandan. "Compile-time and Run-time Optimizations for Enhancing Locality and Parallelism on Multi-core and Many-core Systems." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253557044.

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23

Karaoui, Mohamed Lamine. "Système de fichiers scalable pour architectures many-cores à faible empreinte énergétique." Thesis, Paris 6, 2016. http://www.theses.fr/2016PA066186/document.

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Cette thèse porte sur l'étude des problèmes posés par l'implémentation d'un système de fichiers passant à l'échelle, pour un noyau de type UNIX sur une architecture manycore NUMA à cohérence de cache matérielle et à faible empreinte énergétique. Pour cette étude, nous prenons comme référence l'architecture manycore généraliste TSAR et le noyau de type UNIX ALMOS.L'architecture manycore visée pose trois problèmes pour lesquels nous apportons des réponses après avoir décrit les solutions existantes. L'un de ces problèmes est spécifique à l'architecture TSAR tandis que les deux autres sont généra
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24

Pagna, Disso Jules F. "A novel intrusion detection system (IDS) architecture. Attack detection based on snort for multistage attack scenarios in a multi-cores environment." Thesis, University of Bradford, 2010. http://hdl.handle.net/10454/5248.

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Recent research has indicated that although security systems are developing, illegal intrusion to computers is on the rise. The research conducted here illustrates that improving intrusion detection and prevention methods is fundamental for improving the overall security of systems. This research includes the design of a novel Intrusion Detection System (IDS) which identifies four levels of visibility of attacks. Two major areas of security concern were identified: speed and volume of attacks; and complexity of multistage attacks. Hence, the Multistage Intrusion Detection and Prevention
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25

Pagna, Disso Jules Ferdinand. "A novel intrusion detection system (IDS) architecture : attack detection based on snort for multistage attack scenarios in a multi-cores environment." Thesis, University of Bradford, 2010. http://hdl.handle.net/10454/5248.

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Recent research has indicated that although security systems are developing, illegal intrusion to computers is on the rise. The research conducted here illustrates that improving intrusion detection and prevention methods is fundamental for improving the overall security of systems. This research includes the design of a novel Intrusion Detection System (IDS) which identifies four levels of visibility of attacks. Two major areas of security concern were identified: speed and volume of attacks; and complexity of multistage attacks. Hence, the Multistage Intrusion Detection and Prevention System
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26

Leung, Lap-Fai. "Designing high-performance and low-energy real-time embedded systems based on single-core and multi-cores structures /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LEUNG.

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27

Almaless, Ghassan. "Operating System Design and Implementation for Single-Chip cc-NUMA Many-Core." Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066587/document.

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De nos jours, des processeurs à mémoire partagée cohérente ayant jusqu’à 100 coresintégrés sur la même puce sont une réalité et des processeurs many-cores ayant plusieurs centaines, voire, un millier de cores sont à prévoir prochainement.Dans ces architectures, la question de la localité du trafic lié aux miss decaches L1 (data, instruction et TLB) est primordiale à la fois pour passer àl’échelle et pour réduire la consommation électrique (énergie consommée par bittransféré). Notre thèse est que : (i) la gestion de la localité des accès mémoiredoit être prise en compte au niveau du noyau du sy
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28

Harris, Jonathan McKinley Stroud Charles E. "Built-in self-test configurations for field programmable gate array cores in systems-on-chip." Auburn, Ala., 2004. http://repo.lib.auburn.edu/EtdRoot/2004/FALL/Electrical_and_Computer_Engineering/Thesis/harri34_43_msthesisjharrisF04.pdf.

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29

Cawley, Jon C. "A Re-Evaluation of Mountain Lake, Giles County, Virginia: Lake Origins, History and Environmental Systems." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/29869.

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This project included the following goals: 1. To review and assess the geomorphology and lake morphometry of Mountain Lake, Giles County, Virginia with regard to its age and origin. This included production of an updated bathymetric map of Mountain Lake using Sonar imaging of the lake bottom. 2. To evaluate present trophic conditions in the lake waters. This analysis included the first-reported nutrient conditions for input streams to the lake and rainwater. 3. To collect representative "modern" bottom sediment samples and to analyze these sediment samples for sedimentological characteristics,
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30

Karaoui, Mohamed Lamine. "Système de fichiers scalable pour architectures many-cores à faible empreinte énergétique." Electronic Thesis or Diss., Paris 6, 2016. http://www.theses.fr/2016PA066186.

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Cette thèse porte sur l'étude des problèmes posés par l'implémentation d'un système de fichiers passant à l'échelle, pour un noyau de type UNIX sur une architecture manycore NUMA à cohérence de cache matérielle et à faible empreinte énergétique. Pour cette étude, nous prenons comme référence l'architecture manycore généraliste TSAR et le noyau de type UNIX ALMOS.L'architecture manycore visée pose trois problèmes pour lesquels nous apportons des réponses après avoir décrit les solutions existantes. L'un de ces problèmes est spécifique à l'architecture TSAR tandis que les deux autres sont généra
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31

Kayande, Sarang. "A systems approach to reduce processing and materials induced warpage in large single ply PCB cores." Diss., Online access via UMI:, 2005.

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32

Rambo, Eberle Andrey Verfasser], and Rolf [Akademischer Betreuer] [Ernst. "Fault-Tolerant Many-Cores for Mixed-Critical Real-Time Systems / Eberle Andrey Rambo ; Betreuer: Rolf Ernst." Braunschweig : Technische Universität Braunschweig, 2019. http://d-nb.info/1179910044/34.

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33

Londono, Arcila Lida Patricia. "The use of hepatitis B cores for peptide presentation : delivery to the mouse immune system using live attenuated salmonella." Thesis, Imperial College London, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.297205.

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34

HIROMOTO, MARIA Y. K. "PSINCO-um programa para calculo da distribuicao de potencia e supervisao do nucleo de reatores nucleares, utilizando sinais de detetores tipo 'SPD'." reponame:Repositório Institucional do IPEN, 1998. http://repositorio.ipen.br:8080/xmlui/handle/123456789/10706.

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CARVALHO, LUIZ S. "Frequencia de danos no nucleo por blecaute em reator nuclear de concepcao avancada." reponame:Repositório Institucional do IPEN, 2004. http://repositorio.ipen.br:8080/xmlui/handle/123456789/11147.

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36

Verani, Cláudio Nazari. "Rational synthesis and characterization of paramagnetic heteropolynuclear systems containing [MA - MB - MC], [MA - MB] and [M₁ - ₂ (*R)₁ - ₂ - ₃] cores /." Mülheim an der Ruhr : Max-Planck-Institut für Strahlenchemie, 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=959794514.

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37

Almaless, Ghassan. "Operating System Design and Implementation for Single-Chip cc-NUMA Many-Core." Electronic Thesis or Diss., Paris 6, 2014. http://www.theses.fr/2014PA066587.

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De nos jours, des processeurs à mémoire partagée cohérente ayant jusqu’à 100 coresintégrés sur la même puce sont une réalité et des processeurs many-cores ayant plusieurs centaines, voire, un millier de cores sont à prévoir prochainement.Dans ces architectures, la question de la localité du trafic lié aux miss decaches L1 (data, instruction et TLB) est primordiale à la fois pour passer àl’échelle et pour réduire la consommation électrique (énergie consommée par bittransféré). Notre thèse est que : (i) la gestion de la localité des accès mémoiredoit être prise en compte au niveau du noyau du sy
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38

Gupta, Vishakha. "Coordinated system level resource management for heterogeneous many-core platforms." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42750.

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A challenge posed by future computer architectures is the efficient exploitation of their many and sometimes heterogeneous computational cores. This challenge is exacerbated by the multiple facilities for data movement and sharing across cores resident on such platforms. To answer the question of how systems software should treat heterogeneous resources, this dissertation describes an approach that (1) creates a common manageable pool for all the resources present in the platform, and then (2) provides virtual machines (VMs) with multiple `personalities', flexibly mapped to and efficientl
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39

TATENGUEM, FANKEM Herve'. "CROSS-LAYER DESIGN, OPTIMIZATION AND PROTOTYPING OF NoCs FOR THE NEXT GENERATION OF HOMOGENEOUS MANY-CORE SYSTEMS." Doctoral thesis, Università degli studi di Ferrara, 2014. http://hdl.handle.net/11392/2389382.

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This thesis provides a whole set of design methods to enable and manage the runtime heterogeneity of features-rich industry-ready Tile-Based Networkon- Chips at different abstraction layers (Architecture Design, Network Assembling, Testing of NoC, Runtime Operation). The key idea is to maintain the functionalities of the original layers, and to improve the performance of architectures by allowing, joint optimization and layer coordinations. In general purpose systems, we address the microarchitectural challenges by codesigning and co-optimizing feature-rich architectures. In application
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40

Cota, Erika Fernandes. "Reuse-based test planning for core-based systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/4180.

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O projeto de sistemas eletrônicos atuais segue o paradigma do reuso de componentes de hardware. Este paradigma reduz a complexidade do projeto de um chip, mas cria novos desafios para o projetista do sistema em relação ao teste do produto final. O acesso aos núcleos profundamente embutidos no sistema, a integração dos diversos métodos de teste e a otimização dos diversos fatores de custo do sistema são alguns dos problemas que precisam ser resolvidos durante o planejamento do teste de produção do novo circuito. Neste contexto, esta tese propõe duas abordagens para o planejamento de teste de si
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41

Rouxel, Benjamin. "Minimising shared resource contention when scheduling real-time applications on multi-core architectures." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S092/document.

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Les architectures multi-cœurs utilisant des mémoire bloc-notes sont des architectures attrayantes pour l'exécution des applications embarquées temps-réel, car elles offrent une grande capacité de calcul. Cependant, les systèmes temps-réel nécessitent de satisfaire des contraintes temporelles, ce qui peut être compliqué sur ce type d'architectures à cause notamment des ressources matérielles physiquement partagées entre les cœurs. Plus précisément, les scénarios de pire cas de partage du bus de communication entre les cœurs et la mémoire externe sont trop pessimistes. Cette the
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42

Abdallah, Laure. "Worst-case delay analysis of core-to-IO flows over many-cores architectures." Phd thesis, Toulouse, INPT, 2017. http://oatao.univ-toulouse.fr/17836/1/abdallah_2.pdf.

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Many-core architectures are more promising hardware to design real-time systems than multi-core systems as they should enable an easier mastered integration of a higher number of applications, potentially of different level of criticalities. In embedded real-time systems, these architectures will be integrated within backbone Ethernet networks, as they mostly provide Ethernet controllers as Input/Output(I/O) interfaces. Thus, a number of applications of different level of criticalities could be allocated on the Network-on-Chip (NoC) and required to communicate with sensors and actuators. Howev
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43

Blin, Antoine. "Vers une utilisation efficace des processeurs multi-coeurs dans des systèmes embarqués à criticités multiples." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066114/document.

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Les systèmes embarqués dans les véhicules comportent un mélange d’applications temps réel et « best effort » déployées, pour des raisons d’isolation, sur des calculateurs séparés. L’ajout de nouvelles fonctionnalités dans les véhicules se traduit par un accroissement du nombre de calculateurs et ainsi par une augmentation des coûts, de la consommation électrique et de la dissipation thermique.L’émergence de nouvelles plate-formes multi-cœurs à bas coûts permet d’envisager le déploiement d’une nouvelle architecture dite « virtualisée » pour exécuter en parallèle sur un même calculateur les deux
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44

Kajackaitė, Monika. "Vilniaus miesto Neries slėnio urbanistinės plėtros ir apsaugos principai: Žvėryno šiaurinės dalies atvejis." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2011. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110627_140355-28090.

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Darbo idėja kilo, stebint architektūrinio urbanistinio komplekso dešiniajame Neries krante plėtrą. Šis kompleksas yra realizuotas vadinamosios aštuntojo dešimtmečio „architektūrinių kalvų“ idėjos fragmentas. Nepaisant skeptiško ar net priešiško paveldosaugininkų požiūrio į šį kompleksą, akivaizdu, kad tai yra sėkminga didelio užmojo urbanistinės koncepcijos realizacija. Kita vertus, rezultatas seniai neatitinka pirminės idėjos, nes užima kelis kartus didesnį plotą miesto topografijoje, t.y. išsidėstęs abipus Konstitucijos prospekto, be to, realizuota iš principo kitokia aukštybinių akcentų sis
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45

Plyaskin, Roman [Verfasser], Andreas [Akademischer Betreuer] Herkersdorf, and Wolfgang [Akademischer Betreuer] Rosenstiel. "Fast and accurate performance simulation of out-of-order processing cores in embedded systems / Roman Plyaskin. Gutachter: Wolfgang Rosenstiel ; Andreas Herkersdorf. Betreuer: Andreas Herkersdorf." München : Universitätsbibliothek der TU München, 2014. http://d-nb.info/1054753393/34.

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46

Holmberg, Pär. "Modelling the transient response of windings, laminated steel cores and electromagnetic power devices by means of lumped circuits : with special reference to windings with a coaxial insulation system /." Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2000. http://publications.uu.se/theses/91-554-4877-1/.

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47

SOUZA, ROSE M. G. do P. "Determinação do fator de pico de potência utilizando barras de controle, detectores ex-core e redes neurais." reponame:Repositório Institucional do IPEN, 2005. http://repositorio.ipen.br:8080/xmlui/handle/123456789/11296.

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Made available in DSpace on 2014-10-09T12:50:25Z (GMT). No. of bitstreams: 0<br>Made available in DSpace on 2014-10-09T13:58:44Z (GMT). No. of bitstreams: 1 10895.pdf: 9491478 bytes, checksum: a17089904688d31b0c3d8e9056a263b2 (MD5)<br>Tese (Doutoramento)<br>IPEN/T<br>Instituto de Pesquisas Energeticas e Nucleares - IPEN/CNEN-SP
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48

Blin, Antoine. "Vers une utilisation efficace des processeurs multi-coeurs dans des systèmes embarqués à criticités multiples." Electronic Thesis or Diss., Paris 6, 2017. http://www.theses.fr/2017PA066114.

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Les systèmes embarqués dans les véhicules comportent un mélange d’applications temps réel et « best effort » déployées, pour des raisons d’isolation, sur des calculateurs séparés. L’ajout de nouvelles fonctionnalités dans les véhicules se traduit par un accroissement du nombre de calculateurs et ainsi par une augmentation des coûts, de la consommation électrique et de la dissipation thermique.L’émergence de nouvelles plate-formes multi-cœurs à bas coûts permet d’envisager le déploiement d’une nouvelle architecture dite « virtualisée » pour exécuter en parallèle sur un même calculateur les deux
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49

Holmberg, Pär. "Modelling the transient response of windings, laminated steel coresand electromagnetic power devices by means of lumped circuits : With special reference to windings with a coaxial insulation system." Doctoral thesis, Uppsala University, Department of High Voltage Research, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-548.

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<p>Electromagnetic transients impinging on electromagnetic power devices - such as electric machines, transformers and reactors - can stress the design severely. Thus the magnitudes of the transients are often decisive for the design of the devices. Further, the operation of a device can be transient in itself. This is the case for the explosive magnetic flux compression generator (EMG) and a ferromagnetic actuator. </p><p>Models are presented that are mainly intended for transients in the millisecond range and faster. Hence, eddy currents and the related skin and proximity effect become signi
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50

Venkataramani, Guru Prasadh V. "Low-cost and efficient architectural support for correctness and performance debugging." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31747.

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Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2010.<br>Committee Chair: Prvulovic, Milos; Committee Member: Hughes, Christopher J.; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin S.; Committee Member: Loh, Gabriel H. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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