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Vajmar, Jan. "Jeřáb mostový dvounosníkový." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2016. http://www.nusl.cz/ntk/nusl-241155.
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This master’s thesis describes the design of two-girder overhead crane. At the beginning of the work are designed sectional characteristics of the girder and the crossbeam. Furthermore, they are calculated loads applied during crane operation. Following the determination of the static load and fatigue strength. All calculations are solved with respect to relevant standards relating to overhead cranes. The work also includes analysis of purchased components, which are geared motors, bumpers and drive (no drive) wheels.
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Vošček, Martin. "Silniční a tramvajový most." Master's thesis, Vysoké učení technické v Brně. Fakulta stavební, 2017. http://www.nusl.cz/ntk/nusl-265573.
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The subject of this Diploma Thesis is to develop different alternatives of the road and tram bridge. It is a river bridge with the length of 52,5 m. There are compared two proposals, while in the first proposal it is an arch bridge with the tension bars. The second proposal which is also finalized as the winning proposal is the truss structure. Both proposals have composite deck. The structure is designed from steel S355 and concrete C35/45. The load bearing structure is designed in accordance with applicable technical standards.
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Chroust, Martin. "Mostový jeřáb jednonosníkový." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2018. http://www.nusl.cz/ntk/nusl-377474.
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The focus of this thesis is the construction of a single girder overhead crane. The goal is to render a crane construction according to preset parameters. The parameters include a lifting power of 8,000 kg, a 10,000 mm reach, a 2,400 mm wheelbase and a stroke of 8,000 mm. The thesis includes brief theoretical research focused on overhead cranes, their various types and description of their main components. Brief description of chosen parameters for the construction itself follows. The description of chosen parameters includes calculations of strain acting during operation, technical and stability parameters, essential for the construction. All calculations were made with regard to valid Czech technical standards and specialized literature which focuses on the construction of cranes and their parts. Finally, the thesis is extended by the required technical drawings.
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Žák, Petr. "Konstrukce CNC frézky." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2015. http://www.nusl.cz/ntk/nusl-231996.
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The diploma thesis includes design of vertical CNC milling machine. It also includes research in the field of CNC milling machines on the world market, which is carried out to select the appropriate machine parameters and the structural configuration of the machine. Another part of the thesis deals with the selection of suitable components, design calculations, manufacturing drawings and the 3D model showing the final design solution of proposed machine.
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Stanec, Stanislav. "Jeřáb mostový jednonosníkový." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2017. http://www.nusl.cz/ntk/nusl-318639.
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This diploma thesis deals with constructional design and a calculation of one-girder bridge crane with the requested primary parametres: lifting capacity 10 000 kg, span 12 000 mm, wheel base 2 500 mm, travel height 7 000 mm. In diploma thesis, there is executed analysis of constructional designs of box girders, drawn up technical report with the analysis of the choice of the construction with important technical and physical calculations. Calculations were executed according to valid Czech state norms and literature. Drawing documentation is enclosed to this thesis.
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Mynaříková, Alice. "Dřevěná lávka nad vlčím výběhem." Master's thesis, Vysoké učení technické v Brně. Fakulta stavební, 2016. http://www.nusl.cz/ntk/nusl-240227.
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The subject of this diploma thesis is the construction of a timber foot bridge over the wolf run in the Šumava National Park. The total length of the bridge is 240 m with two ground plan bends. The foot bridge includes three viewing decks, two of which are covered with shed roofs. The foot bridge is divided into 16 segments. Each segment is 15 m long with a width of 2.2 meters. The ground plan dimensions of the viewing decks are approximately 15x7 and 15x11 m. As the main structural material has been chosen glued laminated timber of the strength class GL28h, other elements are made of solid timber of the strength class C24. The thesis includes an introductory document, options analysis, technical report, static analysis, bill of material and drawings.
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Loucif, Samia. "Performance evaluation of Distributed Crossbar Switch Hypermesh." Thesis, University of Glasgow, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301360.
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Cortese, Simone. "Selector devices/architectures for ReRAM crossbar arrays." Thesis, University of Southampton, 2017. https://eprints.soton.ac.uk/418465/.
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Resistive Random Access Memories (ReRAMs) are amongst the most promising next generation memory technologies, due to their small feature size, low power consumption and capacity to be integrated in 3D ehen arranged in crossbar array. ReRAMs harvest the potential of the resistive switching phenomenon that allows to reversibly change their internal resistive state, from High to Low. This aspect, however, is also a problem when ReRAM cells are tesserated in crossbar array configuration: elements that are programmed in their low resistive state can create low resistance sneak paths in the array fabric making the readout operations strenuous. This challenge is usually mitigated by the use of selector devices. A selector must be able to suppress the currents owing in the sneak paths and, at the same time, allow for ReRAM reliable operations. In this work, the sneak current problem is introduced and defined. Several solutions that have been studied in literature are presented and discussed, creating a solid background for the development of this work. Upon this strong basis, different selector devices technologies were developed. Ni/TiO2/Ni selector devices were first designed, studied and benchmarked against other technologies showing improved performances in term of Voltage Margin without any adverse effect on the maximum current supplied. As this device stack has been designed to have a similar metal-insulator-metal architecture to ReRAM devices, the two were monolithically integrated and characterized. The possibility to exploit volatile resistive switching was also introduced and discussed thoroughly, starting from a TiO2/NiO stack exhibiting a promising threshold behaviour for selectorsoperations, fostering iterests of the community on this approach. The limitations of this approach were studied via SPICE simulations, setting the framework and requirements for their implementation in crossbars: through this ongoing work, it was realised that the selector technologies should not be evaluated in isolation from ReRAM, which has led to contributions towards forming-free ReRAM devices. This research stream employed a TiO2/AlOy bi-layer stack devices able to perform resisting switching with a 2-orders of magnitude ON/OFF ratio and low cycle-to-cycle variability without requiring electroforming: this behaviour is presented and discussed. Herein, overall this work has oered contributions towards reliable ReRAM/selector technologies operations for crossbar arrays in terms of both selector technology, improving existing approach and exploring new ones, and ReRAMs, providing the community with a promising path towards forming free operations.
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Alayan, Mouhamad. "Étude des mémoires résistives (RRAM) à base d’HfO2 : caractérisation et modélisation de la fiabilité des cellules mémoire et des nouveaux dispositifs d'accès (Sélecteurs)." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT032/document.
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L'écart de vitesse entre le processeur et la mémoire vive est devenu un point faible pour les performances des systèmes. En raison de ces limitations, de nombreuses mémoires émergentes ont été proposées comme solutions alternatives à ces problèmes existant dans la hiérarchie mémoire. Les mémoires résistives (RRAM) sont considérées comme des candidats pour la « storage class memory » (SCM), les mémoires non volatiles embarquées (eNVM), et les systèmes neuromorphique. Cependant, les problèmes de fiabilité tels que la rétention de données sont encore en cours d'amélioration. De plus, pour obtenir des matrices mémoires de grande densité, la RRAM a besoin des sélecteurs qui seront intégrer en série avec elle dans une architecture un-sélecteur une-résistance (1S1R). Le sélecteur est nécessaire avec le point mémoire pour éliminer les problèmes des courants de fuite, qui gênent le bon fonctionnement de la matrice mémoire dans des architectures crossbar et verticales 3D.Dans cette thèse, notre objectif principal est de traiter les défis ci-dessus. Notre travail peut être divisé en deux parties principales : i) l'étude de la fiabilité des cellules RRAM basées sur HfO2 et ii) la caractérisation des opérations de base et des performances des cellules RRAM basées sur HfO2 et qui sont co-intégrées avec deux types différents des sélecteurs. Pour la partie fiabilité, nous avons étudié les effets du dopage aluminium (Al) sur la rétention de données des cellules RRAM à base de HfO2. Des dispositifs à simple et double couche avec différentes concentrations d'aluminium ont été fabriqués et testés. A partir des comportements électriques macroscopiques, comme la dégradation du diélectrique en fonction du temps (TDDB) et l’opération de forming avec des rampes de tension, on a extrait des propriétés microscopiques des matériaux tels que l'énergie d'activation nécessaire pour la rupture d’une liaison chimique à champ nul et le moment dipolaire des liaisons dans les matériaux testés. En utilisant ces paramètres microscopiques nous avons effectué tout au long de ce travail des simulations physiques pour comprendre les dynamiques de l’opération de forming ainsi que les mécanismes physiques impliqués pendant les opérations du dispositif mémoire. Deuxièmement, nous avons étudié l'immunité aux rayonnements de la RRAM à base de HfO2 pour les applications spatiales. Nos dispositifs RRAM ont été exposés à une énergie de 266 MeV d'ions lourds d'iode. Des analyses pré- et post-exposition ont été effectuées sur les états de la mémoire et les tensions de programmation pour étudier les effets de l'irradiation sur les caractéristiques du dispositif mémoire.Dans la partie des dispositifs d’accès, nous avons évalué deux types différents des sélecteurs. Une forte non-linéarité dans les caractéristiques courant / tension est obligatoire pour effectuer une lecture précise et une écriture à faible consommation. Dans le premier dispositif étudié, la sélectivité est introduite en ajoutant une couche d'oxyde dans l’empilement mémoire et qui agit comme une barrière tunnel. Le principal avantage de cette méthode est la facilité d’intégration de la barrière tunnel, par contre elle souffre d'une faible sélectivité (~ 10) et d'un faible courant de programmation qui dégrade la rétention de données. Deuxièmement, on a co-intégré avec l’RRAM un sélecteur OTS et le dispositif 1S1R a été entièrement caractérisé. Le sélecteur OTS offre une plus grande sélectivité par rapport à la barrière tunnel avec les possibilités d'augmenter fortement cette sélectivité par l'ingénierie des matériaux chalcogénures. Plus de 106 cycles de lecture ont été obtenu pour les dispositifs 1S1R en utilisant une stratégie de lecture innovante que nous avons suggérée pour éviter les lectures perturbatrices et réduire la consommation d'énergieThe performance gaps in nowadays memory hierarchy on the first hand between processor and main memory, on the other hand between main memory and storage have become a bottleneck for system performances. Due to these limitations, many emerging memories have been proposed as alternative solutions to fill out such concerns. The emerging non-volatile resistive random-access memories (RRAM) are considered as strong candidates for storage class memory (SCM), embedded nonvolatile memories (eNVM), enhanced solid-state disks, and neuromorphic computing. However, reliability challenges such as RRAM thermal stability and resistance variability are still under improvement processes. In addition, to achieve high integration densities the RRAM needs two terminal selector devices in one-selector one-resistor (1S1R) serial cell. The BEOL selector device enables suppression of the parasitic leakage paths, which hinder memory array operation in crossbar and vertical 3D architectures.In this PhD, our main focus is to address and treat the above challenges. Here, the work can be divided into two main parts: i) the investigation of the reliability of HfO2 based RRAM cells and ii) the characterization of the basis memory operations and performances of HfO2 based RRAM cells co-integrated with two different back end of line (BEOL) selector technologies.For the reliability part, we have investigated the effects of aluminum (Al) doping on data retention of HfO2 based RRAM cells. Single and double layer devices with different aluminum concentration were fabricated and tested. From macroscopic electrical characteristics, like time dependent dielectric breakdown (TDDB) and ramped voltage forming, microscopic properties of the materials such as the activation energy to break a bond at zero field and the dipole moment of the bond were extracted. These parameters have been used to shed new light on the mechanisms governing the forming process by means of device level simulations. Second, we have addressed the radiation immunity of HfO2 based RRAM for possible space applications as well. Our RRAM devices were exposed to 266 MeV Iodine heavy ions energy. Pre- and post-exposure analysis were carried out on the memory states and the programming voltages to study the effects of the irradiation on the memory characteristics. Throughout this work, we have performed physics based simulations to understand the dynamics of the forming process as well as the physical mechanisms involved during the memory operations.For the access devices part, we have evaluated two different types of selectors. For accurate reading and low power writing a strong selectivity in the current/voltage characteristics is required. In the first studied device, the selectivity is introduced by adding an oxide tunnel barrier. The main advantage of this strategy is that it is easy to integrate, however it suffers of low selectivity (~10) and low programming current. Second, an OTS based selector co-integrated with HfO2 based RRAM was fully characterized. OTS selector provides higher selectivity compared to the oxide tunnel barrier with the possibilities to strongly increase this selectivity by material engineering. Over 106 read cycles have been achieved on our 1S1R devices using an innovative read strategy that we have suggested to prevent disruptive read and to reduce the power consumption
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Mhamdi, Lotfi. "High-performance scheduling algorithms for buffered crossbar switches /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?COMP%202002%20MHAMDI.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.Includes bibliographical references (leaves 116-123). Also available in electronic version. Access restricted to campus users.
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Wu, Ting. "Design of terabits/s CMOS crossbar switch chip /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WU.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.
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Venkateswaran, Sriram. "Functional testing of faults in asynchronous crossbar architecture." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Sriram_09007dcc805dd758.pdf.
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Thesis (M.S.)--Missouri University of Science and Technology, 2009.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed January 22, 2009) Includes bibliographical references.
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Bonam, Ravi Kiran. "Asynchronous nanowire crossbar architecture for manufacturability, modularity and robustness." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2008. http://scholarsmine.mst.edu/thesis/pdf/Bonam_09007dcc804d89fd.pdf.
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Thesis (M.S.)--Missouri University of Science and Technology, 2008.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed April 28, 2008) Includes bibliographical references.
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Zhang, Yixuan. "High-Performance Crossbar Designs for Network-on-Chips (NoCs)." Ohio University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1282056856.
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Uppala, Roshni. "Simulating Large Scale Memristor Based Crossbar for Neuromorphic Applications." University of Dayton / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1429296073.
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Velasquez, Alvaro. "Computation of Boolean Formulas Using Sneak Paths in Crossbar Computing." Honors in the Major Thesis, University of Central Florida, 2014. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/1649.
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Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory and computation units. The computation of Boolean formulas using memristor circuits has been a subject of several recent investigations. Crossbar computing, in general, has also been a topic of active interest, but sneak paths have posed a hurdle in the design of pervasive general-purpose crossbar computing paradigms. In this paper, we demonstrate that sneak paths in nano-crossbar computing can be exploited to design a Boolean-formula evaluation strategy. We demonstrate our approach on a simple Boolean formula and a 1-bit addition circuit. We also conjecture that our nano-crossbar design will be an effective approach for synthesizing high-performance customized arithmetic and logic circuits.B.S.
Bachelors
Electrical Engineering and Computer Science
Engineering and Computer Science
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Picon, Andoni Irizar. "A self-routing asynchronous crossbar switch for multiprocessors based micropipelines." Thesis, University of Sheffield, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.287348.
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Shin, Eung Seo. "Automated Generation of Round-robin Arbitration and Crossbar Switch Logic." Diss., Available online, Georgia Institute of Technology, (2003), 2003. http://etd.gatech.edu/theses/available/etd-11232003-150424/.
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Liu, Jing. "Stable and scalable arbitration algorithms for crossbar-based switches/routers /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?COMP%202003%20LIUJ.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 92-96). Also available in electronic version. Access restricted to campus users.
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Charny, Anna. "Providing QoS guarantees in input buffered crossbar switches with speedup." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9628.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 103-105).
This dissertation investigates a number of issues related to providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of providing delay guarantees comparable to those known for output-buffered switch architecture. Several algorithms which ensure different delay guarantees with different values of speedup are presented and analyzed.
by Anna Charny.
Ph.D.
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Lipener, Patrícia Almeida. "Considerações sobre variações livres em pontes." Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/3/3144/tde-15012018-145233/.
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Pontes são estruturas denominadas obras de arte ou obras especiais, utilizadas em rotas e vias de comunicação, possibilitando que veículos atravessem obstáculos naturais ou artificiais como, por exemplo, rios. Tais estruturas são calculadas e construídas considerando os esforços aos quais serão submetidas em serviço e sua distribuição na estrutura. Além disso, também existe a necessidade de se avaliar as frequências naturais de vibração para garantir a segurança das mesmas. No presente trabalho são analisados alguns problemas relacionados às vibrações de pontes e viadutos em grelha, resultantes das variações de rigidez e massa nessas estruturas. Essa análise foi feita considerando-se que vibrações excessivas não condizem com o conforto humano e durabilidade da ponte. Ademais, para a estrutura é interessante fugir do efeito de ressonância, que acontece quando a frequência de excitação coincide com uma das frequências naturais de oscilação do sistema. Essa condição faz o sistema vibrar em amplitudes cada vez maiores, podendo causar inclusive a ruína. Para estudar formas de sair de uma frequência natural não amortecida indesejada, foi realizada uma pesquisa paramétrica das características dinâmicas deste tipo de estrutura, modificando parâmetros como rigidez (pela distribuição de longarinas e de transversinas), massa (devido à alteração das dimensões) e danos estruturais causados durante a vida útil da estrutura. Com intuito de estudar diversos modelos, foram adotadas três diferentes situações de projeto: superestrutura com variadas alturas de longarinas e transversinas, da qual foi possível concluir que a altura da longarina tem mais impacto na frequência natural não amortecida da estrutura que a transversina; pequenos defeitos ou danos na estrutura e o efeito de uma longarina rompida para os quais foram comparadas suas frequências naturais não amortecidas. As análises foram realizadas pelo Método dos Elementos Finitos, utilizando-se o programa comercial SAP2000.Bridges are structures sometimes referred as works of art or special works, used on routes and roads that allow vehicles to cross natural or artificial obstacles, such as rivers. Such structures are calculated and constructed considering the efforts to which they will be submitted in service and their distribution in the structure. In addition, there is also a need to evaluate the natural frequencies of vibration to ensure their safety. In the present study some effects were analyzed related to the vibrations of grid bridges and viaducts resulting from changes in stiffness and mass in these structures. This analysis was made considering that excessive vibrations are not consistent with human comfort and bridge durability. For the structure, it is interesting to stay away from the resonance effect, which occurs when the excitation frequency matches one of the natural frequencies of oscillation of the system. This leads to oscillation with increasing amplitudes which may cause even the ruin. In order to study several models, three different design situations were adopted: superstructure with varying heights of beams and crossbeams, from which it was possible to conclude that the height of the beams has more impact on the undamped natural frequency of the structure than the crossbeams; small defects or damage to the structure and the effect of a ruptured beam for which its undamped natural frequencies were compared. The analysis were performed using the Finite Element Method, using the SAP2000 commercial program.
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Beeley, James Malcolm. "Design and construction of a distributed crossbar switch hypermesh parallel computer." Thesis, University of Glasgow, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.401958.
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Sahebkarkhorasani, Seyedmorteza. "A Non-destructive Crossbar Architecture of Multi-Level Memory-Based Resistor." OpenSIUC, 2015. https://opensiuc.lib.siu.edu/theses/1629.
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Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6µm to 22 µm. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation
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Yoshigoe, Kenji. "Design and evaluation of the combined input and crossbar queued (CICQ) switch." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000464.
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Stuart, Colin Tai Chen. "Fabrication of three-dimensional organic crossbar circuits by nanoimprint lithography and nanotransfer printing." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=2026649981&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Hung, Chun-Kit. "VLSI design of high-speed and scalable schedulers for input-queued crossbar switches /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HUNG.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.Includes bibliographical references (leaves 82-84). Also available in electronic version. Access restricted to campus users.
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Pessanha, Fábio Gonçalves. "Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar." Universidade do Estado do Rio de Janeiro, 2013. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=7436.
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Multi-Processor System-on-Chip (MPSoC) possui vários processadores, em um único chip. Várias aplicações podem ser executadas de maneira paralela ou uma aplicação paralelizável pode ser particionada e alocada em cada processador, a fim de acelerar a sua execução. Um problema em MPSoCs é a comunicação entre os processadores, necessária para a execução destas aplicações. Neste trabalho, propomos uma arquitetura de
rede de interconexão baseada na topologia crossbar, com memória compartilhada. Esta arquitetura é parametrizável, possuindo N processadores e N módulos de memórias. A
troca de informação entre os processadores é feita via memória compartilhada. Neste tipo de implementação cada processador executa a sua aplicação em seu próprio módulo de memória. Através da rede, todos os processadores têm completo acesso a seus módulos
de memória simultaneamente, permitindo que cada aplicação seja executada concorrentemente. Além disso, um processador pode acessar outros módulos de memória, sempre que necessite obter dados gerados por outro processador. A arquitetura proposta é modelada
em VHDL e seu desempenho é analisado através da execução paralela de uma aplicação, em comparação à sua respectiva execução sequencial. A aplicação escolhida consiste na otimização de funções objetivo através do método de Otimização por Enxame de Partículas (Particle Swarm Optimization - PSO). Neste método, um enxame de partículas é distribuído igualmente entre os processadores da rede e, ao final de cada interação, um processador acessa o módulo de memória de outro processador, a fim de obter a melhor posição encontrada pelo enxame alocado neste. A comunicação entre processadores é baseada
em três estratégias: anel, vizinhança e broadcast. Essa aplicação foi escolhida por ser computacionalmente intensiva e, dessa forma, uma forte candidata a paralelização.Multi-Processor System-on-Chip (MPSoC) has multiple processors in a single chip. Multiple applications can be executed in parallel or a parallelizable application can be partitioned and allocated to each processor in order to accelerate their execution. One problem in MPSoCs is the communication between the processors required to implement these applications. In this work, we propose the architecture of an interconnection network based on the crossbar topology, with shared memory. This architecture is parameterizable, having N processors and N memory modules. The exchange of information between processors is done via shared memory. In this type of implementation each processor executes its application stored in its own memory module. Through the network, all processors have complete access to their own memory modules simultaneously allowing each application to run concurrently. Moreover, a processor can access other memory modules, whenever it needs to retrieve data generated by another processor. The proposed architecture is modelled in VHDL and its performance is analysed by the execution of a parallel aplication, in comparison to its sequencial one. The chosen application consists of optimizing some objetive functions by using the Particle Swarm Optimization method. In this method, particles of a swarm are distributed among the processors and, at the end of each iteration, a processor accesses the memory module of another one in order to obtain the best position found in the swarm. The communication between processors is based on three strategies: ring, neighbourhood and broadcast. This application was chosen due to its computational intensive characteristic and, therefore, a strong candidate for parallelization.
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Hansen, Mirko [Verfasser]. "On the development of memristive devices for electroforming-free and analog memristive crossbar arrays / Mirko Hansen." Kiel : Universitätsbibliothek Kiel, 2018. http://d-nb.info/1167770986/34.
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Levisse, Alexandre. "3D high density memory based on emering resistive technologies : circuit and architecture design." Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0584.
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Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAMWhile conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures
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Rinklin, Philipp [Verfasser], Bernhard [Akademischer Betreuer] Wolfrum, and Jörg [Akademischer Betreuer] Fitter. "Microwire crossbar arrays for chemical, mechanical, and thermal stimulation of cells / Philipp Rinklin ; Bernhard Wolfrum, Jörg Fitter." Aachen : Universitätsbibliothek der RWTH Aachen, 2015. http://d-nb.info/1126971588/34.
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Bhide, Kanchan P. "DESIGN ENHANCEMENT AND INTEGRATION OF A PROCESSOR-MEMORY INTERCONNECT NETWORK INTO A SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/253.
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This thesis involves modeling, design, Hardware Description Language (HDL) design capture, synthesis, implementation and HDL virtual prototype simulation validation of an interconnect network for a Hybrid Data/Command Driven Computer Architecture (HDCA) system. The HDCA is a single-chip shared memory multiprocessor architecture system. Various candidate processor-memory interconnect topologies that may meet the requirements of the HDCA system are studied and evaluated related to utilization within the HDCA system. It is determined that the Crossbar network topology best meets the HDCA system requirements and it is therefore used as the processormemory interconnect network of the HDCA system. The design capture, synthesis, implementation and HDL simulation is done in VHDL using XILINX ISE 6.2.3i and ModelSim 5.7g CAD softwares. The design is validated by individually testing against some possible test cases and then integrated into the HDCA system and validated against two different applications. The inclusion of crossbar switch in the HDCA architecture involved major modifications to the HDCA system and some minor changes in the design of the switch. Virtual Prototype testing of the HDCA executing applications when utilizing crossbar interconnect revealed proper functioning of the interconnect and HDCA. Inclusion of the interconnect into the HDCA now allows it to implement dynamic node level reconfigurability and multiple forking functionality.
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Flocke, Alexander Verfasser], Tobias G. [Akademischer Betreuer] Noll, and Rainer [Akademischer Betreuer] [Waser. "Grundlegende Analyse der Schreib- und Leseoperationen in passiven Crossbar-Strukturen mit resistiv schaltenden Materialien / Alexander Flocke ; Tobias G. Noll, Rainer Waser." Aachen : Universitätsbibliothek der RWTH Aachen, 2015. http://d-nb.info/1130729982/34.
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Flocke, Alexander [Verfasser], Tobias G. Akademischer Betreuer] Noll, and Rainer [Akademischer Betreuer] [Waser. "Grundlegende Analyse der Schreib- und Leseoperationen in passiven Crossbar-Strukturen mit resistiv schaltenden Materialien / Alexander Flocke ; Tobias G. Noll, Rainer Waser." Aachen : Universitätsbibliothek der RWTH Aachen, 2015. http://d-nb.info/1130729982/34.
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Flocke, Alexander [Verfasser], Tobias [Akademischer Betreuer] Noll, and Rainer [Akademischer Betreuer] Waser. "Grundlegende Analyse der Schreib- und Leseoperationen in passiven Crossbar-Strukturen mit resistiv schaltenden Materialien / Alexander Flocke ; Tobias G. Noll, Rainer Waser." Aachen : Universitätsbibliothek der RWTH Aachen, 2015. http://nbn-resolving.de/urn:nbn:de:hbz:82-rwth-2016-015166.
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Alhaj, Ali Khaled. "New design approaches for flexible architectures and in-memory computing based on memristor technologies." Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2020. http://www.theses.fr/2020IMTA0197.
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Le développement récent de nouvelles technologies de mémoires non-volatiles basées sur le concept de memristor a suscité de nombreux efforts pour explorer leur utilisation potentielle dans différents domaines d'application. Les propriétés uniques de ces dispositifs memristifs et leur compatibilité pour uneintégration avec les technologies CMOS conventionnelles permettent de nouveaux paradigmes de conception d’architecture, offrant des niveaux sans précédent de densité, de reconfigurabilité et d’efficacité énergétique. Dans ce contexte, le but de ce travail de thèse était d'explorer et d'introduire de nouvelles approches de conception basées sur les memristors pour combiner flexibilité et efficacité en proposant des architectures originales qui dépassent les limites des architectures existantes. Cette exploration et cette étude ont été menées à trois niveaux : interconnexion, traitement et mémoire. Au niveau des interconnexions, nous avons étudié l'utilisation de dispositifs memristifs pour permettre une grande flexibilité basée sur des réseaux d'interconnexion programmables. Cela a permis de proposer la première architecture de transformée de Fourier rapide reconfigurable basée sur des memristors, nommée mrFFT. Les memristors sont insérés comme des commutateurs reconfigurables au niveau des interconnexions afin d'établir un routage flexible puce. Au niveau du traitement, nous avons exploré l'utilisation de dispositifs memristifs et leur intégration avec les technologies CMOS pour la conception de fonctions logique combinatoire. Ces circuits hybrides memristor-CMOS exploitent la forte densité d'intégration des memristors afin d'améliorer les performances des implémentations numériques, et en particulier des unités arithmétiques et logiques. Au niveau mémoire, une nouvelle approche de calcul en mémoire a été introduite. Dans ce contexte, un nouveau style de conception logique a été proposé, nommé Memristor Overwrite Logic (MOL), associé à une architecture originale de mémoire de calcul. L’approche proposée permet de combiner efficacement le stockage et le traitement afin de contourner les problèmes liés aux accès mémoire et d'améliorer ainsi l'efficacité de calcul. L'approche proposée a été appliquée dans trois études de cas à des fins de validation et d'évaluation des performancesThe recent development of new non-volatile memory technologies based on the memristor concept has triggered many research efforts to explore their potential usage in different application domains. The distinctive features of memristive devices and their suitability for CMOS integration are expected to lead for novel architecture design paradigms enabling unprecedented levels of energy efficiency, density, and reconfigurability. In this context, the goal of this thesis work was to explore and introduce new memristor based designs that combine flexibility and efficiency through the proposal of original architectures that break the limits of the existing ones. This exploration and study have been conducted at three levels: interconnect, processing, and memory levels. At interconnect level, we have explored the use of memristive devices to allow high degree of flexibility based on programmable interconnects. This allows to propose the first memristor-based reconfigurable fast Fourier transform architecture, namely mrFFT. Memristors are inserted as reconfigurable switches at the level of interconnects in order to establish flexible on-chip routing. At processing level, we have explored the use of memristive devices and their integration with CMOS technologies for combinational logic design. Such hybrid memristor-CMOS designs exploit the high integration density of memristors in order to improve the performance of digital designs, and particularly arithmetic logic units. At memory level, we have explored new in-memory computing approaches and proposed a novel logic design style, namely Memristor Overwrite Logic (MOL), associated with an original MOL-based computational memory. The proposed approach allows efficient combination of storage and processing in order to bypass the memory wall problem and thus to improve the computational efficiency. The proposed approach has been applied in three real application case studies for the sake of validation and performance evaluation
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Hasan, Md Raqibul. "Multi-core Architectures for Feed-forward Neural Networks." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1395140542.
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Hasan, Md Raqibul. "Memristor Based Low Power High Throughput Circuits and Systems Design." University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1459522347.
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Chabi, Djaafar. "Architectures de circuits nanoélectroniques neuro-inspirée." Phd thesis, Université Paris Sud - Paris XI, 2012. http://tel.archives-ouvertes.fr/tel-00679300.
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Les nouvelles techniques de fabrication nanométriques comme l'auto-assemblage ou la nanoimpression permettent de réaliser des matrices régulières (crossbars) atteignant des densités extrêmes (jusqu'à 1012 nanocomposants/cm2) tout en limitant leur coût de fabrication. Cependant, il est attendu que ces technologies s'accompagnent d'une augmentation significative du nombre de défauts et de dispersions de caractéristiques. La capacité à exploiter ces crossbars est alors conditionnée par le développement de nouvelles techniques de calcul capables de les spécialiser et de tolérer une grande densité de défauts. Dans ce contexte, l'approche neuromimétique qui permet tout à la fois de configurer les nanodispositifs et de tolérer leurs défauts et dispersions de caractéristiques apparaît spécialement pertinente. L'objectif de cette thèse est de démontrer l'efficacité d'une telle approche et de quantifier la fiabilité obtenue avec une architecture neuromimétique à base de crossbar de memristors, ou neurocrossbar (NC). Tout d'abord la thèse introduit des algorithmes permettant l'apprentissage de fonctions logiques sur un NC. Par la suite, la thèse caractérise la tolérance du modèle NC aux défauts et aux variations de caractéristiques des memristors. Des modèles analytiques probabilistes de prédiction de la convergence de NC ont été proposés et confrontés à des simulations Monte-Carlo. Ils prennent en compte l'impact de chaque type de défaut et de dispersion. Grâce à ces modèles analytiques il devient possible d'extrapoler cette étude à des circuits NC de très grande taille. Finalement, l'efficacité des méthodes proposées est expérimentalement démontrée à travers l'apprentissage de fonctions logiques par un NC composé de transistors à nanotube de carbone à commande optique (OG-CNTFET).
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Hubert, Quentin. "Optimisation de mémoires PCRAM pour générations sub-40 nm : intégration de matériaux alternatifs et structures innovantes." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01061795.
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Au cours des dernières années, la demande de plus en plus forte pour des mémoires non-volatiles performantes, a mené au développement des technologies NOR Flash et NAND Flash, qui dominent aujourd'hui le marché des mémoires non-volatiles. Cependant, la miniaturisation de ces technologies, qui permettait d'en réduire le coût, laisse aujourd'hui entrevoir ses limites. En conséquence, des mémoires alternatives et émergentes sont développées, et parmi celles-ci, la technologie des mémoires à changement de phase, ou PCRAM, est l'une des candidates les plus prometteuses tant pour remplacer les mémoires Flash, notamment de type NOR, que pour accéder à de nouveaux marchés tels que le marché des SCM. Toutefois, afin d'être pleinement compétitives avec les autres technologies mémoires, certaines performances de la technologie PCRAM doivent encore être améliorées. Au cours de cette thèse, nous cherchons donc à obtenir des dispositifs PCRAM plus performants. Parmi les résultats présentés, nous réduisons les courants de programmation et la consommation électrique des dispositifs tout en augmentant la rétention de l'information à haute température. Pour cela, nous modifions la structure du dispositif ou nous utilisons un matériau à changement de phase alternatif. De plus, à l'aide de solutions innovantes, nous permettons aux dispositifs PCRAM de conserver l'information pendant une éventuelle étape de soudure de la puce mémoire. Enfin, nous avons conçu, développé et validé un procédé de fabrication permettant d'intégrer une diode PN de sélection en Silicium en série avec un élément résistif PCRAM, démontrant l'intérêt de ce sélecteur vertical pour être utilisées comme élément de sélection d'une cellule PCRAM intégrée au sein d'une architecture crossbar.
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Vangal, Sriram R. "Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures." Licentiate thesis, Linköping : Linköpings universitet, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7845.
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Matos, Débora da Silva Motta. "Exploring hierarchy, adaptability and 3D in NoCs for the next generation of MPSoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/94764.
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A demanda por sistemas com elevado desempenho tem trazido a necessidade de aumentar o número de elementos de processamento, surgindo os chamados Sistemas em Chip Multiprocessados (MPSoCs). Além disso, com a possibilidade de redução da escala tecnológica na era submicrônica, permitindo a integração de vários dispositivos, os chips têm se tornado ainda mais complexos. No entanto, com o aumento no número de elementos de processamento, as interconexões são vistas com o principal gargalo dos sistemas-em-chip. Com isso, uma preocupação na forma como tais elementos se comunicam e estão interconectados tem sido levantada, uma vez que tais características são cruciais nos aspectos de desempenho, energia e potência, principalmente em sistemas embarcados. Essa necessidade permitiu o advento das redes-em-chip (Networks-on-Chip – NoCs) e inúmeros estudos já foram realizados para tais dispositivos. No entanto, devido ao aceleramento tecnológico atual, que traz a necessidade por sistemas ainda mais complexos, que consumam baixa energia e que permitam que as aplicações sejam constantemente atualizadas sem perder as características de desempenho, as arquiteturas de interconexão tradicionais não serão suficientes para satisfazer tais desafios. Outras alternativas de interconexão para MPSoCs precisam ser investigadas e nesse trabalho novas arquiteturas para NoCs com tais requisitos são apresentadas. As soluções propostas exploram hierarquia, adaptabilidade e interconexões em três dimensões. Esse trabalho aborda a necessidade do uso de diferentes estratégias em NoCs a fim de atingir os requisitos de desempenho e baixo consumo de potência dos atuais e futuros MPSoCs. Dessa forma, serão verificadas as diversas arquiteturas de interconexões para sistemas heterogêneos, sua escalabilidade, suas principais características e as vantagens das propostas apresentadas sobre as demais soluções.The demand for systems with high performance has brought the need to increase the number of cores, emerging the called Multi-Processors System-on-Chip (MPSoCs). Also, with the shrinking feature size in deep-submicron era, allowing the integration of several devices, chips have become even more complex. However, with the increase in these elements, interconnections are seen as the main bottleneck in many core systemson- chip. With this, a concern about how these devices communicate and are interconnected has been raised, since these features are crucial for the performance, energy and power consumption aspects, mainly in embedded systems. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies had already been done to analyze such interconnection devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming lower energy and providing constant application updates without losing performance features, traditional interconnect architectures will not be sufficient to satisfy such challenges. Other interconnecting alternatives for MPSoCs need to be investigated and in this work, novel architectures for NoCs meeting such requirements are presented. The proposed solutions explore hierarchy, adaptability and three dimensional interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the performance requisites and low power consumption of the current and future MPSoCs. Hence, in this approach, several interconnection architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.
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Gold, Brian. "Balancing Performance, Area, and Power in an On-Chip Network." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34137.
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Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications.
The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects.
This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption.Master of Science
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Nauenheim, Christian [Verfasser]. "Integration of resistive switching devices in crossbar structures / Christian Nauenheim. Forschungszentrum Jülich GmbH, Institute of Solid State Research (IFF), Electronic Materials (IFF-6). [Hrsg.: Forschungszentrum Jülich GmbH, Zentralbibliothek]." Jülich : Forschungszentrum, Zentralbibliothek, 2009. http://d-nb.info/1008265985/34.
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Akbaba, Erdem Eyup. "The Development And Hardware Implementation Of A High-speed Adaptable Packet Switch Fabric." Master's thesis, METU, 2013. http://etd.lib.metu.edu.tr/upload/12615454/index.pdf.
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Routers have to be fast enough to keep pace with increasing traffic data rate because of the increasing need for network bandwidth and processing. The switch fabric component of a router is a combination of hardware and software which moves the incoming packets to the outgoing ports. The access of the input ports to the switch fabric is controlled by a scheduler which affects the overall performance together with the fabric design. In this thesis we investigate two switch fabric and scheduler architectures, the well-known iSlip fabric scheduler and the Byte-Focal switch. We observe that these two architectures have different behaviors under different input traffic load ranges. The novel contribution of this thesis is a combined switch architecture which is composed of these two architectures that are implemented and run in parallel to selectively forward the packets with lower delay to the outputs to achieve an overall lower average delay. The design of the combined switch is carried out on FPGA and simulated. Our results show that the combined architecture has 100% throughput and a lower average delay compared to the Byte-Focal switch and the input-queued switch with iSlip. On the other hand, our combined switch uses more resources in FPGA than individual iSlip and Byte-Focal switch.
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Cvejn, Jiří. "Konstrukce multifunkčního obráběcího centra." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2013. http://www.nusl.cz/ntk/nusl-230922.
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The purpose of this diploma thesis is a design of frame, crossbar, transverse feed, sliding feed of multifunctional machining center. In the first part, there is a brief research of history of machine tool conducted, division of machining centers, materials for frame construction, alternatives of drives of sliding axis. Further, I carry out an analysis of parameters of compeeting machine tools, from which I selected the parameters of our machine. Frame project of the machine, propulsion of axis X and Y, kinematic connection of axis X,Y,Z. Frame of machine is analysed by Finite Element Method. Over the scope of this work I suggest a solution for covering of linear axis as well as their measuring of actual position. 3D model of frame and drives of machine are included in this work. A complete formation has been introduced into the immersive virtual reality environment.
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Charbonneau, Micaël. "Etude et développement de points mémoires résistifs polymères pour les architectures Cross-Bar." Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT116/document.
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Ces dix dernières années, les technologies de stockage non-volatile Flash ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimedia (MP3, Smartphone, clés USB, ordinateurs ultraportables…). Afin d’améliorer davantage les performances, augmenter les capacités et diminuer les coûts de fabrication, de nouvelles solutions technologiques sont aujourd’hui étudiées pour pouvoir compléter ou remplacer la technologie Flash. Citées par l’ITRS, les mémoires résistives polymères présentent des caractéristiques très prometteuses : procédés de fabrication à faible coût et possibilité d’intégration haute densité au dessus des niveaux d’interconnexions CMOS ou sur substrat souple. Ce travail de thèse a été consacré au développement et à l'étude des mémoires résistifs organiques à base de polymère de poly-méthyl-méthacrylate (PMMA) et de molécules de fullerènes (C60). Trois axes de recherche ont été menés en parallèle: le développement et la caractérisation physico-chimique de matériaux composites, l’intégration du matériau organique dans des structures de test spécifiques et la caractérisation détaillée du fonctionnement électrique des dispositifs et des performances mémoiresOver the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development & characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis
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Braun, Stefan. "Wafer-level heterogeneous integration of MEMS actuators." Doctoral thesis, Stockholm : Skolan för elektro- och systemteknik, Kungliga Tekniska högskolan, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-11833.
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LIAN, WEI-BO, and 連偉博. "Study of Crossbeam Thermal Deformation of Five-Axis Machine Tools." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/18677059676730409161.
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碩士國立雲林科技大學
機械工程系
104
In the study, we are focusing on crossbeam thermal deformation of five-axis machine tools. First, figure out the accuracy of the crossbeam in a variety of temperature. Second, set up a thermal experiment in a room temperature which would be changeable for a period of time, and collect the data. Third, input the data into thermal deformation model built by ANSYS Workbench to analyze the deformation of five-axis machine tools. Finally, we can investigate the influences between temperature and thermal deformation in order to get the accuracy that effect on machine. Keywords：Thermal deformation, Temperature, Crossbeam
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Chen, Tzu-lin, and 陳姿琳. "Using underground crossbeam to provide lateral resistances of pile with numerical method." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/05302533733781896699.
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碩士國立中央大學
土木工程研究所
95
Pile foundations are often used in large constructions. It can transfer the weight of structures directly to stiff layer or rock ground. However, the lateral resistances of piles in soft ground are limited. In order to conform to the practicability, the lateral displacement of pile must be restrained in a certain limit. This study focused on the treated effects of lateral displacement by underground crossbeam. The underground crossbeam can provide lateral resistance for pile which bears lateral load. The lateral bearing behaviors of pile in soft soil layer were analyzed by finite element method. To perform the numerical analysis, FEM based software named ABAQUS was used in this research. The analytic mode is governed by three parameters including lateral load, underground crossbeam’s length and underground crossbeam’s thickness respectively. Finally, the research showed the best mode of treatment by this numerical analysis results. The numerical results indicated that the lateral displacement decreases as the underground crossbeam’s length and depth increase. Installing underground crossbeam beneath the ground surface can provide suitable horizontal resistance and decrease the lateral displacement of the pile.
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HUANG, YI-HSIANG, and 黃義翔. "The Research of Design Optimization for Crossbeam in Five-Axis Gantry-Type Machine Tools." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/8x9pwz.
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碩士國立雲林科技大學
機械工程系
107
The five-axis gantry-type machine tool is widely used in processing large sized components for aircraft and automobile, which aims at high-speed and high-precision processing. However, the weight of five-axis gantry-type machine tool influences spindle head’s rotation reaction and machine tool’s dynamic characteristics, which influences the efficiency of the process. The purpose of this research is to reduce the weight of the crossbeam in five-axis gantry-type machine tool by changing its structure and maintaining the stiffness. The modification can reduce the loads caused by the weight and enhance the moving reaction of the crossbeam. This research is done by the finite element analysis software to simulate the deformation of the forced five-axis gantry-type machine tool. With the application of finite element analysis software, we can test the connection between the crossbeam and the deformation of five-axis gantry-type machine tool. This project can effectively optimize the cost, reduce time, and improve quality on development. Keyword：finite element method、optimization、machine tool