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Journal articles on the topic 'Crypto Processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Rashid, Muhammad, Sajjad Shaukat Jamal, Sikandar Zulqarnain Khan, Adel R. Alharbi, Amer Aljaedi, and Malik Imran. "Elliptic-Curve Crypto Processor for RFID Applications." Applied Sciences 11, no. 15 (July 31, 2021): 7079. http://dx.doi.org/10.3390/app11157079.

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This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

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2

Cho, Wook-Lae, Ki-Bbeum Kim, Gi-Chur Bae, and Kyung-Wook Shin. "A Crypto-processor Supporting Multiple Block Cipher Algorithms." Journal of the Korea Institute of Information and Communication Engineering 20, no. 11 (November 30, 2016): 2093–99. http://dx.doi.org/10.6109/jkiice.2016.20.11.2093.

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3

Somani, Turki F. Al, M. K. Ibrahim, and Adnan Gutub. "High Performance Elliptic Curve GF(2m) Crypto-processor." Information Technology Journal 5, no. 4 (June 15, 2006): 742–48. http://dx.doi.org/10.3923/itj.2006.742.748.

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4

Saad, Mahaba, Khalid Youssef, Mohamed Tarek, and Hala Abdel-Kader. "Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications." Indonesian Journal of Electrical Engineering and Computer Science 4, no. 2 (November 1, 2016): 412. http://dx.doi.org/10.11591/ijeecs.v4.i2.pp412-423.

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<p>Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6). The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers and provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. </p>

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5

Ahmadi, Hamid Reza, Ali Afzali-Kusha, and Massoud Pedram. "A power-optimized low-energy elliptic-curve crypto-processor." IEICE Electronics Express 7, no. 23 (2010): 1752–59. http://dx.doi.org/10.1587/elex.7.1752.

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6

Bouesse, Fraidy, M. Renaudin, and Fabien Germain. "Asynchronous AES Crypto-Processor Including Secured and Optimized Blocks." Journal of Integrated Circuits and Systems 1, no. 1 (November 16, 2004): 5–13. http://dx.doi.org/10.29292/jics.v1i1.249.

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This paper presents the first study of an asynchronous AES architecture compliant with the NIST standard. It exploits the fundamental properties of quasi delay insensitive asynchronous circuits. First, 1 to N encoding is extensively used in order to minimize hardware cost, thus optimizing area and speed. Most importantly, it is shown how the quasi delay insensitive logic style gives the opportunity to design balanced architectures, particularly well suited to improve differential power analysis resistance. Indeed, the proposed design methodology enables the generation of logic circuits which always involve a constant number of logical transitions, independently of data values processed by the circuit. Based on a 32-bit data-path, a balanced and optimized QDI asynchronous architecture of the AES is described. In addition, several architecture trade-offs are considered, and their area and speed estimated. Simulation results show that with the proposed design approach, throughputs ranging from 36 Mbit/s to more than 569 Mbit/s can be achieved, well suited to target smart-card applications.

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7

Machhout, Mohsen, Zied Guitouni, Kholdoun Torki, and Lazhar Khriji. "Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor." International journal of Network Security & Its Applications 2, no. 2 (April 25, 2010): 100–112. http://dx.doi.org/10.5121/ijnsa.2010.2208.

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8

Imran, Malik, Muhammad Rashid, Atif Raza Jafri, and Muhammad Najam-ul-Islam. "ACryp-Proc: Flexible Asymmetric Crypto Processor for Point Multiplication." IEEE Access 6 (2018): 22778–93. http://dx.doi.org/10.1109/access.2018.2828319.

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9

Huang, Hai, Bin Yu, Zhiwei Liu, Rui Weng, Junfeng Gao, and Mingyuan Ren. "DPA countermeasures for reconfigurable crypto processor using non-deterministic execution." IEICE Electronics Express 15, no. 24 (2018): 20180987. http://dx.doi.org/10.1587/elex.15.20180987.

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10

Qin, Xiaotie. "Software Architecture for IPSec Crypto Offload Based on Security Processor." Open Automation and Control Systems Journal 6, no. 1 (December 31, 2014): 952–58. http://dx.doi.org/10.2174/1874444301406010952.

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11

Imran, Malik, Muhammad Rashid, Atif Raza Jafri, and Muhammad Kashif. "Throughput/area optimised pipelined architecture for elliptic curve crypto processor." IET Computers & Digital Techniques 13, no. 5 (March 25, 2019): 361–68. http://dx.doi.org/10.1049/iet-cdt.2018.5056.

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12

Zhu, Yihong, Min Zhu, Bohan Yang, Wenping Zhu, Chenchen Deng, Chen Chen, Shaojun Wei, and Leibo Liu. "LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 3 (March 2021): 1146–59. http://dx.doi.org/10.1109/tcsi.2020.3048395.

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13

Di Matteo, Stefano, Luca Baldanzi, Luca Crocetti, Pietro Nannipieri, Luca Fanucci, and Sergio Saponara. "Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications." Energies 14, no. 15 (August 1, 2021): 4676. http://dx.doi.org/10.3390/en14154676.

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Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks. A simulated approach to extract power traces has been used to assess the effectiveness of the proposed algorithm compared to classical algorithms for Point Multiplication. A constant-time version of the Shamir’s Trick has been adopted to speed-up the Double-Point Multiplication and modular inversion is executed using Fermat’s Little Theorem, reusing the internal modular multipliers. The accelerator has been verified on a Xilinx ZCU106 development board and synthesized on both 45 nm and 7 nm Standard-Cell technologies.

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14

Han, Jun, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, and Xiaoyang Zeng. "A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 5 (May 2015): 1372–81. http://dx.doi.org/10.1109/tcsi.2015.2407431.

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15

Kahri, Fatma, Hassen Mestiri, Belgacem Bouallegue, and Mohsen Machhout. "High Speed FPGA Implementation of Cryptographic KECCAK Hash Function Crypto-Processor." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650026. http://dx.doi.org/10.1142/s0218126616500262.

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Cryptographic hash functions are at the heart of many information security applications like message authentication codes (MACs), digital signatures and other forms of authentication. One of the methods to ensure information integrity is the use of hash functions, which generates a stream of bytes (hash) that must be unique. But most functions can no longer prevent malicious attacks and ensure that the information have just a hash. Because of the weakening of the widely used SHA-1 hash algorithm and concerns over the similarly-structured algorithms of the SHA-2 family, the US National Institute of Standards and Technology (NIST) has initiated the SHA-3 contest in order to select a suitable drop-in replacement. KECCAK hash function has been submitted to SHA-3 competition and it belongs to the final five candidate functions. In this paper, we present the implementation details of the hash function’s KECCAK algorithm, moreover, the proposed KECCAK design has been implemented on XILINX FPGAs. Its area, frequency, throughput and efficiency have been derived and compared and it is shown that the proposed design allows a trade-off between the maximum frequency and the area implementation.

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16

Kang, Jae-Seok, and Min-Sup Kang. "FPGA Implementation of ARIA Crypto-processor Based on Advanced Key Scheduling." Journal of Security Engineering 13, no. 6 (December 31, 2016): 439–50. http://dx.doi.org/10.14257/jse.2016.12.05.

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17

Ahmad, N., and S. M. Rezaul Hasan. "Efficient integrated AES crypto-processor architecture for 8-bit stream cipher." Electronics Letters 48, no. 23 (2012): 1456. http://dx.doi.org/10.1049/el.2012.2932.

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18

Rashid, Muhammad. "Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor." IET Computers & Digital Techniques 15, no. 1 (January 2021): 77. http://dx.doi.org/10.1049/cdt2.12008.

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19

Bagul, Riya, Atharva Karaguppi, Vishwas Karale, Mudit Singal, and Dr Vaishali Ingale. "A Dynamic and Highly Configurable Crypto-Processor for brief communication interval." Journal of University of Shanghai for Science and Technology 23, no. 05 (May 25, 2021): 551–61. http://dx.doi.org/10.51201/jusst/21/05162.

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In modern computing systems data security is of paramount importance. The data transfer must be made secure because it can be significantly sensitive for any organization involved. This paper expounds a SOC architecture to facilitate end to end secure data exchange for applications involving short communication intervals. This SOC has been designed to behave as a co-processor which along with a standard general-purpose processor would serve as a cryptosystem. The SOC employs two famous algorithms – RSA and AES for cryptography. In contrast to usual single key cryptographic systems, this paper tries to elaborate an innovative methodology involving dynamic security measures that makes the system distributed rather than making it central to a specific algorithm and hence a particular key. The methodology involves generating and using an AES key for data encryption and RSA key for secure transfer of the AES key between the point of transmission and reception.

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20

Kim, Hyunji, Jaehoon Park, Hyeokdong Kwon, Kyoungbae Jang, and Hwajeong Seo. "Convolutional Neural Network-Based Cryptography Ransomware Detection for Low-End Embedded Processors." Mathematics 9, no. 7 (March 24, 2021): 705. http://dx.doi.org/10.3390/math9070705.

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A crypto-ransomware has the process to encrypt victim’s files. Afterward, the crypto-ransomware requests a ransom for the password of encrypted files to victims. In this paper, we present a novel approach to prevent crypto-ransomware by detecting block cipher algorithms for Internet of Things (IoT) platforms. We extract the sequence and frequency characteristics from the opcode of binary files for the 8-bit Alf and Vegard’s RISC (AVR) processor microcontroller. In other words, the late fusion method is used to extract two features from one source data, learn through each network, and integrate them. We classify the crypto-ransomware virus or harmless software through the proposed method. The general software from AVR packages and block cipher implementations written in C language from lightweight block cipher library (i.e., Fair Evaluation of Lightweight Cryptographic Systems (FELICS)) are trained through the deep learning network and evaluated. The general software and block cipher algorithms are successfully classified by training functions in binary files. Furthermore, we detect binary codes that encrypt a file using block ciphers. The detection rate is evaluated in terms of F-measure, which is the harmonic mean of precision and recall. The proposed method not only achieved 97% detection success rate for crypto-ransomware but also achieved 80% success rate in classification for each lightweight cryptographic algorithm and benign firmware. In addition, the success rate in classification for Substitution-Permutation-Network (SPN) structure, Addition-Rotation-eXclusive-or structures (ARX) structure, and benign firmware is 95%.

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21

Rashid, Muhammad, Malik Imran, Atif Raza Jafri, and Turki F. Al-Somani. "Flexible Architectures for Cryptographic Algorithms — A Systematic Literature Review." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1930003. http://dx.doi.org/10.1142/s0218126619300034.

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Symmetric and asymmetric cryptographic algorithms are used for a secure transmission of data over an unsecured public channel. In order to use these algorithms in real-time applications, many flexible hardware architectures have been proposed and implemented with multiple design constraints. Therefore, a systematic study is required to analyze various implementation approaches. This paper has focused on the identification and classification of recent research practices pertaining to the flexible hardware implementation of cryptographic algorithms. We have used Systematic Literature Review (SLR) process to identify 51 research articles, published during 2008–2017. The identified researches have been classified according to three design approaches: (1) crypto processor, (2) crypto coprocessor and (3) multicore crypto processor. Consequently, a comparative analysis of various cryptographic algorithms in terms of flexibility, throughput, area, power and implementation technology has been presented. A comprehensive investigation of flexible architectures for implementing cryptographic algorithms facilitates researchers and designers of the domain to select an appropriate design approach for a particular algorithm and/or application according to their needs.

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22

Moon, Sangook, and Jongsu Park. "System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/390176.

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As today’s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the microarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design are not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a soft and advanced type of SystemVerilog at an electronic system level. We apply the concept of design-and-reuse with a high level of abstraction to implement elliptic curve crypto-processor server farms. With the concept of the superior level of abstraction to the RTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms as well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required error-prone Verilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software, sacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m) serial multiplication architecture.

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23

Sung, Mi-Ji, and Kyung-Wook Shin. "8.3 Gbps pipelined LEA Crypto-Processor Supporting ECB/CTR Modes of operation." Journal of the Korea Institute of Information and Communication Engineering 20, no. 12 (December 31, 2016): 2333–40. http://dx.doi.org/10.6109/jkiice.2016.20.12.2333.

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24

Al-Somani, Turki F., M. K. Ibrahim, and Adnan Gutub. "Highly Efficient Elliptic Curve Crypto-Processor with Parallel GF(2m) Field Multipliers." Journal of Computer Science 2, no. 5 (May 1, 2006): 395–400. http://dx.doi.org/10.3844/jcssp.2006.395.400.

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25

SUGIYAMA, Shotaro, Hiromitsu AWANO, and Makoto IKEDA. "Low Latency 256-bit $\mathbb{F}_p$ ECDSA Signature Generation Crypto Processor." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101.A, no. 12 (December 1, 2018): 2290–96. http://dx.doi.org/10.1587/transfun.e101.a.2290.

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26

Liu, Leibo, Bo Wang, Chenchen Deng, Min Zhu, Shouyi Yin, and Shaojun Wei. "Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 12 (December 2018): 3081–94. http://dx.doi.org/10.1109/tcad.2018.2801229.

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27

Imran, Malik, and Faisal Shehzad. "FPGA Based Crypto Processor for Elliptic Curve Point Multiplication (ECPM) Over GF(2233)." International Journal for Information Security Research 7, no. 1 (March 30, 2017): 706–13. http://dx.doi.org/10.20533/ijisr.2042.4639.2017.0082.

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28

C, Lakshmi. "Reconfigurable Design of Low Power Hybrid Crypto Processor using Signcryption for Wireless Networks." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 3 (June 25, 2020): 4030–36. http://dx.doi.org/10.30534/ijatcse/2020/228932020.

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29

Cavo, Luis, Sébastien Fuhrmann, and Liang Liu. "Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices." Microprocessors and Microsystems 72 (February 2020): 102899. http://dx.doi.org/10.1016/j.micpro.2019.102899.

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30

Bikos, Anastasios N., and Nicolas Sklavos. "Architecture Design of an Area Efficient High Speed Crypto Processor for 4G LTE." IEEE Transactions on Dependable and Secure Computing 15, no. 5 (September 1, 2018): 729–41. http://dx.doi.org/10.1109/tdsc.2016.2620437.

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31

El-Hadidi, Mahmoud T., Hany M. Elsayed, Karim Osama, Mohamed Bakr, and Heba K. Aslan. "Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm." Journal of Advanced Research 12 (July 2018): 67–78. http://dx.doi.org/10.1016/j.jare.2017.11.002.

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32

Y.A, Suryawanshi, and Neha Trimbak Khadgi. "Design of Elliptic Curve Crypto Processor with Modified Karatsuba Multiplier and its Performance Analysis." International Journal of Distributed and Parallel systems 4, no. 3 (May 31, 2013): 95–104. http://dx.doi.org/10.5121/ijdps.2013.4308.

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33

DAN, Yong-ping, Xue-cheng ZOU, Zheng-lin LIU, Yu HAN, and Li-hua YI. "Design of highly efficient elliptic curve crypto-processor with two multiplications over GF(2163)." Journal of China Universities of Posts and Telecommunications 16, no. 2 (April 2009): 72–79. http://dx.doi.org/10.1016/s1005-8885(08)60206-x.

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34

Venugopal, K. R., G. Leelavathi, and K. Shaila. "Reconfigurable hardware architecture of public key crypto processor for VANET and wireless sensor nodes." International Journal of Vehicle Information and Communication Systems 5, no. 1 (2020): 11. http://dx.doi.org/10.1504/ijvics.2020.10029202.

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35

Leelavathi, G., K. Shaila, and K. R. Venugopal. "Reconfigurable hardware architecture of public key crypto processor for VANET and wireless sensor nodes." International Journal of Vehicle Information and Communication Systems 5, no. 1 (2020): 11. http://dx.doi.org/10.1504/ijvics.2020.107179.

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36

Kang, Jae-Seok, and Min-Sup Kang. "Design of AES Crypto-processor Based on Composite Field S-Box for Security CCTV System." Journal of Security Engineering 13, no. 5 (October 31, 2016): 363–78. http://dx.doi.org/10.14257/jse.2016.10.05.

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37

Choi, Piljoo, Ji-Hoon Kim, and Dong Kyue Kim. "Fast and Power-Analysis Resistant Ring Lizard Crypto-Processor Based on the Sparse Ternary Property." IEEE Access 7 (2019): 98684–93. http://dx.doi.org/10.1109/access.2019.2929299.

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38

Rani, Deevi Radha, and S. Venkateswarlu. "Security against Timing Analysis Attack." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 4 (August 1, 2015): 759. http://dx.doi.org/10.11591/ijece.v5i4.pp759-764.

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Timing attack is the type of side-channel attack involves the time taken to complete critical operations. Securing crypto processor from timing attack is critical issue. This paper implements the Bernstein’s Timing Attack and timing attack based on hamming weight. The countermeasures of Bernstein’s Timing attack are implemented in our experimental test bed and their performance is compared. This paper also proposes the key recovery method based on timing attack using hamming weight of the key.

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39

Abu Khadra, Shaimaa, Salah Eldin S. E. Abdulrahman, and Nabil A. Ismail. "Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices." Menoufia Journal of Electronic Engineering Research 29, no. 2 (July 1, 2020): 106–18. http://dx.doi.org/10.21608/mjeer.2020.103280.

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40

Sbiaa, Fatma, Sonia Kotel, Medien Zeghid, Rached Tourki, Mohsen Machhout, and Adel Baganne. "High-Level Implementation of a Chaotic and AES Based Crypto-System." Journal of Circuits, Systems and Computers 26, no. 07 (March 17, 2017): 1750122. http://dx.doi.org/10.1142/s0218126617501225.

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Given the increasing complexity of cryptographic devices, testing their security level against existing attacks requires a fast simulation environment. SystemC is a standard language that is widely used for the modeling and the verification of complex systems. It is a promising candidate in Electronic System Level (ESL) which allows models to reach higher simulation speed. Accordingly, the Advanced Encryption Standard (AES) is one of the most known block ciphers. It is widely used in various applications in order to secure the sensitive data. It is considered to be secure. Still, some issues lie in the used key and the S-Box. This paper presents a SystemC implementation of a chaos-based crypto-processor for the AES algorithm. The design of the proposed architecture is studied using the SystemC tools. The proposed correction approach exploits the chaos theory properties to cope with the defaulting parameters of the AES algorithm. Detailed experimental results are given in order to evaluate the security level and the performance criteria. In fact, the proposed crypto-system presents numerous interesting features, including a high security level, a pixel distributing uniformity, a sufficiently large key-space with improved key sensitivity, and an acceptable speed.

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41

Ho Won Kim and Sunggu Lee. "Design and implementation of a private and public key crypto processor and its application to a security system." IEEE Transactions on Consumer Electronics 50, no. 1 (February 2004): 214–24. http://dx.doi.org/10.1109/tce.2004.1277865.

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42

KASHIF, Muhammad, and İhsan ÇİÇEK. "Field-programmable gate array (FPGA) hardware design and implementation of a new area eﬀicient elliptic curve crypto-processor." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 29, no. 4 (July 26, 2021): 2127–39. http://dx.doi.org/10.3906/elk-2008-8.

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43

AWANO, Hiromitsu, Tadayuki ICHIHASHI, and Makoto IKEDA. "An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 1 (January 1, 2019): 56–64. http://dx.doi.org/10.1587/transfun.e102.a.56.

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44

Kumar, Raghavan, Xiaosen Liu, Vikram Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, and Sanu K. Mathew. "A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS." IEEE Journal of Solid-State Circuits 56, no. 4 (April 2021): 1141–51. http://dx.doi.org/10.1109/jssc.2021.3052146.

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45

Kim, Ki-Bbeum, Wook-Lae Cho, and Kyung-Wook Shin. "A Design of PRESENT Crypto-Processor Supporting ECB/CBC/OFB/CTR Modes of Operation and Key Lengths of 80/128-bit." Journal of the Korea Institute of Information and Communication Engineering 20, no. 6 (June 30, 2016): 1163–70. http://dx.doi.org/10.6109/jkiice.2016.20.6.1163.

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46

Haija, Qasem Abu Al, and Ahmad Al Badawi. "Cost-effective design for binary Edwards elliptic curves crypto-processor over GF (2^N) using parallel multipliers and architectures." International Journal of Information and Computer Security 5, no. 3 (2013): 236. http://dx.doi.org/10.1504/ijics.2013.055840.

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Weku, Winsy. "Model Proyeksi (X/Z2, Y/Z2) pada Kurva Hesian Secara Paralel Menggunakan Mekanisme Kriptografi Kurva Eliptik." JURNAL ILMIAH SAINS 12, no. 1 (April 30, 2012): 65. http://dx.doi.org/10.35799/jis.12.1.2012.404.

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MODEL PROYEKSI (X/Z2, Y/Z2) PADA KURVA HESIAN SECARA PARALEL MENGGUNAKAN MEKANISME KRIPTOGRAFI KURVA ELIPTIKABSTRAK Suatu kunci publik, Elliptic Curve Cryptography (ECC) dikenal sebagai algoritma yang paling aman yang digunakan untuk memproteksi informasi sepanjang melakukan transmisi. ECC dalam komputasi aritemetika didapatkan berdasarkan operasi inversi modular. Inversi modular adalah operasi aritmetika dan operasi yang sangat panjang yang didapatkan berdasar ECC crypto-processor. Penggunaan koordinat proyeksi untuk menentukan Kurva Eliptik/ Elliptic Curves pada kenyataannya untuk memastikan koordinat proyeksi yang sebelumnya telah ditentukan oleh kurva eliptik E: y2 = x3 + ax + b yang didefinisikan melalui Galois field GF(p)untuk melakukan operasi aritemtika dimana dapat diketemukan bahwa terdapat beberapa multiplikasi yang dapat diimplementasikan secara paralel untuk mendapatkan performa yang tinggi. Pada penelitian ini, akan dibahas tentang sistem koordinat proyeksi Hessian (X/Z2, Y,Z2) untuk meningkatkan operasi penggandaan ECC dengan menggunakan pengali paralel untuk mendapatkan paralel yang maksimum untuk mendapatkan hasil maksimal. Kata kunci: Elliptic Curve Cryptography, Public-Key Cryptosystem, Galois Fields of Primes GF(p PROJECTION MODEL (X/Z2, Y/Z2) ON PARALLEL HESIAN CURVE USING CRYPTOGRAPHY ELIPTIC CURVE MECHANISM ABSTRACT As a public key cryptography, Elliptic Curve Cryptography (ECC) is well known to be the most secure algorithms that can be used to protect information during the transmission. ECC in its arithmetic computations suffers from modular inversion operation. Modular Inversion is a main arithmetic and very long-time operation that performed by the ECC crypto-processor. The use of projective coordinates to define the Elliptic Curves (EC) instead of affine coordinates replaced the inversion operations by several multiplication operations. Many types of projective coordinates have been proposed for the elliptic curve E: y2 = x3 + ax + b which is defined over a Galois field GF(p) to do EC arithmetic operations where it was found that these several multiplications can be implemented in some parallel fashion to obtain higher performance. In this work, we will study Hessian projective coordinates systems (X/Z2, Y,Z2) over GF (p) to perform ECC doubling operation by using parallel multipliers to obtain maximum parallelism to achieve maximum gain. Keywords: Elliptic Curve Cryptography , Public-Key Cryptosystem , Galois Fields of Primes GF(p)

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Kong, Jia Hao, Li-Minn Ang, and Kah Phooi Seng. "A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box." Journal of Engineering 2013 (2013): 1–26. http://dx.doi.org/10.1155/2013/785126.

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The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.

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Murvay, Pal-Stefan, and Bogdan Groza. "Performance Evaluation of SHA-2 Standard vs. SHA-3 Finalists on Two Freescale Platforms." International Journal of Secure Software Engineering 4, no. 4 (October 2013): 1–24. http://dx.doi.org/10.4018/ijsse.2013100101.

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Embedded devices are ubiquitously involved in a large variety of security applications which heavily rely on the computation of hash functions. Roughly, two alternatives for speeding up computations co-exist in these resource constrained devices: parallel processing and hardware acceleration. Needles to say, multi-core devices are clearly the next step in embedded systems due to clear technological limitations on single processor frequency. Hardware accelerators are long known to be a cheaper approach for costly cryptographic functions. The authors analysis is focused on the five SHA-3 finalists which are also contrasted to the previous SHA-2 standard and to the widespread MD5. On the hardware side, the authors deploy their implementations on two platforms from Freescale: a S12X core equipped with an XGATE coprocessor and a Kinetis K60 core equipped with a crypto co-processor. These platforms differ significantly in terms of computational power, the first is based on a 16-bit Freescale proprietary architecture while the former relies on a more recent 32-bit Cortex core. The authors’ experimental results show mixed performances between the old standard and the new candidates. Some of the new candidates clearly outperform the old standard in terms of both computational speed and memory requirements while others do not. Bottom line, on the 16 bit platform BLAKE and Grøstl are the top performers while on the 32-bit platform Keccak, Blake and Skein give the best results.

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Ramalingam, Soodamani, Hock Gan, Gregory Epiphaniou, and Emilio Mistretta. "A Holistic Systems Security Approach Featuring Thin Secure Elements for Resilient IoT Deployments." Sensors 20, no. 18 (September 14, 2020): 5252. http://dx.doi.org/10.3390/s20185252.

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IoT systems differ from traditional Internet systems in that they are different in scale, footprint, power requirements, cost and security concerns that are often overlooked. IoT systems inherently present different fail-safe capabilities than traditional computing environments while their threat landscapes constantly evolve. Further, IoT devices have limited collective security measures in place. Therefore, there is a need for different approaches in threat assessments to incorporate the interdependencies between different IoT devices. In this paper, we run through the design cycle to provide a security-focused approach to the design of IoT systems using a use case, namely, an intelligent solar-panel project called Daedalus. We utilise STRIDE/DREAD approaches to identify vulnerabilities using a thin secure element that is an embedded, tamper proof microprocessor chip that allows the storage and processing of sensitive data. It benefits from low power demand and small footprint as a crypto processor as well as is compatible with IoT requirements. Subsequently, a key agreement based on an asymmetric cryptographic scheme, namely B-SPEKE was used to validate and authenticate the source. We find that end-to-end and independent stand-alone procedures used for validation and encryption of the source data originating from the solar panel are cost-effective in that the validation is carried out once and not several times in the chain as is often the case. The threat model proved useful not so much as a panacea for all threats but provided the framework for the consideration of known threats, and therefore appropriate mitigation plans to be deployed.

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