Academic literature on the topic 'CSS hardware acceleration'

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Journal articles on the topic "CSS hardware acceleration"

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Kang, S. "High performance hardware accelerator for design-error simulation." IEE Proceedings - Circuits, Devices and Systems 144, no. 2 (1997): 81. http://dx.doi.org/10.1049/ip-cds:19971008.

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Bensaali, F., A. Amira, and A. Bouridane. "Accelerating matrix product on reconfigurable hardware for image processing applications." IEE Proceedings - Circuits, Devices and Systems 152, no. 3 (2005): 236. http://dx.doi.org/10.1049/ip-cds:20040838.

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VOSS, G. A. "R&D PROGRESS TOWARD FUTURE LINEAR COLLIDERS." Modern Physics Letters A 14, no. 28 (1999): 1923–31. http://dx.doi.org/10.1142/s0217732399001991.

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During the last 20 years there has been a worldwide effort to develop the physics and technology of linear colliders. Present goals at SLAC, KEK and DESY are to bring the R&D efforts to the point where proposals for 500/1000 GeV cms electron–positron colliders can be officially submitted in the years 2002/2003. The CLIC study at CERN aims at a second generation very high energy electron–positron collider, to be considered after completion of the LHC. The main areas of hardware R&D include efficient accelerating waveguides without harmful higher order mode (h.o.m) effects, high peak power klystrons, klystron modulators and rf-power compression. Test facilities have been put in place for the testing of h.o.m behavior of new waveguide designs (ASSET), focusing on low emittance beams to spot sizes in the nanometer range (FFTB) and damping particle oscillations in a special damping ring (ATF) to prepare low emittance bunch trains of electrons for injection into linear colliders. The TESLA collaboration is making a major effort to develop the required technology for a superconducting linear collider. Test accelerator sections, which employ all the necessary new accelerator components, have been built and are currently being tested at SLAC and DESY.
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VOSS, GUSTAV-ADOLF. "R&D PROGRESS TOWARD FUTURE LINEAR COLLIDERS." International Journal of Modern Physics A 15, supp01b (2000): 806–15. http://dx.doi.org/10.1142/s0217751x00005425.

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During the last twenty years, there has been a world wide effort to develop the physics and technology of linear colliders. Present goals at SLAC, KEK, and DESY are to bring the R&D efforts to the point where proposals for 500/1000 GeV cms electron-positron colliders can be officially submitted in the years 2002/2003. The CLIC study at CERN aims at a second generation very high energy electron-positron collider, to be considered after completion of the LHC. The main areas of hardware R&D include efficient accelerating waveguides without harmful higher order mode (h.o.m.) effects, high peak power klystrons, klystron modulators, and rf-power compression. Test facilities have been put in place for the testing of h.o.m. behavior of new waveguide designs (ASSET), focusing of low emittance beams to spot sizes in the nanometer range (FFTB), and damping particle oscillations in a special damping ring (ATF) to prepare low emittance bunch trains of electrons for injection into linear colliders. The TESLA collaboration is making a major effort to develop the required technology for a superconducting linear collider. Test accelerator sections, which employ all the necessary new accelerator components, have been built and are currently being tested at SLAC and DESY.
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Summers, Sioni, and Andrew Rose. "Kalman Filter track reconstruction on FPGAs for acceleration of the High Level Trigger of the CMS experiment at the HL-LHC." EPJ Web of Conferences 214 (2019): 01003. http://dx.doi.org/10.1051/epjconf/201921401003.

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Track reconstruction at the CMS experiment uses the Combinatorial Kalman Filter. The algorithm computation time scales exponentially with pileup, which will pose a problem for the High Level Trigger at the High Luminosity LHC. FPGAs, which are already used extensively in hardware triggers, are becoming more widely used for compute acceleration. With a combination of high performance, energy efficiency, and predictable and low latency, FPGA accelerators are an interesting technology for high energy physics. Here, progress towards porting of the CMS track reconstruction to Maxeler Technologies’ Dataflow Engines is shown, programmed with their high level language MaxJ. The performance is compared to CPUs, and further steps to optimise for the architecture are presented.
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Romaniuk, Ryszard S. "Compact Muon Solenoid Decade Perspective and Local Implications." International Journal of Electronics and Telecommunications 60, no. 1 (2014): 79–84. http://dx.doi.org/10.2478/eletel-2014-0010.

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Abstract The Compact Muon Solenoid CMS is one of the major detectors of the LHC Large Hadron Collider accelerator. The second, a competitive brother, is Atlas. The accelerator complex in CERN was shut down for two years, after two years of exploitation, and will resume its work in 2015. During this break, called long shutdown LS1 a number of complex components, including electronics and photonics, will be intensely refurbished. Not only the LHC itself but also the booster components and detectors. In particular, the beam luminosity will be doubled, as well as the colliding beam energy. This means tenfold increase in the integrated luminosity over a year to 250fb−1/y. Discovery potential will be increased. This potential will be used for subsequent two years, with essentially no breaks, till the LS2 in 2017. The paper presents an introduction to the research area of the LHC and chosen aspects of the CMS detector modernization. The Warsaw CMS Group is involved in CMS construction, commissioning, maintenance and refurbishment, in particular for algorithms and hardware of the muon trigger. The Group consists of members form the following local research institutions, academic and governmental: IFD-UW, NCBJ-´Swierk and ISEWEiTI- PW.
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Andrews, Michael, Bjorn Burkle, Shravan Chaudhari, et al. "Accelerating End-to-End Deep Learning for Particle Reconstruction using CMS open data." EPJ Web of Conferences 251 (2021): 03057. http://dx.doi.org/10.1051/epjconf/202125103057.

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Machine learning algorithms are gaining ground in high energy physics for applications in particle and event identification, physics analysis, detector reconstruction, simulation and trigger. Currently, most data-analysis tasks at LHC experiments benefit from the use of machine learning. Incorporating these computational tools in the experimental framework presents new challenges. This paper reports on the implementation of the end-to-end deep learning with the CMS software framework and the scaling of the end-to-end deep learning with multiple GPUs. The end-to-end deep learning technique combines deep learning algorithms and low-level detector representation for particle and event identification. We demonstrate the end-to-end implementation on a top quark benchmark and perform studies with various hardware architectures including single and multiple GPUs and Google TPU.
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Yang, Bing, Xi Chen, Xiang Yun Liao, Mian Lun Zheng, and Zhi Yong Yuan. "FEM-Based Modeling and Deformation of Soft Tissue Accelerated by CUSPARSE and CUBLAS." Advanced Materials Research 671-674 (March 2013): 3200–3203. http://dx.doi.org/10.4028/www.scientific.net/amr.671-674.3200.

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Realistic modeling and deformation of soft tissue is one of the key technologies of virtual surgery simulation which is a challenging research field that stimulates the development of new clinical applications such as the virtual surgery simulator. In this paper we adopt the linear FEM (Finite Element Method) and sparse matrix compression stored in CSR (Compressed Sparse Row) format that enables fast modeling and deformation of soft tissue on GPU hardware with NVIDIA’s CUSPARSE (Compute Unified Device Architecture Sparse Matrix) and CUBLAS (Compute Unified Device Architecture Basic Linear Algebra Subroutines) library. We focus on the CGS (Conjugate Gradient Solver) which is the mainly time-consuming part of FEM, and transplant it onto GPU with the two libraries mentioned above. The experimental results show that the accelerating method in this paper can achieve realistic and fast modeling and deformation simulation of soft tissue.
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Ushaq, Muhammad, and Fang Jian Cheng. "A Fault Tolerant Integrated Navigation Scheme Realized through Online Tuning of Weighting Factors for Federated Kalman Filter." Applied Mechanics and Materials 446-447 (November 2013): 1078–85. http://dx.doi.org/10.4028/www.scientific.net/amm.446-447.1078.

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Strapdown Inertial navigation (SINS) is a highly reliable navigation system for short term applications. SINS functions continuously, less hardware failures, renders high speed navigation solutions ranging from 50 Hz to 1000 Hz and exhibits low short-term errors. It provides efficient attitude, angular rate, acceleration, velocity and position solutions. But, the accuracy of SINS solution vitiates with time as the sensor (gyros & accelerometers) errors are integrated through the navigation equations. Average navigation grade SINS are capable of providing effective stand-alone navigation for shorter duration (few minutes) applications Stand-alone SINS capable of providing solutions for applications exceeding 10 minutes duration, are generally highly expensive ($0.1M to $2.0M). To cope with this limitation, a cost effective solution is the integrated navigation system wherein the unboundedly growing errors of SINS are contained with the help of external non-inertial navigation aids like GPS, Celestial Navigation System (CNS), Odometer, Doppler radars etc. The efficient methodology for integrated or multi-sensory navigation is the Federated Kalman Filter (FKF) scheme. In FKF architecture, a reference SINS solution is integrated independently with each of the aiding navigation systems in a bank of local Kalman filters. There are a number of different ways in which the local filter outputs may be combined to produce an integrated navigation solution. The no-reset, fusion-reset, zero-reset, and cascaded versions of federated integration have been used by different researcher and navigators over the years. All different schemes of FKF have certain pros and cons. Fusion-reset method although nearly optimal is less fault tolerant while no-resent scheme renders highly fault tolerant solutions but with sub-optimal solutions and compromised precision. To enhance the fault tolerance ability of fusion-reset scheme of FKF, additional parameters called weighting factors are introduced to tune the contribution of each local filter in the final data fusion. The presented scheme has been found nearly optimal and expressively fault tolerant.
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Dissertations / Theses on the topic "CSS hardware acceleration"

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Urban, Martin. "Práce s historickými mapami na mobilním zařízení." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-235414.

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The goal of this thesis is to experiment with the latest web technologies and to design new process for mobile application creation. It is possible to create multiplatform applications which are almost unrecognizable from native applications by proposed procedures.  It is focused on performance and native behaviour of the user interface in this thesis. Described practices are demonstrated on application designed for work with historical maps, which is able to show maps from historical archives whole over world real-time. Rapid acceleration has been showed on the demonstrative application compared to standard process of creation of web applications.
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Book chapters on the topic "CSS hardware acceleration"

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Chang, Wanli, Swaminathan Narayanaswamy, Alma Pröbstl, and Samarjit Chakraborty. "Reliable CPS Design for Unreliable Hardware Platforms." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_23.

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AbstractToday, many battery-operated cyber-physical systems (CPS) ranging from domestic robots, to drones, and electric vehicles are highly software-intensive. The software in such systems involves multiple feedback control loops that implement different functionality. How these control loops are designed is closely related to both the semiconductor aging of the processors on which the software is run and also the aging of the batteries in these systems. For example, sudden acceleration in an electric vehicle can negatively impact the health of the vehicle’s battery. On the other hand, processors age over time and stress, impacting the execution of control algorithms and thus the control performance. With increasing semiconductor scaling, and our increasing reliance on battery-operated devices, these aging effects are of concern for the lifetime of these devices. Traditionally, the design of the control loops focused only on control-theoretic metrics, related to stability and performance (such as peak overshoot or settling time). In this chapter we show that such controller design techniques that are oblivious of the characteristics of the hardware implementation platform dramatically worsen the battery behaviour and violate the safety requirement with processor aging. However, with proper controller design these effects can be mitigated—thereby improving the lifetime of the devices.
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Conference papers on the topic "CSS hardware acceleration"

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Bag, Arnab, Sikhar Patranabis, L. Tribhuvan, and Debdeep Mukhopadhyay. "Hardware Acceleration of Searchable Encryption." In CCS '18: 2018 ACM SIGSAC Conference on Computer and Communications Security. ACM, 2018. http://dx.doi.org/10.1145/3243734.3278509.

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Gao, Yuanyuan, Li Zhou, Yanhu Chen, Yang Wang, Jia Wang, and Tao Sun. "A Hardware Acceleration Engine for Ray Tracing." In 2014 IEEE 17th International Conference on Computational Science and Engineering (CSE). IEEE, 2014. http://dx.doi.org/10.1109/cse.2014.118.

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Mai, Jingeng, Wanwen Chen, Shichang Zhang, Dongfang Xu, and Qining Wang. "Performance analysis of hardware acceleration for locomotion mode recognition in robotic prosthetic control." In 2018 IEEE International Conference on Cyborg and Bionic Systems (CBS). IEEE, 2018. http://dx.doi.org/10.1109/cbs.2018.8612257.

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Panait, Ovidiu, Luminita Dumitriu, and Ioan Susnea. "Hardware and Software Architecture for Accelerating Hash Functions Based on SoC." In 2019 22nd International Conference on Control Systems and Computer Science (CSCS). IEEE, 2019. http://dx.doi.org/10.1109/cscs.2019.00031.

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