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Journal articles on the topic 'CTE mismatch'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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1

YANG, CHEN, HUIQING FAN, SHAOJUN QIU, YINGXUE XI, and JIN CHEN. "EFFECTS OF THERMAL EXPANSION COEFFICIENT MISMATCH ON STRUCTURE AND ELECTRICAL PROPERTIES OF TiO2 FILM DEPOSITED ON Si SUBSTRATE." Surface Review and Letters 15, no. 04 (August 2008): 487–91. http://dx.doi.org/10.1142/s0218625x08011639.

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Effects of thermal expansion coefficient (CTE) mismatch on structure and electrical properties of TiO 2 film deposited on Si substrate by ion beam assistant electron beam evaporation have been investigated. Because of a high CTE mismatch between TiO 2 film and Si substrate, microcracks appeared in the TiO 2 film deposited directly on Si substrate after the as-deposited film was annealed at 600°C. In order to decrease the CTE mismatch, TiO 2 film was deposited on Si substrate which was covered by a ZrO 2 thin layer. As a result, crack–free TiO 2 film after annealed at the same temperature was obtained. Meanwhile, corresponding to the crack–free structure, the TiO 2 thin film has more stable dielectric properties and excellent I–V characteristics.
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2

Khaleque, Tasnuva, Xiaolong Zhang, Vijay Kumar Thakur, Adrianus Indrat Aria, and Hamed Yazdani Nezhad. "Tailoring of Thermo-Mechanical Properties of Hybrid Composite-Metal Bonded Joints." Polymers 13, no. 2 (January 6, 2021): 170. http://dx.doi.org/10.3390/polym13020170.

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Metallic substrates and polymer adhesive in composite-metal joints have a relatively large coefficient of thermal expansion (CTE) mismatch, which is a barrier in the growing market of electric vehicles and their battery structures. It is reported that adding carbon nanotubes (CNTs) to the adhesive reduces the CTE of the CNT-enhanced polymer adhesive multi-material system, and therefore when used in adhesively bonded joints it would, theoretically, result in low CTE mismatch in the joint system. The current article presents the influence of two specific mass ratios of CNTs on the CTE of the enhanced polymer. It was observed that the addition of 1.0 wt% and 2.68 wt% of multi-walled CNTs (MWCNTs) decreased the CTE of the polymer adhesive from 7.5×10−5 °C−1 (pristine level) to 5.87×10−5 °C−1 and 4.43×10−5 °C−1, respectively, by 22% and 41% reductions.
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3

Palmer, Michael J., R. Wayne Johnson, Mohammad Motalab, Jeffrey Suhling, and James D. Scofield. "Development of a Silicon Nitride High Temperature Power Module." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000172–79. http://dx.doi.org/10.4071/hiten-paper7-rwjohnson.

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Silicon nitride (Si3N4) offer potential advantages as a substrate for high temperature power packaging. Si3N4 has higher fracture strength than alumina and aluminum nitride. The coefficient of thermal expansion (CTE) of Si3N4 is ~3 ppm/°C and the thermal conductivity ranges from 30–50W/m-K. Active metal brazed Cu-Si3N4 substrates are commercially available for power modules. However, the large mismatch in CTE between Si3N4 and Cu results in ceramic fracture and delamination with the wide temperature thermal cycling ranges encountered in high temperature applications. In this work Cu-Carbon and Cu-Mo metal matrix composites have been investigated to reduce the CTE mismatch. The process details are presented along with finite element modeling of the proposed structure. Ultimately, the proposed structure was unsuccessful.
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4

Chen, Cheng Gang, Kevin H. Hoos, and Ming Yung Chen. "Ceramic/Polymeric Hybrids with Reduced Coefficients of Thermal Expansion." Advances in Science and Technology 63 (October 2010): 120–25. http://dx.doi.org/10.4028/www.scientific.net/ast.63.120.

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The mismatch of the coefficient of the thermal expansion (CTE) is one of the main causes of crack initiation and delamination for carbon fiber-reinforced polymer hybrids and metal/polymer hybrid materials. In this research, a negative CTE ceramic material (zirconium tungstate) was incorporated with a thermoset polymer (bismaleimide) resulting in a ~40% reduction in CTE and a significant improvement in thermal stability. The morphology showed good dispersion of the zirconium tungstate particles within the bismaleimide. Comparisons of the experimental CTE values with the rule-of-mixture and the analytical micromechanical models will be discussed.
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5

Nomura, Shuhei, Shigeki Sawamura, Yu Hanawa, Yusuke Sakai, and Kazutaka Hayashi. "Novel glass substrates for minimizing thermal stress development during electronic device packaging process." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000607–11. http://dx.doi.org/10.4071/isom-2016-thp33.

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Abstract Glass can be utilized for support or career substrate in large size packaging process since it has excellent mechanical and optical properties. However, the thermal stress caused by a mismatch of coefficient of thermal expansion (CTE) causes an unneglectable warpage during a thermal process. In order to overcome this thermal stress issue, we have developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on a glass substrate whose CTE is perfectly matched with that of Si, and a series of glass substrates whose CTEs are controlled in sub-ppm order and within the range of 3.3 ~ 12.0 ppm/°C. To evaluate the effect of glass CTE on the thermal stress management, the warpage behavior of Si wafer after glass wafer bonding were investigated by both numerical simulation and experiment. Both results indicate that a small CTE mismatch can cause an unneglectable wafer warpage during the thermal process. Thus sub-ppm order control of glass CTE is essential for minimizing thermal stress development in large size packaging process. The glass substrate with Si matched CTE is suitable for the process where glass and Si are contact directly, e.g. Si back grinding process or through glass via (TGV) technology. The series of glass substrates whose CTEs are finely controlled in a high range are useful when the packaging process utilizes high amount of resins, such as Fan-Out wafer level packaging process.
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6

Bhatkal, Ravi M., Ranjit Pandher, Anna Lifton, Paul Koep, and Hafez Raeisi Fard. "Evaluating Thermal Cycling Fatigue Resistance for LED Chip-on-Board Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 000706–37. http://dx.doi.org/10.4071/2012dpc-ta43.

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LED chip-on-board applications typically involve assembling an LED die stack directly on to a high thermal conductivity substrate such as a Metal Core PCB. If solder is used for die-substrate attach for such chip-on-board applications, one needs to consider the CTE mismatch between the die stack and the MCPCB and its impact on thermal cycle-induced creep fatigue of the solder material. This paper presents a methodology to compare relative performance of different solder materials with varying thermo-mechanical properties, and compare the impact of CTE mismatch and temperature swings on transient thermal properties and relative reliability of the solder attach materials. Implications for LED chip-on-board applications are discussed.
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7

Park, Sang Hyun, Jin Ho Kang, Seoung Soo Lee, Yeon Gil Jung, and Ung Yu Paik. "Control of Shrinkage Behavior and Thermal Expansion Coefficient in BaTiO3-Added Ni Electrodes." Key Engineering Materials 336-338 (April 2007): 765–68. http://dx.doi.org/10.4028/www.scientific.net/kem.336-338.765.

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In this study, shrinkage behavior and coefficient of thermal expansion (CTE) of novel nickel (Ni) powder with an addition of dielectric material, BaTiO3, have been investigated to reduce the large shrinkage mismatch between Ni electrode and dielectric material and to control the thermal and/or residual stresses created by CTE mismatch in MLCCs (multilayer ceramic capacitors). For which two kinds of Ni powders were used. The component of Ni powders is analyzed by XRF, and the thermal behavior is measured by TG/DTA. The Ni and BaTiO3 powders were mixed with 9:1, 8:2, and 7:3 volume ratios. The BaTiO3-added Ni green bodies were fabricated through cold isostatic pressing, and then sintered to 1300°C in a reduction atmosphere. The shrinkage behavior with volume ratio was checked during sintering from 700 to 1300°C with 300°C interval. The CTE was measured in inert (argon) atmosphere with sintered samples. It is found that the shrinkage behavior and the CTE of Ni electrode are dependent on the volume of BaTiO3 added. The particle size of Ni powder also affects the microstructure and its sintering density, with less effect of its component.
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8

Sujan, D., X. B. Pang, M. E. Rahman, and M. M. Reddy. "Performance of Solder Bond on Thermal Mismatch Stresses in Electronic Packaging Assembly." Materials Science Forum 773-774 (November 2013): 242–49. http://dx.doi.org/10.4028/www.scientific.net/msf.773-774.242.

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Thermo-mechanical stresses have been considered one of the major concerns in electronic Packaging assembly structural failure. The interfacial stresses are often caused by the thermal mismatch stresses induced by the coefficient of thermal expansion (CTE) difference between materials, typically during the high temperature change in the bonding process. This research work examined the effect of bond layer on thermal mismatch interfacial stresses in a bi-layered assembly. The paper verified the existing thermal mismatch solder bonded bi-layered analytical model using finite element method (FEM) simulation. The parametric studies were carried out on the effect of change of bond layer properties in order to provide useful references for interfacial stress evaluation and the electronic packaging assembly design. These parameters included CTE, temperature, thickness, and stiffness (compliant and stiff bond) of the bond layer. The recent development on lead free bonding material was being reviewed and found to have enormous potential and key role to address the future electronic packaging assembly reliability.
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9

Kitazono, Koichi, Eiichi Sato, and Kazuhiko Kuribayashi. "Unified Constitutive Equation of CTE-Mismatch Superplasticity Based on Continuum Micromechanics." Materials Science Forum 357-359 (January 2001): 289–94. http://dx.doi.org/10.4028/www.scientific.net/msf.357-359.289.

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10

Morelock, Cody R., Matthew R. Suchomel, and Angus P. Wilkinson. "A cautionary tale on the use of GE-7031 varnish: low-temperature thermal expansion studies of ScF3." Journal of Applied Crystallography 46, no. 3 (April 6, 2013): 823–25. http://dx.doi.org/10.1107/s0021889813005955.

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GE-7031 varnish, a commonly used low-temperature adhesive and electrical insulator owing to its high thermal conductivity and mechanical strength at low temperatures, was used as a sample matrix for low-temperature powder X-ray diffraction measurements of the negative thermal expansion (NTE) material ScF3. When ScF3powder was mixed with GE-7031 varnish, an unexpected cubic to rhombohedral phase transition in the ScF3sample was observed at ∼50 K, and it exhibited smaller low-temperature unit-cell volumes than samples without the varnish matrix. Experimental observations and quantitative estimates suggest that these anomalies are the result of stress induced by a thermal expansion mismatch between the varnish matrix (large positive coefficient of thermal expansion, CTE) and ScF3(quite large negative CTE). The use of GE-7031 varnish as a sample matrix for low-temperature measurements should be approached with caution if a large thermal expansion mismatch is expected.
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11

Dwarakanath, Shreya, P. Markondeya Raj, Kaya Demir, Vanessa Smet, Venky Sundaram, and Rao Tummala. "Electrodeposited Copper-Graphite Composites for Low-CTE-Integrated Thermal Structures." Journal of Microelectronics and Electronic Packaging 14, no. 2 (April 1, 2017): 56–62. http://dx.doi.org/10.4071/imaps.435561.

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Abstract Emerging high-power and high-temperature electronic modules require thick copper structures for power supply, thermal vias, heat spreaders, and also as carriers or lead frames for high-power packages. Such structures should coexist with glass and other substrates with low coefficient of thermal expansion (CTE) to meet high-temperature performance, dimensional stability, and superior device interconnection reliability with low stresses and warpage. The primary challenge with these packages arises from the CTE mismatch between the conductors and the substrates. Cu-graphite composites with glass-matched CTE are explored to address this challenge through analytical modeling of properties such as CTE, Young's modulus and thermal conductivity, finite-element-modeling predictions of glass warpage and stresses, process development to deposit copper-graphite composite films with high graphite loading of 64 vol. %, and warpage measurements using shadow moiré. Results indicate that Cu-graphite composites can mitigate the warpage and stress issues in high-temperature and high-power packages.
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12

Dwarakanath, Shreya, P. Markondeya Raj, Kaya Demir, Vanessa Smet, Venky Sundaram, and Rao Tummala. "Electrodeposited copper-graphite composites for low-CTE integrated thermal structures." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000088–93. http://dx.doi.org/10.4071/isom-2016-tp45.

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Abstract Emerging high-power and high-temperature electronic modules require thick copper structures for power-supply, thermal vias, heat-spreaders, and also as carriers or lead-frames for high-power packages. Such structures should coexist with glass and other low-CTE substrates to meet high-temperature performance, dimensional stability and superior device interconnection reliability with low stresses and warpage. The primary challenge with these packages arises from the coefficient of thermal expansion (CTE) mismatch between the conductors and the substrates. Cu-graphite composites with glass-matched CTE are explored to address this challenge through analytical modeling of properties such as CTE, Young's modulus and thermal conductivity, FEM predictions of glass warpage and stresses, process development to deposit copper-graphite composite films with high graphite loading of 64 vol. %, and warpage measurements using shadow-moiré. Results indicate that Cu-graphite composites can mitigate the warpage and stress issues in high-temperature and high-power packages.
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13

Fragoudakis, Roselita, Michael A. Zimmerman, and Anil Saigal. "Application of a Ag Ductile Layer in Minimizing Si Die Stresses in LDMOS Packages." Key Engineering Materials 605 (April 2014): 372–75. http://dx.doi.org/10.4028/www.scientific.net/kem.605.372.

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Lateral Diffused Metal Oxide Semiconductors (LDMOS) normally have a Cu-W flange, whose CTE is matched to Si. Low cost Cu substrate material provides 2X high thermal conductivity, and along with a AuSi eutectic solder is recommended for optimal thermal performance. However, the CTE mismatch between Cu and Si can lead to failure of the semiconductor as a result of die fracture, due to thermal stresses developed during the soldering step of the manufacturing process. Introducing a Ag ductile layer is very important in minimizing such thermal stresses and preventing catastrophic failure of the semiconductor. Ag is a ductile material electroplated on the Cu substrate to absorb stresses developed during manufacturing due to the CTE mismatch between Si and Cu. The Ag layer thickness affects the magnitude of the resulting thermal stresses. This study attempts to measure the yield strength of the Ag layer, and examines the optimal layer thickness to minimize die stresses and prevent failure. The yield stress of the ductile layer deposited on a Cu flange was measured by nanoindentation. The Oliver and Pharr method was applied to obtain modulus of elasticity and yield depth of Ag. A finite element analysis of the package was performed in order to map die stress distribution for various ductile layer thicknesses. The analysis showed that increasing the ductile layer thickness up to 0.01 - 0.02 mm, decreases the Si die stresses.
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14

Mohd Amin, Nurfatin Liyana, Muhamad Khairudin Rahim, Nor Akmal Fadil, and Astuty Amrin. "The Effect of Temperature on Nickel Deposited as an Underlayer Between Copper Filler and Silicon Wafer." Journal of Computational and Theoretical Nanoscience 17, no. 2 (February 1, 2020): 1271–74. http://dx.doi.org/10.1166/jctn.2020.8800.

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Through silicon via (TSV) has garnered a lot of interest in the semiconductor industry due to its ability to provide the shortest interconnect path. The coefficient of thermal expansion (CTE) mismatch between the copper (Cu) interconnection filler and the silicon (Si) wafer result in reliability issues of the TSV system. This research proposed the introduction of an underlayer between the Cu filler and Si wafer in order to reduce the CTE mismatch in the TSV. The chosen underlayer is nickel (Ni) as it has a CTE value placed in between Cu and Si at 13 ppm/°C (Cu = 17 ppm/°C, Si = 2.8 ppm/°C). The Ni layer was deposited using the electroless deposition process at different temperature of plating bath (75 °C, 85 °C, and 95 °C) and deposition time (20, 40, and 60 minutes). The analysis of the microstructure of the Ni layer deposited on the Si wafer was characterized. The adhesion test was conducted using the ATM D3359 (Measuring Adhesion by Tape Test) Standard for coating adhesion test and the 4-Point Probe Test for the resistivity measurement. It was found that the optimum Ni plating temperature was at 85 °C based on its adhesion and high stability of plating bath. The resistivity test showed that the increased of Nickel underlayer thickness deposited between copper and Si wafer has slightly increased the resistivity.
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15

Kim, Seong Keol, Chong-Min Jang, Jung-Min Hwang, and Man-Chul Park. "Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging." Journal of The Korean Society of Manufacturing Technology Engineers 22, no. 1 (February 15, 2013): 168–72. http://dx.doi.org/10.7735/ksmte.2013.22.1.168.

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16

Heinrich, S. M., S. Shakya, and P. S. Lee. "Improved Analytical Estimate of Global CTE Mismatch Displacement in Areal-Array Solder Joints." Journal of Electronic Packaging 119, no. 4 (December 1, 1997): 218–27. http://dx.doi.org/10.1115/1.2792240.

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An analytical expression is derived for determining the maximum solder joint shearing displacement occurring in an a real-array interconnect under global CTE mismatch loading. The result may be viewed as a “load correction factor” to be applied to the commonly used estimate which is based on the free thermal expansion of component and substrate. The new expression for the correction factor includes the following parameters: (a) dimensions and material properties of component and substrate; (b) array size and population; (c) material properties of solder; and (d) geometric parameters of the individual joints. The theoretical result is based on modeling the assembly as two circular elastic disks connected by a shear-type “elastic foundation” whose distributed shear stiffness is related to the joint/array characteristics. The analytical expression and the graphical aids presented herein may provide convenient alternatives to performing time-consuming and expensive finite element “macro-analyses” on the assembly for the purpose of specifying boundary conditions for a subsequent “micro-analysis” on a single joint.
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17

Joliff, Yoann, Joseph Absi, Marc Huger, and Jean Claude Glandus. "Microcracks with unexpected characteristics induced by CTE mismatch in two-phase model materials." Journal of Materials Science 43, no. 1 (October 17, 2007): 330–37. http://dx.doi.org/10.1007/s10853-007-1691-x.

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18

Jikihara, Alice N., Carina B. Tanaka, Rafael Y. Ballester, Michael V. Swain, Antheunis Versluis, and Josete B. C. Meira. "Why a zero CTE mismatch may be better for veneered Y-TZP structures." Journal of the Mechanical Behavior of Biomedical Materials 96 (August 2019): 261–68. http://dx.doi.org/10.1016/j.jmbbm.2019.04.049.

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19

Chen, Ming Yung, and Cheng Gang Chen. "Lightweight Hybrid Foam with Dimensional Stability." Advances in Science and Technology 63 (October 2010): 114–19. http://dx.doi.org/10.4028/www.scientific.net/ast.63.114.

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Availability of advanced materials has opened up opportunities in meeting several functional requirements through hybridization. Hybrids consisting of ceramics, metals and high performance polymers could benefit many aircraft and space satellite applications. They could meet requirements of low weight, high environmental stability, and high thermal or dimensional stability. In this study, hybrid materials consisting of high performance polymer, porous ceramics (glass microballoons) and other constituents such as Zircornium Tungstate (with negative coefficient of thermal expansion (CTE)) and nanoclay were studied. Specimens were successfully produced with a range of density from 0.4 to 1.1 g/cm3 depending on the degree of fill in the syntactic foams. CTE tailoring was achieved to greatly reduce the residual stress arising from processing and CTE mismatch of dissimilar materials. The evaluations of dimensional stability were examined from thermomechanical analysis. The synergistic effects of resin, ceramic constituents and pores on the hybrid properties will be presented.
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20

Schöbel, Michael, Guillermo C. Requena, Heinz Kaminski, Hans Peter Degischer, Thomas Buslaps, and Marco Di Michiel. "Residual Stresses and Void Kinetics in AlSiC MMCs during Thermal Cycling." Materials Science Forum 571-572 (March 2008): 413–18. http://dx.doi.org/10.4028/www.scientific.net/msf.571-572.413.

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AlSi7Mg/SiC/70p (AlSiC) is used for heat sinks because of its good thermal conductivity combined with a low coefficient of thermal expansion (CTE). These properties are important for power electronic devices where heat sinks have to provide efficient heat transfer to a cooling device. A low CTE is essential for a good surface bonding of the heat sink material to the insulating ceramics. Otherwise mismatch in thermal expansion would lead to damage of the bonding degrading the thermal contact within the electronic package. Therefore AlSiC replaces increasingly copper heat sinks. The CTE mismatch between insulation and a conventional metallic heat sink is transferred into the MMC heat sink. The stability of the interface bonding within a MMC is critical for its thermal properties. In situ thermal cycling measurements of an AlSi7Mg/SiC/70p MMC are reported yielding the void volume fraction and internal stresses between the matrix and the reinforcements in function of temperature. The changes in void volume fractions are determined simultaneously by synchrotron tomography and residual stresses by synchrotron diffraction at ESRF-ID-15. The measurements show a relationship between thermal expansion, residual stresses and void formation in the MMC. The results obtained from the in situ measurements reveal a thermoelastic range up to 200 °C followed by plastic matrix deformation reducing the volume of voids during heating. A reverse process takes place during cooling. Thus the CTE becomes smaller than according to thermoelastic calculations. Damage could be observed after multiple heating cycles, which increase the volume fraction and the size of the voids. The consequence is local debonding of the matrix from the reinforcement particles, which leads to an irreversible reduction of the thermal conductivity after multiple heating cycles.
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21

Tang, Shi Bin, Zheng Zhao Liang, and Ya Fang Zhang. "Study on the Thermal Cracking Processes of Composite Subjected to Thermal Loading." Applied Mechanics and Materials 256-259 (December 2012): 2867–70. http://dx.doi.org/10.4028/www.scientific.net/amm.256-259.2867.

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A numerical method RFPA-T (Thermal Induced Rock Failure Process Analysis) code is used to study the thermal cracking processes of quasi-brittle materials subjected to high or low temperature. The numerical results indicate that thermal stress concentrating along the interface between the matrix and the embedded grains due to their different coefficient of thermal expansion (CTE). The modeling results indicate that θ-crack is generated during temperature increment as the CTE of the embedded grain is smaller than that of the matrix. However, radial-cracks emerged when the temperature decrease. The results obtained from RFPA-T code show a good agreement with experimental evidence of crack patterns caused by thermal expansion mismatch.
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22

Rubinsztajn, Slawomir, Donald Buckley, John Campbell, David Esler, Eric Fiveland, Ananth Prabhakumar, Donna Sherman, and Sandeep Tonapi. "Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials." Journal of Electronic Packaging 127, no. 2 (June 1, 2005): 77–85. http://dx.doi.org/10.1115/1.1846067.

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Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.
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23

Chou, Yeong-Shyung, and Jeffry W. Stevenson. "Novel silver/mica multilayer compressive seals for solid-oxide fuel cells: The effect of thermal cycling and material degradation on leak behavior." Journal of Materials Research 18, no. 9 (September 2003): 2243–50. http://dx.doi.org/10.1557/jmr.2003.0313.

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A novel Ag/mica compressive seal was thermally cycled between 100 °C and 800 °C in air to evaluate its stability. The novel Ag/mica compressive seal was composed of a naturally cleaved Muscovite mica sheet and two thin silver layers, and was reported in a previous study to have very low leak rates at 800 °C. In the present study, we examined the thermal cycle stability of the Ag/mica-based compressive seals pressed between mating couples with large and small mismatch in thermal expansion. For comparison, thermal cycling also was conducted on plain mica as well as plain silver only. In addition, the results were compared with published data of a similar mica seal using glass instead of Ag as the interlayers. For mating materials of large mismatch in thermal expansion coefficient (CTE; Inconel/alumina), the Ag/mica seal showed lower leak rates than the plain mica. For mating materials of small mismatch in CTE (SS430/alumina), the leak rates were similar for both the Ag/mica and the plain mica seal. Scanning electron microscopy was used to characterize the microstructure of the mica after thermal cycling. Microcracks, fragmentation, and wear-particle formation were observed on the mica and were correlated to the leak behavior. Overall, the novel Ag/mica seals present good thermal cycle stability for solid-oxide fuel cells, although the leak rates were greater than the corresponding mica seals with glass interlayers.
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24

Mei, Yaochuan, Peter J. Diemer, Muhammad R. Niazi, Rawad K. Hallani, Karol Jarolimek, Cynthia S. Day, Chad Risko, John E. Anthony, Aram Amassian, and Oana D. Jurchescu. "Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps." Proceedings of the National Academy of Sciences 114, no. 33 (July 24, 2017): E6739—E6748. http://dx.doi.org/10.1073/pnas.1705164114.

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The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms.
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25

Gupta, Vineet K., and Donald B. Barker. "Influence of Surface Mount Lead End Geometry on Fatigue Life." Journal of Electronic Packaging 116, no. 2 (June 1, 1994): 157–60. http://dx.doi.org/10.1115/1.2905505.

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The local coefficient of thermal expansion (CTE) mismatch between compliant surface mount component leads and the solder that is used to attach the components to a printed wiring board can dramatically influence the thermal fatigue life of the solder joint. To quantify the contribution of the local CTE mismatch to the overall thermal fatigue damage of the solder joint, a finite element thermal fatigue simulation using an energy partitioning technique is used to compare four different lead end shapes. The four lead configurations considered are J-lead, and three gullwings leads; one with the foot parallel to the board surface, one with the foot sloped slightly downward towards the board, and one with the foot sloped slightly upward. The dimensions of the leads are purposely chosen so that the in-plane compliance is equal for the different lead shapes, only the shape of the lead end varied. Comparisons are first made with equal solder joint heights and then the solder height of the gull-wing lead is varied between 0.05 to 0.23 mm (2 to 9 mils). The influence of the solder wetting angle is also investigated.
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26

Jang, Ju-Woong, Byung Soo Kim, Hak Kwan Kim, and Deuk Yong Lee. "Correlation between Thermal Expansion Coefficients of La2O3-Al2O3-SiO2 Glasses and Strength of the Glass Infiltrated Alumina for all Ceramic Crown." Materials Science Forum 449-452 (March 2004): 1193–96. http://dx.doi.org/10.4028/www.scientific.net/msf.449-452.1193.

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16 different lanthanum-aluminosilicate glasses were prepared to evaluate the effect of alkalis (Na2O, K2O) and alkaline earths (MgO, CaO) on thermal expansion coefficients (CTEs) of the glasses. Analysis was performed with an aid of the Taguchi method and orthogonal arrays to elucidate four factor interactions between 4 two-level factors using two level L16(215) orthogonal arrays. The observed CTEs were in the range of 6.29×10-6 C-1 to 8.22×10-6 C-1. The addition of alkalis was more influential to CTE of the glass than that of alkaline earth, however, co-addition of the mixed alkalis was detrimental to CTEs of the glasses due to the crystallization caused by the mixed alkali effect. However, the highest strength of the glass infiltrated alumina composite was observed at a CTE of 6.4×10-6 C-1 due to the compressive stress caused by the thermal mismatch, indicating that CTE difference between the glass and the alumina should be above 1.0×10-6 C-1.
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Tanimoto, Satoshi, Hidekazu Tanisawa, Kinuyo Watanabe, Kohei Matsui, and Shinji Sato. "Power Module Package Structure Capable of Surviving Greater ΔTj Thermal Cycles." Materials Science Forum 740-742 (January 2013): 1040–43. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1040.

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A new SiC power module package structure is proposed that is capable of withstanding greater ΔTj cycle stress. Its most notable feature is the use of a SiN substrate having Cu/Invar/Cu foils (C/I/C thickness ratio of 1/8/1) brazed on both sides as conductor plates. The CIC foils show a very low coefficient of thermal expansion (CTE) of 5.1 ppm/°C and therefore can significantly reduce package degradation resulting from the larger CTE mismatch of the conductor to SiC and SiN. A thermal cycle test (TCT) was conducted between -40°C and 250°C (ΔTj = 290°C). It was found that the SiC/Au-Ge/CIC-SiN die attachment maintained joint strength of 78 MPa even after 3000 cycles.
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28

Kim, Hong Gun. "A Study on the Thermoelastic Analysis in Shear Deformable Discontinuous Composites." Key Engineering Materials 261-263 (April 2004): 645–50. http://dx.doi.org/10.4028/www.scientific.net/kem.261-263.645.

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A stress analysis has been performed to evaluate the thermally induced elastic stresses which can develop in a short fiber composite due to coefficient of thermal expansion (CTE) mismatch. An axisymmetric finite element model with the constraint between cells has implemented to find the magnitude of thermoelastic stresses in the fiber and the matrix as a function of volume fraction, CTE ratio, modulus ratio, and fiber aspect ratio. It was found that the matrix end regions fall under significant thermal stresses that have the same sign as that of the fibers themselves. Furthermore, it was found that the stresses vary along the fiber and fiber end gap in the same manner as that obtained in a shear-lag model during non-thermal mechanical loading.
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YANG, FAN, DAI-NING FANG, BIN LIU, and CHANG-AN WANG. "THERMAL-ELASTIC BEHAVIORS OF STAGGERED COMPOSITES." International Journal of Applied Mechanics 01, no. 04 (December 2009): 569–80. http://dx.doi.org/10.1142/s1758825109000319.

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A theoretical model is developed to predict the Coefficient of Thermal Expansion (CTE) and thermal mismatch stress of composites with staggered hard platelets in parallel alignment in a soft matrix. The theoretical predictions agree well with the Finite Element Method (FEM) simulations. The results show that different from sandwich composites, the effective CTEs of staggered composite can be tailored by adjusting the aspect ratio of reinforced platelets even with the same volume fraction, which makes the staggered composites more thermal-elastically compatible with the neighboring structures or materials. Moreover, the thermal mismatch stress in the two phases of staggered composite can be reduced through designing microstructure geometry parameters. The staggered composites therefore may have potential application in thermal protections.
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30

Huger, M., T. Ota, N. Tessier-Doyen, P. Michaud, and T. Chotard. "Microstructural effects associated to CTE mismatch for enhancing the thermal shock resistance of refractories." IOP Conference Series: Materials Science and Engineering 18, no. 22 (September 16, 2011): 222002. http://dx.doi.org/10.1088/1757-899x/18/22/222002.

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31

Heinrich, S. M., S. Shakya, and P. S. Lee. "Effect of Component Heterogeneity on Global CTE Mismatch Displacement in Areal-Array Solder Interconnects." Journal of Electronic Packaging 120, no. 1 (March 1, 1998): 12–17. http://dx.doi.org/10.1115/1.2792278.

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An analytical model is developed for the problem of a thermally loaded electronic assembly consisting of a nonhomogeneous component attached to a substrate by means of an areal array of solder joints. The component is heterogeneous in the sense that the interior, or “die”, portion and the exterior, or “carrier”, portion may have different elastic moduli, different coefficients of thermal expansion, and/or different temperature excursions. Analytical results are presented for determining (a) the location of the critical joint(s) in the array, defined as those experiencing the maximum shearing displacement due to global CTE mismatch, and (b) the magnitude of the maximum shearing displacement. The critical joint location and the (dimensionless) peak displacement are shown to depend on only two parameters: one involving the material, geometric, and loading characteristics of the component and substrate, the other being the ratio of the die dimension to the array dimension. The stiffness of the solder array is neglected in the model; thus, the results should be valid for (a) thermal/power cycling of low-modulus solders (relative to component and substrate materials), and (b) high-temperature, low-frequency thermal/power cycling, for which a large degree of stress relaxation occurs in the solder. The results may also provide conservative estimates for situations involving stiffer arrays.
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Yamada, Tomoyuki, Masahiro Fukui, Kenji Terada, Masaaki Harazono, Teruya Fujisaki, Sushumna Iruvanti, Charles Carey, et al. "Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package." International Symposium on Microelectronics 2014, no. 1 (October 1, 2014): 000068–73. http://dx.doi.org/10.4071/isom-ta31.

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In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper. In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented. The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.
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Courcot, Emilie, and Francis Rebillat. "Overview: How to Quantify the Capability of Yttrium Silicates to be Used as an Environmental Barrier Coating." Advances in Science and Technology 66 (October 2010): 80–85. http://dx.doi.org/10.4028/www.scientific.net/ast.66.80.

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To be used as environmental barrier coatings, yttrium silicates must be thermally and chemically stable at high temperatures, under high pressures in a moist environment. This work proposes a full method to quantify their thermo chemical and mechanical stabilities: (i) in a corrosive environment at high temperature and (ii) against the covered material to protect. These stabilities were first estimated by thermodynamic calculations and further confirmed with corrosion tests. This first step needed: (i) to measure the partial pressures of yttrium hydroxides through corrosion tests on the simple oxide, Y2O3 and (ii) to extract the free energies of formation of gaseous yttrium-hydroxides formed. In a second step, the measured values of coefficients of thermal expansion (CTE) on these materials allowed identifying what compositions should be preferentially used, to get CTE close to that of the substrate material to prevent delaminating or cracking due to CTE mismatch stress. Finally, these materials are deposited on SiC/SiC composites by plasma spraying. The impact of the morphology, crystallinity, porosity and composition of elaborated coatings on their corrosion behaviour is highlighted.
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34

Sukantharat, Anan, Kessararat Ugsornrat, and Chalermsak Sumithpibul. "Effect of Epoxy Molding Compound Material and Roughness Leadframe to Integrated Circuit Package for Automotive Devices." ECTI Transactions on Electrical Engineering, Electronics, and Communications 18, no. 2 (August 31, 2020): 179–88. http://dx.doi.org/10.37936/ecti-eec.2020182.240488.

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This research studied about an effect of epoxy molding compound material and roughness leadframe of integrated circuit package for automotive device. In manufacturing process, the epoxy molding compound material and leadframe roughness are main factors that effect to coefficient of thermal expansion (CTE) and reliability for automotive device package with no delamination in high temperature application. In experiment, two types of epoxy molding compound materials were studied and compared between standard and roughened leadframe for quad flat non lead (QFN) package. For reliability test, the epoxy molding compound materials type A and type B with different leadframe were analyzed with moisture sensitivity level 1 to observe delamination inside packages. The results showed that CTE of epoxy molding compound material type A is less CTE mismatch than that of epoxy molding compound material type B with both standard and roughness leadframe. Moreover, the results also found no delamination for epoxy molding compound material type A with roughened leadframe. In addition, both epoxy molding compound materials showed significant delamination inside packages with standard leadframe.
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35

Charbonneau, Paul, Hans Ohman, and Marc Fortin. "Solder Joint Reliability Assessment for a High Performance RF Ceramic Package." International Symposium on Microelectronics 2014, no. 1 (October 1, 2014): 000062–67. http://dx.doi.org/10.4071/isom-ta26.

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The prediction of long term solder joint reliability, (SJR), of microelectronic devices and packaging solutions continues to challenge the microelectronic packaging industry, particularly with the introduction of lead-free materials, the push for higher performance (frequency/speed/thermal) and lower unit cost. High performance packages are generally custom designed and therefore have minimal industry data on configuration specific reliability performance. In this application, the package substrate coefficient of thermal expansion, (CTE), was closely matched to the die resulting in a relatively large CTE mismatch between the package and organic PCB. In addition, the package RF and thermal performance requirements required this particular solution to be configured as a “cavity down” perimeter ball array with a large central ground pad to electrically couple the package to the PCB. Given the package's unique design requirements and CTE mismatch, even modest daily temperature swings of 20°C usually found in a controlled or “Central Office” environment could have an adverse impact on the interconnect reliability. This study provides an overview of the solder joint reliability assessment methodologies performed for a custom design lead-free, high performance RF package as part of the requirements to demonstrate compliance to product specifications. SJR life predictions were made for varying package BGA configurations using a multi-tiered approach using constitutive material models, thermo-mechanical finite element simulations, and material specific fatigue models. Empirical accelerated life testing was performed and a life prediction obtained through modeling was validated. Finally, statistical failure distributions were fit to empirical data and discussed in the context of absolute solder life predictions of small fractions unit failures, (100ppm).
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36

Kim, Gun Rae, Sang-Su Ha, Sangwoo Pae, Jongwoo Park, and Byoungdeog Choi. "Reliability Impacts on Flip Chip Packages: Moisture Resistance, Mechanical Integrity and Photo-Sensitive Polyimide (PSPI) Passivation." Science of Advanced Materials 12, no. 4 (April 1, 2020): 577–82. http://dx.doi.org/10.1166/sam.2020.3669.

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In this paper, the effects of moisture sensitivity during preconditioning (30 °C/60% RH, 192 hours) tests and material property changes after reliability stressing on flip chip chip-scale package (FCCSP) were comprehensively investigated by various experimental data as well as theoretical explanation. Since the integrity of FCCSP is dependent on the mechanical integrity of underfill and PCB used in package assembly process, deep insight was given on the material properties in order to understand degradation mechanism induced by the combined stresses of preconditioning test and environmental stresses in a sequence. As a result of DOE (Design of Experiment) for 2 different PCB, failures were found only in J PCB because of a large CTE change before and after moisture absorption. After moisture absorption, large CTE change from 27.78 to 32.04 of J PCB could aggravate the thermal mismatch between a PCB and an underfill, it caused shear displacement by more than 2,309 ppm in the interface. According to the DOE for underfill, we verified that higher modulus underfill could improve the reliability of flip chip packages. Based on our works, we recommend the optimized value for underfill modulus is from 8 GPa to 12 GPa. We explained logically two different failure mechanisms of delamination. One is induced by CTE mismatch of PCB, and the other is by underfill modulus by means of electron microscope. Finally, as to reliability concerns of moisture resistance arisen from the absence of the photo-sensitive polyimide (PSPI) passivation layer, we demonstrated that potential risk is minimal if FCCSP is assembled with an appropriate underfill as well as PCB.
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37

Lopes, Murilo Baena, Zhuoqun Yan, Simonides Consani, Alcides Gonini Júnior, Anderson Aleixo, and John F. McCabe. "Evaluation of the coefficient of thermal expansion of human and bovine dentin by thermomechanical analysis." Brazilian Dental Journal 23, no. 1 (2012): 03–07. http://dx.doi.org/10.1590/s0103-64402012000100001.

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The mismatch of thermal expansion and contraction between restorative materials and tooth may cause stresses at their interface, which may lead to microleakage. The present work compared the coefficient of thermal expansion (CTE) with the thermomechanical behavior of human and bovine teeth and determined if the CTE is a suitable parameter to describe tooth behavior. Fifteen human third molar and 15 bovine incisor tooth slices (6×5×2 mm) were allocated to 3 groups according to the test environment: G1 - room condition, G2 - 100% humidity, G3 - desiccated and tested in dry condition. Each specimen was weighed, heated from 20 to 70ºC at 10ºC min−1 and reweighed. The CTE was measured between 20 and 50ºC. Fresh dentin (human -0.49% ± 0.27, bovine -0.22% ± 0.16) contracted on heating under dry condition. Under wet conditions, only human teeth (-0.05% ± 0.04) showed contraction (bovine 0.00% ± 0.03) accompanied by a significantly lower (p<0.05) weight loss than in dry specimens (human 0.35% ± 0.15, bovine 0.45% ± 0.20). The desiccated dentin expanded on heating without obvious weight changes (0.00% ± 0.00). The CTE found was, respectively, in dry, wet and dissected conditions in ºC-1: human (-66.03×10-6, -6.82×10-6, 5.52×10-6) and bovine (-33.71×10-6, 5.47×10-6, 4.31×10-6). According to its wet condition, the dentin showed different CTEs. The thermal expansion behavior of human and bovine dentin was similar. A simple evaluation of the thermal expansion behavior of tooth structure by its CTE value may not be appropriate as a meaningful consideration of the effects on the tooth-material interface.
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38

Srolovitz, D. J., S. M. Yalisove, and J. C. Bilello. "Design of multiscalar metallic multilayer composites for high strength, high toughness, and low CTE mismatch." Metallurgical and Materials Transactions A 26, no. 7 (July 1995): 1805–13. http://dx.doi.org/10.1007/bf02670768.

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39

Sujan, D., T. K. Piaw, and Dereje Engida Woldemichael. "Thermo-Mechanical Stress Analysis in Electronic Packaging with Continuous and Partial Bond Layer." Applied Mechanics and Materials 465-466 (December 2013): 50–54. http://dx.doi.org/10.4028/www.scientific.net/amm.465-466.50.

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Interfacial stress due to thermal mismatch in layered structure has been considered as one of the major causes of mechanical failure in electronic packaging. The mismatch due to the differences in coefficient of thermal expansion (CTE) of the materials in multi-layered structure may induce severe stress concentration to the electronic composites namely interfacial delamination and die cracking. Therefore, the studies and evaluation of interfacial stress in electronic packaging become significantly important for optimum design and failure prediction of the electronic devices. The thermal mismatch shear stress for bi-layered assembly can be analyzed by using the mathematical models based on beam theory. In this study, Finite Element Method (FEM) simulation was performed to an electronic package by using ANSYS. The shear stress growth behavior at the interface of the bonded section was studied with the considerations of continuous and partial bond layers in the interfaces. Based on the analysis, it can be observed that the partial bond layer with small center distances can be simplified as a continuous bond layer for bi-layered shearing stress model analysis.
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40

Ley, K. L., M. Krumpelt, R. Kumar, J. H. Meiser, and I. Bloom. "Glass-ceramic sealants for solid oxide fuel cells: Part I. Physical properties." Journal of Materials Research 11, no. 6 (June 1996): 1489–93. http://dx.doi.org/10.1557/jmr.1996.0185.

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A family of sealant materials has been developed for use in the solid oxide fuel cell (SOFC) and in other applications in the temperature range of 800–1000 °C. These materials are based on glasses and glass-ceramics in the SrO–La2O3–Al2O3–B2O3–SiO2 system. The coefficients of thermal expansion (CTE) for these materials are in the range of 8–13 × 10−6/°C, a good match with those of the SOFC components. These sealant materials bond well with the ceramics of the SOFC and, more importantly, form bonds that can be thermally cycled without failure. At the fuel cell operating temperature, the sealants have viscosities in the range of 104–106 Pa-s, which allow them to tolerate a CTE mismatch of about 20% among the bonded substrates. The gas tightness of a sample seal was demonstrated in a simple zirconia-based oxygen concentration cell.
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41

Dash, Khushbu, Suvin Sukumaran, and Bankim C. Ray. "The behaviour of aluminium matrix composites under thermal stresses." Science and Engineering of Composite Materials 23, no. 1 (January 1, 2016): 1–20. http://dx.doi.org/10.1515/secm-2013-0185.

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AbstractThe present review work elaborates the behaviour of aluminium matrix composites (AMCs) under various kinds of thermal stresses. AMCs find a number of applications such as automobile brake systems, cryostats, microprocessor lids, space structures, rocket turbine housing, and fan exit guide vanes in gas turbine engines. These applications require operation at varying temperature conditions ranging from high to cryogenic temperatures. The main objective of this paper was to understand the behaviour of AMCs during thermal cycling, under induced thermal stresses and thermal fatigue. It also focuses on the various thermal properties of AMCs such as thermal conductivity and coefficient of thermal expansion (CTE). CTE mismatch between the reinforcement phase and the aluminium matrix results in the generation of residual thermal stress by virtue of fabrication. These thermal stresses increase with increasing volume fraction of the reinforcement and decrease with increasing interparticle spacing. Thermal cycling enhances plasticity at the interface, resulting in deformation at stresses much lower than their yield stress. Low and stable CTE can be achieved by increasing the volume fraction of the reinforcement. The thermal fatigue resistance of AMC can be increased by increasing the reinforcement volume fraction and decreasing the particle size. The thermal conductivity of AMCs decreases with increase in reinforcement volume fraction and porosity.
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42

Lu, Hua, C. Bailey, and M. Cross. "Reliability Analysis of Flip Chip Designs Via Computer Simulation." Journal of Electronic Packaging 122, no. 3 (January 17, 2000): 214–19. http://dx.doi.org/10.1115/1.1286122.

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A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young’s modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE CTEz of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias. [S1043-7398(00)01203-2]
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43

Ghosh, Barun, Fang Xu, and Xianghui Hou. "Thermally conductive poly(ether ether ketone)/boron nitride composites with low coefficient of thermal expansion." Journal of Materials Science 56, no. 17 (March 5, 2021): 10326–37. http://dx.doi.org/10.1007/s10853-021-05923-0.

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AbstractThe substantial heat generation due to miniaturization and high-degree integration of electronic devices is one of the major issues to facilitate efficient thermal management in power electronics. Though epoxy-based composites have shown great interest in different applications such as laminated circuit board, electronic component encapsulations, and potting, they have low application temperature (up to 150 °C) and higher mismatch of coefficient of thermal expansion (CTE) between the heat source and heat sink. Here, poly(ether ether ketone) (PEEK) composites reinforced with hexagonal boron nitride (hBN) nanoplatelets have been developed by liquid mixing and re-melting method for a step change in composite materials with lower CTE and significantly improved thermal dissipation capability. The lowest achieved CTE is 2.1 µm m−1 K−1, and the highest thermal conductivity is 1.04 W m−1 K−1 in PEEK/hBN composites at 30 wt% hybrid hBN content (hBN platelets with two different sizes, i.e. 70 nm and 500 nm, taken as 1:1 weight ratio), due to the formation of thermally conductive inter-filler networks. The composites show negligible variation in K with the working temperature up to 250 °C. The developed composites also exhibit excellent electrical insulation properties; thus, they will have good potential in thermal management for power electronic applications. Graphical abstract
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44

Su, Y. F., K. N. Chiang, and Steven Y. Liang. "Design and Reliability Assessment of Novel 3D-IC Packaging." Journal of Mechanics 33, no. 2 (September 9, 2016): 193–203. http://dx.doi.org/10.1017/jmech.2016.82.

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AbstractPresently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.
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45

Kornain, Zainudin, Azman Jalar, Rozaidi Rashid, and Shahrum Abdullah. "An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging." Advanced Materials Research 97-101 (March 2010): 23–27. http://dx.doi.org/10.4028/www.scientific.net/amr.97-101.23.

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Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.
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46

Tang, Jie, Yan Li Huo, Yu Feng Chen, Hai Lin Liu, Chun Peng Wang, and Xiao Ying Peng. "Preparation of Compositionally Graded CVD SiC Oxidation-Resistant Coating." Key Engineering Materials 434-435 (March 2010): 562–64. http://dx.doi.org/10.4028/www.scientific.net/kem.434-435.562.

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A SiC coating was chemical vapour deposited (CVD) on a Cf/SiC composite with the ratio of H2 and methyltrichlorosilane (MTS) changed gradually from 6:1 to 12:1 during the CVD processing. Energy-dispersive spectrometry (EDS) of the coating showed that the content of C decreased while Si increased continuously from the interface between coating and Cf/SiC substrate to the outside surface of coating. The obtained compositionally graded structure effectively reduced the generation of microcracks by releasing the mismatch of CTE of the coating and the composite.
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47

Fan, Guangyu, Christine Labarbera, Ning-Cheng Lee, and Colin Clark. "Shear Strength and Thermomechanical Reliability of Sintered Ag Joints Containing low CTE Non-metal Additives for Die Attach." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000167–72. http://dx.doi.org/10.4071/2380-4505-2018.1.000167.

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Abstract Ag sintering has been paid attention as an alternative to soldering in die attach for decades, especially for high temperature power electronics packages because of its high melting temperature, highly thermal and electrical conductivity of the sintered silver joints, and low process temperature less than 275°C. The coefficient of thermal expansion (CTE) of silver (19.1ppm/°C), however, is much higher than the silicon die (2.6ppm/°C) and the commonly used alumina substrate (7.2ppm/°C). CTE mismatch of the different materials in the various components in a power electronics package lead to the delamination at the interface between interconnection layer and chips or substrate, and/or cracking of the interconnection layer is one of the mostly common causes of failure of power electronics device during thermal cycling or high temperature operation. In recent years we have been developing a series of silver sinter pastes containing low CTE non-metal particles to reduce or adjust CTE of the sintered joints so as to extend the lifetime and reliability of power electronics device in high temperature applications. In the present paper, we will report a new set of silver sinter pastes containing micro scale non-metal particles, a sintering process, microstructural morphologies, thermo-mechanical reliability of the sintered joint and effect of the contents of non-metal particles on shear strength of the sintered silver joints bonding an Ag silicon die on Ni/Au DBC substrates. Shear tests on the sintered joints with and/or without the low CTE non-metal additives have been conducted at room temperature, 200, 250, and 300°C. Thermo-mechanical reliability of the sintered joints was evaluated by thermal cycling, thermal shock, high temperature storage tests (HTS), respectively. X-ray inspection and scanning electronic microscopy (SEM) were used to characterize void, crack and microstructure morphologies of the sintered joints with and/or without the additives.
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48

Mallik, Aditi, and Roger Stout. "Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS® Finite Element Analysis." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000364–71. http://dx.doi.org/10.4071/isom-2010-wa1-paper3.

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Wafers warp. It is important to minimize warpage in order to achieve optimal die yield and potentially prevent future device failure. Although the word warpage is widely used in the literature to represent wafer bow (convex or concave shape), in the real world wafers are often seen into warp into saddle shapes. This complicates the characterization of both the sources of and solutions to warpage, because (as will be discussed) Stoney's formula (relating intrinsic stress and curvature) does not apply for structures warped with compound curvature, and standard wafer warpage measurements are not designed to measure compound curvature. During thin film deposition, wafer warpage occurs due to the intrinsic stresses and the coefficient of thermal expansion (CTE) mismatch of the different thin films and the substrate. Unfortunately, whereas the introduction of the thermal stresses due to CTE mismatch into a finite element model is easily understood, the introduction of intrinsic stress is not. Further, although a saddle shape is clearly a physically realizable (indeed, often preferred) equilibrium configuration for a circular disk (consistent with an appropriate state of stress), obtaining a saddle shape in a finite element solution turns out to be extremely difficult, as convex or concave shapes may also be stable and numerically preferred. In this paper, a finite element technique (using ANSYS software) to model wafer warpage is presented. Simulations have been done for silicon wafers with aluminum or standard UBM films on top. Saddle-shaped warpage has been successfully modeled, and the aggravating effects of thinning (back side grinding) have been reproduced.
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49

Fraivillig, Jim, Richard Koba, and Kent Hutchings. "Semiconductor-to-metal attachment with silver-filled TPI bondlines." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000064–67. http://dx.doi.org/10.4071/hiten-session2-paper2_4.

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In the attachment of semiconductor chips and submounts to metal heat sinks, bondlines utilizing silver-filled thermoplastic polyimide adhesive (TPI) are very durable across a wide range of environmental conditions (thermal, physical, chemical, radiation). TPI bondlines can withstand an extreme CTE-mismatch between the laminated materials, and have excellent bonding with adhesive-layer thicknesses down to only a few microns. To provide electrical conductivity and enhance thermal conductivity, the TPI bondline can be compounded with a high concentration of silver particles, and retain durability and adhesion. There are two general constructions of silver-filled TPI bondlines:Bondfoil – thin layers of silver-filled B-staged TPI coatings on either side of a metal carrier/substrate. The thickness of the (cured) TPI coatings would be 2–10 μm/side. TPI-priming (B- or C-staged; partially or fully cured) of a semiconductor surface may be required.TPI coating only – thin layers of silver-filled TPI polymer (1–3 μm/surface; B- or C-staged) on the interface surfaces to be bonded. A minimal amount of A-staged TPI (liquid: polymer in solvent) may be added to the bondline construction to optimize surface wetting during lamination.The ultimate in robustness and thinness, silver-filled TPI bondlines can provide:Continuous operation at 350°C, as well as temporary exposure to 450°C. Thermogravimetric analysis (TGA) of the TPI polymer shows that degradation does not start until well above 500°C. [See opposite.]Thermal shock durability -- the CTE-mismatched TPI bondline between silicon and aluminum can survive repeated thermal shocks with a ΔT of 300–400°C.Thermal impedance as low as 0.06 °C-cm2/W (0.01°C-in2/W) when using a silver-filled TPI bondfoil, and about 0.01 °C-cm2/W (0.002°C-in2/W) when using just silver-filled TPI coatings on the interface surfaces (no metal foil). In both constructions, the thermal impedance includes all interface resistances.Shear strength of 10 MPa to an aluminum surface and 1–2 MPa to silicon. These features make TPI bondlines ideal for demanding, CTE-mismatched semiconductor packages. As opposed to cross-linked thermoset bondlines -- which are brittle, especially when highly filled -- thermoplastic polyimide bondlines remain ductile and resist cracking, even when highly stressed.
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50

Bora, Mumtaz Y. "fcLGA Package Assembly Qualification for Mobile Applications." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000115–20. http://dx.doi.org/10.4071/2380-4505-2018.1.000115.

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Abstract Flip Chip Land Grid Array (FcLGA) packages are widely used in Mobile product applications due to their thin form factor and performance. Assembly process qualification requires careful selection of materials and optimization of reflow processes to make consistent and reliable product. The fcLGA typically uses an organic substrate on which the die is reflowed instead of the copper lead frame used in QFN packages. This requires assessment of CTE mismatch and controlled reflow processes to prevent bump separation [1]. The paper reviews the selection of substrate, optimization of assembly process and reliability testing conducted for package qualification
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