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Journal articles on the topic 'Cu dual damascene processes'

Author: Grafiati

Published: 4 June 2021

Last updated: 19 February 2022

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1

Tang, Jian She, Brian J. Brown, Steven Verhaverbeke, Han Wen Chen, Jim Papanu, Raymond Hung, Cathy Cai, and Dennis Yost. "Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow." Solid State Phenomena 103-104 (April 2005): 353–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.353.

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As device features scale down to 90nm and Cu/low-k films are employed for back end interconnects, post etch and ash residue cleaning becomes increasingly challenging due to the higher aspect ratio of the features, tighter CD control requirements, sensitivity of the low-k films, and the requirement for high wet etch selectivity between CuxO and Cu. Traditional solvent based cleaning in wet benches has additional issues such as wafer cross-contamination and high disposal cost [1, 2]. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. The results of physical characterization, process integration electrical data, and process integration reliability data such as electromigration (EM) and stress migration data are presented. The main conclusions can be summarized as follows: (1) The single wafer cleaning process developed on the Oasis™ system can clean post etch residues and simultaneously clean the wafer front side and backside metallic contaminants; (2) In terms CuxO and Cu wet etch selectivity, CD loss control, the Oasis™ aqueous single wafer clean process is superior to the bench solvent cleaning process; (3)The Oasis aqueous cleaning process shows no undercut below etchstop due to the very low Cu etch amount in one cleaning pass, therefore the electromigration and stress migration performance of the aqueous Oasis processed wafers is clearly better than that of the solvent bench processed wafers.

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2

Jung, Chung Kyung, Sung Wook Joo, Sang Wook Ryu, S. Naghshineeh, Yang Lee, and Jae Won Han. "Improved Cleaning Process for Etch Residue Removal in an Advanced Copper/Low-k Device without the Use of DMAC (Dimethylacetamide)." Solid State Phenomena 187 (April 2012): 245–48. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.245.

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Plasma dry etching processes are commonly used to fabricate sidewalls of trenches and vias for copper / low-k dual damascene devices. Typically, some polymers remain in the trench and at the via top and sidewall. Other particulate etch residues are may remained in the bottom and on the sidewalls of vias. Generally, the particulate consists of mixtures of copper oxide with polymers. The polymers on the sidewalls and the particulate residues at the bottom of vias must be removed prior to the next process step. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the etching in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Until now, the industry has relied mainly on organic solvent containing mixtures to clean etch / ash residues from such devices. The effectiveness of available residue removers varies with the specific process and also depends on which new integration materials are used. New materials typically include Cu, TaN, low-k dielectrics and others [1-. Solvent content is thought to aid the removal of polymer residues and particulates produced during plasma dry etching processes. Therefore, in the past we have used a residue remover which contains DMAC (dimethylacetamide). But the use of DMAC is banned in microelectronic fabrication facilities in Europe because of its toxicity. Thus we wanted to find and evaluate a DMAC-free residue remover for removing polymer residues while maintaining high selectivity to the copper and ILD films.

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3

Perng, Dung-Ching, Jia-Feng Fang, and Jhin-Wei Chen. "Single mask dual damascene processes." Microelectronic Engineering 85, no. 3 (March 2008): 599–602. http://dx.doi.org/10.1016/j.mee.2007.11.003.

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4

Ogawa, E. T., Ki-Don Lee, V. A. Blaschke, and P. S. Ho. "Electromigration reliability issues in dual-damascene Cu interconnections." IEEE Transactions on Reliability 51, no. 4 (December 2002): 403–19. http://dx.doi.org/10.1109/tr.2002.804737.

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5

Heo, Jung Shik, Jun Hwan Oh, Hong Jae Shin, and Nae In Lee. "Cu Dendrite Formation in Post Trench Etch Cleaning." Solid State Phenomena 145-146 (January 2009): 331–33. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.331.

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Copper has been widely used as the interconnect material for integrated circuits because of the good electrical conductivity and electron migration resistance. Copper dual damascene structure has been adapted due to the impossibility of etching the copper. For via first dual damascene (VFDD) integration, via is opened after trench etch. Generally, diluted HF cleaning after trench etch is used to remove both etch residues and carbon depletion layer of low-k material. In this study, we investigated the characteristics of copper dendritic formation occurred in post trench etch cleaning with single wafer spin tool (SWST).

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6

Pyun, Jung Woo, Won-Chong Baek, Lijuan Zhang, Jay Im, Paul S. Ho, Larry Smith, and Gregory Smith. "Electromigration behavior of 60 nm dual damascene Cu interconnects." Journal of Applied Physics 102, no. 9 (November 2007): 093516. http://dx.doi.org/10.1063/1.2805425.

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7

Hu, C. K., L. Gignac, E. Liniger, and R. Rosenberg. "Electromigration in On-Chip Single/Dual Damascene Cu Interconnections." Journal of The Electrochemical Society 149, no. 7 (2002): G408. http://dx.doi.org/10.1149/1.1482057.

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8

Kriz, J., C. Angelkort, M. Czekalla, S. Huth, D. Meinhold, A. Pohl, S. Schulte, A. Thamm, and S. Wallace. "Overview of dual damascene integration schemes in Cu BEOL integration." Microelectronic Engineering 85, no. 10 (October 2008): 2128–32. http://dx.doi.org/10.1016/j.mee.2008.05.034.

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9

Oates, A. S., and S. C. Lee. "Electromigration failure distributions of dual damascene Cu /low – k interconnects." Microelectronics Reliability 46, no. 9-11 (September 2006): 1581–86. http://dx.doi.org/10.1016/j.microrel.2006.07.038.

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10

Wu, ZhenYu, YinTang Yang, ChangChun Chai, YueJin Li, JiaYou Wang, Jing Liu, and Bin Liu. "Temperature-dependent stress-induced voiding in dual-damascene Cu interconnects." Microelectronics Reliability 48, no. 4 (April 2008): 578–83. http://dx.doi.org/10.1016/j.microrel.2007.12.001.

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11

Lee, Ki-Don, Ennis T. Ogawa, Hideki Matsuhashi, Patrick R. Justison, Kil-Soo Ko, Paul S. Ho, and Volker A. Blaschke. "Electromigration critical length effect in Cu/oxide dual-damascene interconnects." Applied Physics Letters 79, no. 20 (November 12, 2001): 3236–38. http://dx.doi.org/10.1063/1.1418034.

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12

Lee, K. D., and P. S. Ho. "Statistical Study for Electromigration Reliability in Dual-Damascene Cu Interconnects." IEEE Transactions on Device and Materials Reliability 4, no. 2 (June 2004): 237–45. http://dx.doi.org/10.1109/tdmr.2004.827679.

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13

Ogawa, Ennis T., Ki-Don Lee, Hideki Matsuhashi, Paul S. Ho, Volker A. Blaschke, and Robert H. Havemann. "Reliability and early failure in Cu/oxide dual-damascene interconnects." Journal of Electronic Materials 31, no. 10 (October 2002): 1052–58. http://dx.doi.org/10.1007/s11664-002-0042-6.

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14

Fayolle, M., J. Torres, G. Passemard, F. Fusalba, G. Fanget, D. Louis, M. Assous, et al. "Integration of Cu/SiOC in Cu dual damascene interconnect for 0.1-μm technology." Microelectronic Engineering 64, no. 1-4 (October 2002): 35–42. http://dx.doi.org/10.1016/s0167-9317(02)00769-4.

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15

Vairagar, A. V., S. G. Mhaisalkar, M. A. Meyer, E. Zschech, and Ahila Krishnamoorthy. "Reservoir effect on electromigration mechanisms in dual-damascene Cu interconnect structures." Microelectronic Engineering 82, no. 3-4 (December 2005): 675–79. http://dx.doi.org/10.1016/j.mee.2005.07.076.

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16

Hu, C.-K., L. Gignac, S. G. Malhotra, R. Rosenberg, and S. Boettcher. "Mechanisms for very long electromigration lifetime in dual-damascene Cu interconnections." Applied Physics Letters 78, no. 7 (February 12, 2001): 904–6. http://dx.doi.org/10.1063/1.1347400.

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17

Lee, Ki-Don, Ennis T. Ogawa, Sean Yoon, Xia Lu, and Paul S. Ho. "Electromigration reliability of dual-damascene Cu/porous methylsilsesquioxane low k interconnects." Applied Physics Letters 82, no. 13 (March 31, 2003): 2032–34. http://dx.doi.org/10.1063/1.1564294.

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18

Gotkis, Y., and S. Guha. "Cu-CMP for dual damascene technology: Prestonian vs. non-prestonian regimes of Cu removal." Journal of Electronic Materials 30, no. 4 (April 2001): 396–99. http://dx.doi.org/10.1007/s11664-001-0050-y.

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19

Nagahara, Seiji, Masashi Fujimoto, Mitsuharu Yamana, Susumu Watanabe, Kazutoshi Shiba, and Makoto Tominaga. "Elimination of Resist Poisoning in Via-First Dual Damascene Processes." Journal of Photopolymer Science and Technology 16, no. 3 (2003): 351–61. http://dx.doi.org/10.2494/photopolymer.16.351.

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20

Lau, J., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, et al. "Redistribution Layers (RDLs) for 2.5D/3D IC Integration." Journal of Microelectronics and Electronic Packaging 11, no. 1 (January 1, 2014): 16–24. http://dx.doi.org/10.4071/imaps.406.

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Redistribution layer (RDL) is an integral part of 3D IC integration, especially for 2.5D IC integration with a passive interposer. The RDL allows for circuitry fan-outs of and allows for lateral communication between the chips attached to the interposer. There are at least two ways to fabricate the RDL, namely (1) polymers to make the passivation and Cu-plating to make the metal layer, and (2) semiconductor back-end-of-line Cu damascene. In this study, the materials and processes of these methods are presented. Emphasis is placed on the Cu damascene method.

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21

Lau, J., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, K. Saito, et al. "Redistribution Layers (RDLs) for 2.5D/3D IC Integration." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000434–41. http://dx.doi.org/10.4071/isom-2013-wa12.

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Redistribution layer (RDL) is an integral part of 3D IC integration, especially for 2.5D IC integration with a passive interposer. The RDL allows for fans out of the circuitries and allows the lateral communication between the chips attached to the interposer. There are at least two ways to fabricate the RDL, namely (a) polymers to make the passivation and Cu-plating to make the metal layer, and (b) semiconductor back-end-of-line Cu damascene. In this study, the materials and processes of these methods are presented. Emphasis is placed on the Cu damascene method.

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22

Maestre Caro, A., Y. Travaly, G. Beyer, Z. Tokei, G. Maes, G. Borghs, and S. Armini. "Selective self-assembled monolayer coating to enable Cu-to-Cu connection in dual damascene vias." Microelectronic Engineering 106 (June 2013): 76–80. http://dx.doi.org/10.1016/j.mee.2012.12.028.

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23

Vairagar, A. V., S. G. Mhaisalkar, and Ahila Krishnamoorthy. "Electromigration behavior of dual-damascene Cu interconnects––Structure, width, and length dependences." Microelectronics Reliability 44, no. 5 (May 2004): 747–54. http://dx.doi.org/10.1016/j.microrel.2003.12.011.

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24

Li, H. Y., Y. J. Su, C. F. Tsang, S. M. Sohan, V. Bliznetsov, and L. Zhang. "Process improvement of 0.13μm Cu/Low K (Black DiamondTM) dual damascene interconnection." Microelectronics Reliability 45, no. 7-8 (July 2005): 1134–43. http://dx.doi.org/10.1016/j.microrel.2004.11.057.

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25

Nagaishi, H., M. Fukui, H. Asakura, and A. Sugimoto. "Defect reduction in Cu dual damascene process using short-loop test structures." IEEE Transactions on Semiconductor Manufacturing 16, no. 3 (August 2003): 446–51. http://dx.doi.org/10.1109/tsm.2003.815622.

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26

Ueki, M., M. Hiroi, N. Ikarashi, T. Onodera, N. Furutake, N. Inoue, and Y. Hayashi. "Effects of Ti Addition on Via Reliability in Cu Dual Damascene Interconnects." IEEE Transactions on Electron Devices 51, no. 11 (November 2004): 1883–91. http://dx.doi.org/10.1109/ted.2004.837579.

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27

Jiang, P., F. G. Celii, W. W. Dostalik, K. J. Newton, and H. Sakima. "Trench etch processes for dual damascene patterning of low-k dielectrics." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 19, no. 4 (July 2001): 1388–91. http://dx.doi.org/10.1116/1.1380717.

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28

Lee, Soo Geun, Yun Jun Kim, Seung Pae Lee, Hyeok-Sang Oh, Seung Jae Lee, Min Kim, Il-Goo Kim, et al. "Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process." Japanese Journal of Applied Physics 40, Part 1, No. 4B (April 30, 2001): 2663–68. http://dx.doi.org/10.1143/jjap.40.2663.

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29

Yan, M. Y., K. N. Tu, A. V. Vairagar, S. G. Mhaisalkar, and Ahila Krishnamoorthy. "A direct measurement of electromigration induced drift velocity in Cu dual damascene interconnects." Microelectronics Reliability 46, no. 8 (August 2006): 1392–95. http://dx.doi.org/10.1016/j.microrel.2005.11.004.

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30

Motte, P., J. Torres, J. Palleau, F. Tardif, O. Demolliens, and H. Bernard. "Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture." Microelectronic Engineering 50, no. 1-4 (January 2000): 487–93. http://dx.doi.org/10.1016/s0167-9317(99)00319-6.

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31

Vairagar, A. V., S. G. Mhaisalkar, M. A. Meyer, E. Zschech, Ahila Krishnamoorthy, K. N. Tu, and A. M. Gusak. "Direct evidence of electromigration failure mechanism in dual-damascene Cu interconnect tree structures." Applied Physics Letters 87, no. 8 (August 22, 2005): 081909. http://dx.doi.org/10.1063/1.2033136.

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32

Usui, Takamasa, Tadayoshi Watanabe, Masaaki Hatano, Sachiyo Ito, Junichi Wada, and Hisashi Kaneko. "Electromigration of Al-0.5 wt%Cu with Nb-Based Liner Dual Damascene Interconnects." Japanese Journal of Applied Physics 43, no. 10 (October 8, 2004): 6957–62. http://dx.doi.org/10.1143/jjap.43.6957.

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33

Vairagar, A. V., Zhenghao Gan, Wei Shao, S. G. Mhaisalkar, Hongyu Li, K. N. Tu, Zhong Chen, E. Zschech, H. J. Engelmann, and Sam Zhang. "Improvement of Electromigration Lifetime of Submicrometer Dual-Damascene Cu Interconnects Through Surface Engineering." Journal of The Electrochemical Society 153, no. 9 (2006): G840. http://dx.doi.org/10.1149/1.2217267.

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34

Yan, M. Y., J. O. Suh, F. Ren, K. N. Tu, A. V. Vairagar, S. G. Mhaisalkar, and Ahila Krishnamoorthy. "Effect of Cu3Sn coatings on electromigration lifetime improvement of Cu dual-damascene interconnects." Applied Physics Letters 87, no. 21 (November 21, 2005): 211103. http://dx.doi.org/10.1063/1.2132536.

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35

Ogawa, Ennis T., Alexander J. Bierwag, Ki-Don Lee, Hideki Matsuhashi, Patrick R. Justison, Anup N. Ramamurthi, Paul S. Ho, et al. "Direct observation of a critical length effect in dual-damascene Cu/oxide interconnects." Applied Physics Letters 78, no. 18 (April 30, 2001): 2652–54. http://dx.doi.org/10.1063/1.1365414.

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36

Vairagar, A. V., S. G. Mhaisalkar, Ahila Krishnamoorthy, K. N. Tu, A. M. Gusak, Moritz Andreas Meyer, and Ehrenfried Zschech. "In situobservation of electromigration-induced void migration in dual-damascene Cu interconnect structures." Applied Physics Letters 85, no. 13 (September 27, 2004): 2502–4. http://dx.doi.org/10.1063/1.1795978.

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37

Furusawa, Takeshi, Shuntaro Machida, Daisuke Ryuzaki, Kenji Sameshima, Takeshi Ishida, Kensuke Ishikawa, Noriko Miura, Nobuhiro Konishi, Tatsuyuki Saito, and Hizuru Yamaguchi. "Dual-Damascene Cu/Low-k Interconnect Fabrication Scheme Using Dissoluble Hard Mask Material." Journal of The Electrochemical Society 153, no. 2 (2006): G160. http://dx.doi.org/10.1149/1.2149297.

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38

Rossnagel, S. M. "Filling dual damascene interconnect structures with AlCu and Cu using ionized magnetron deposition." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 13, no. 1 (January 1995): 125. http://dx.doi.org/10.1116/1.588004.

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39

Weng, C. J. "Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration." Strain 45, no. 3 (June 2009): 221–31. http://dx.doi.org/10.1111/j.1475-1305.2009.00599.x.

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40

Shao, W., S. G. Mhaisalkar, T. Sritharan, A. V. Vairagar, H. J. Engelmann, O. Aubel, E. Zschech, A. M. Gusak, and K. N. Tu. "Direct evidence of Cu/cap/liner edge being the dominant electromigration path in dual damascene Cu interconnects." Applied Physics Letters 90, no. 5 (January 29, 2007): 052106. http://dx.doi.org/10.1063/1.2437689.

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41

Motoyama, K., O. van der Straten, J. Maniscalco, and M. He. "PVD Cu Reflow Seed Process Optimization for Defect Reduction in Nanoscale Cu/Low-k Dual Damascene Interconnects." Journal of The Electrochemical Society 160, no. 12 (2013): D3211—D3215. http://dx.doi.org/10.1149/2.035312jes.

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42

Pipia, Francesco, Annamaria Votta, Alice C. Elbaz, Salvo Grasso, Enrica Ravizza, Simona Spadoni, and Mauro Alessandri. "Cu Surface Characterization after Wet Cleaning Processes." Solid State Phenomena 145-146 (January 2009): 371–75. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.371.

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In damascene architecture, widely used both in flash memories and in DRAM as interconnect scheme since 90 nm node, copper surface is exposed after via etch. A deep understanding of the effect of different wet cleanings on Cu surface is therefore mandatory, not only to ensure an efficient post etch polymer removal, but also to provide a better surface termination, capable to minimize Cu oxidation kinetic and to reduce the growth of Cu-rich precipitates which may negatively effect contact resistance. In this work we have analyzed the Cu surface after processing with several cleaning chemistries -often present in BEOL cleaning processes- using XPS (X-ray Photoelectron Spectroscopy) and ToF-SIMS (Time of Flight – Secondary Ion Mass Spectroscopy), fast and powerful techniques widely used in Cu surface characterization [1]. In addition, the evolution of the surface with storage time has been monitored using the same techniques, in order to better understand the effect of the different cleaning chemistries. XPS has been proven to be very sensitive to monitor Cu oxidation, while ToF-SIMS has been used to reveal organic species adsorbed on the surface.

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43

Shao, W., Z. H. Gan, S. G. Mhaisalkar, Zhong Chen, and Hongyu Li. "The effect of line width on stress-induced voiding in Cu dual damascene interconnects." Thin Solid Films 504, no. 1-2 (May 2006): 298–301. http://dx.doi.org/10.1016/j.tsf.2005.09.064.

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44

Gignac, L. M., C. K. Hu, and E. G. Liniger. "Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects." Microelectronic Engineering 70, no. 2-4 (November 2003): 398–405. http://dx.doi.org/10.1016/s0167-9317(03)00284-3.

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45

Ueki, Makoto, Munehiro Tada, Masayoshi Tagami, Mitsuru Narihiro, Fuminori Ito, and Yoshihiro Hayashi. "A Robust Low-$k$/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)." IEEE Transactions on Device and Materials Reliability 11, no. 1 (March 2011): 98–105. http://dx.doi.org/10.1109/tdmr.2011.2106130.

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46

Bana, F., L. Arnaud, D. Ney, and Y. Wouters. "Investigation on the multi-voids formation during electromigration degradation in dual damascene Cu lines." Microelectronic Engineering 112 (December 2013): 130–32. http://dx.doi.org/10.1016/j.mee.2012.11.028.

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47

Kabansky, A., S. S. H. Tan, E. A. Hudson, G. Delgadino, L. Gancs, and J. Marks. "Effective Defect Control in TiN Metal Hard Mask Cu/Low-k Dual Damascene Process." ECS Transactions 58, no. 6 (August 31, 2013): 143–50. http://dx.doi.org/10.1149/05806.0143ecst.

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48

Tagami, Masayoshi, and Yoshihiro Hayashi. "Thermal Stress Control in Cu Dual Damascene Interconnects with Low-k Organic Polymer Film." Journal of The Electrochemical Society 157, no. 12 (2010): H1071. http://dx.doi.org/10.1149/1.3486808.

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49

Izumitani, Junko, Daisuke Kodama, Shigenori Kido, Hiroyuki Chibahara, Yoshihiro Oka, Kinya Goto, Naohito Suzumura, Masahiko Fujisawa, and Hiroshi Miyatake. "Cu Dual-Damascene Interconnects with Direct Chemical Mechanical Polishing Process on Porous Low-kFilm." Japanese Journal of Applied Physics 49, no. 5 (May 20, 2010): 05FC02. http://dx.doi.org/10.1143/jjap.49.05fc02.

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50

Lee, Sang-Yun, Yong-Bae Kim, and Jeong Soo Byun. "Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process." Journal of The Electrochemical Society 150, no. 1 (2003): G58. http://dx.doi.org/10.1149/1.1528944.

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