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Mylonas, Georgios. "Programmable voltage reference generator for a SAR-ADC." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-98567.
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SAR-ADCs are very popular and suitable for conversions up to few tens of MHz with 8 to 12 bits of resolution. A very popular type is the Charge Redistribution SAR-ADC which is based on a capacitive array. Higher speeds can be achieved by using the interleaving technique where a number of SAR-ADCs are working in parallel. These speeds, however, can only be achieved if the reference voltage can cope with the switching of the capacitive array. In this thesis the design of a programmable voltage reference generator for a Charge Redistribution SAR-ADC was studied. A number of architectures were studied and one based on a Current Steering DAC was chosen because of the settling time that could offer to the Charge Redistribution SAR-ADC switching operation. This architecture was further investigated in order to spot the weak points of the design and try to minimize the settling time. In the end, the final design was evaluated and possible trimming techniques were proposed that could further speed up the design.
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Mudroch, Michal. "Návrh nízkonapěťového napájecího a referenčního bloku založeného na teplotně stabilní napěťové referenci." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399479.
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In this diploma thesis there is elaborated design of low-voltage power supply block using I3T25 technology. The theoretical part describes the basic structures used in the design, using CMOS and bipolar devices. Furthermore, the properties and the analysis used in the evaluation are described. In the design part there is an elaborated design of individual parts, including voltage references, current references, DAC converter, operational amplifier. In the last part, the power supply block is subjected to simulations for verification of temperature compensated output variables and analyzed circuit functionality.
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Skalický, Pavel. "Referenční zdroje napětí a proudu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219331.
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The topic of the master´s thesis are voltage and current reference sources. There is detailed description of current and voltage references, which are basic building blocks of many analog circuits, in the theoretical part. Next part of the master´s thesis is the design of a voltage reference source, the design of a voltage reference generating two voltages and a current reference source. The correct function of all circuits have been verified using simulations, especially dependence of the output voltage or current on supply voltage or dependence of the output voltage or current when the ambient temperature is changed.
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Digvadekar, Ashish A. "A sub 1 V bandgap reference circuit /." Online version of thesis, 2005. https://ritdml.rit.edu/dspace/handle/1850/2595.
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Toledo, Pedro Filipe Leite Correia de. "Modelamento e análise do efeito de coeficiente nulo de temperatura (ZTC) do Mosfet para aplicações análogicas de baixa sensibilidade têrmica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/140814.
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A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C.<br>Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.
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Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.
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The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.
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Mácha, Petr. "Návrh převodníku DA s plně diferenčním výstupem v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316964.
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This diploma thesis deals with the design of eight-bit digital to analog coverter with fully differential outputs in technology I3T25 of ON Semiconductor company. The work contains the description of basic structures and characteristics of digital to analog converters. The main focus of the work is to design a converter and auxiliary circuits at the transistor level. The functionality of designed circuits is verified by simulation environment Cadence.
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Miri, Lavasani Seyed Hossein. "Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41096.
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Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible.
Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy.
The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.
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Štibraný, Miroslav. "Řízený laboratorní zdroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-240809.
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Master’s thesis deals with design of laboratory supply with precise voltage and current measuring. At the beginning it presents properties, advantages and disadvantages of linear and switching supplies, based on these facts it chooses a linear type of regulator. The design continues with detailed description of power and control analog and digital circuits. The thesis includes description of taking control over the supply from the front panel or through computer. The last part is devoted to measurement results and to presentation of some static and dynamic parameters of the designed supply.
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El, Dbib Issa. "Low Voltage Current Conveyor Design Techniques." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-233421.
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Disertační práce se zabývá proudovými konvejery CCII v proudovém modu s nízkým napájecím napětím. Potřeba velké rychlosti, vysokého výkonu a nízkého napájecího napětí pro mobilní elektroniku a komunikační systémy a potíže se současným stavem tlačí analogové návrháře k nalezení obvodové architektury a nové nízkopříkonové techniky. Je zde podrobně rozebrána technika složené kaskody a substrátu řízeného tranzistoru, která pomáhá produkci nízkopříkonových nízkovoltových obvodů. Dále jsou rozebrány a diskutovány základní funkční bloky, jako jsou proudová zrcadla, diferenční zesilovače a další, schopné pracovat při nízkých napájecích napětích. Jádrem práce je návrh konvejerů typu CCII s nízkým napájecím napětím. Jsou rozebrány jejich výhody a srovnání s konvenčními obvody. Princip a implementace operačního zesilovače založeného na proudovém konvejeru CCII je v práci navržen a popsán.
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Zhang, Yushu. "Multilevel voltage source converters in high voltage direct current transmission systems." Thesis, University of Strathclyde, 2012. http://oleg.lib.strath.ac.uk:80/R/?func=dbin-jump-full&object_id=25814.
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This research focuses on voltage source multilevel converters in high voltage direct current (HVDC) transmission systems. The first Voltage Source Converter based HVDC (VSC-HVDC) systems with series connected IGBTs in a two-level converter represented a solution to meet industrial and economical requirements but is associated with significant drawbacks such as high dv/dt and di/dt, high switching loss, and poor output voltage and current quality. To overcome these issues, the multilevel converter was proposed for HVDC application. The Modular Multilevel Converter (M2C) was the first multilevel converter to be commercially used in the power industry. In this thesis, the M2C is investigated mainly in terms of operating principle, capacitor size and capacitor voltage ripple, capacitor voltage balancing technique and modulation scheme. The results of this investigation show that the M2C offers the following features: improved efficiency, lower supporting voltage and current in the switching devices and low dv/dt. These features make the M2C suitable for HVDC systems. Two new operational principles and modulation strategies for a Hybrid Cascaded Multilevel Converter (HCMC) are proposed in this thesis. Both modulation schemes extend the modulation index linear range and improve the output waveform quality. This gives the HCMC a higher power density than any known multilevel converter topology for the same dc link voltage and switching device rating. Simulations for both types of multilevel converter (M2C and HCMC) are supported by practical results from scaled hardware laboratory converters. Mathematical analysis and calculation of conversion loss for both types of multilevel converter and for the conventional two-level converter are performed. It is shown that both M2C and HCMC provide lower conversion loss compare to the conventional two-level converter. A control strategy for these two multilevel converters in point-to-point and multi-terminal HVDC systems is also studied. Simulation results show that these two converters are able to operate over the entire specified P-Q capability curve and are capable of riding through ac faults without imposing any over-voltage or over-current on the converter switches.
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Holman, William Timothy. "A low noise CMOS voltage reference." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.
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Mai, Yuan Yen. "Current-mode DC-DC buck converter with current-voltage feedforward control /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20MAI.
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Balasubramaniam, Senthooran. "Series current flow controllers for high voltage direct current transmission grids." Thesis, Cardiff University, 2017. http://orca.cf.ac.uk/104744/.
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Large scale grid integration of renewables and cross country border energy exchange may be facilitated by multi-terminal high-voltage direct-current (MTdc) grids. However, as the number of terminals and dc lines increases, power flow management between dc nodes becomes amajor challenge. The current carrying capability of dc lines is limited by their thermal and electric stress limits. Thus, the line current must be maintained within the permissible operational region to protect the lines fromdamages. This thesis addresses this fundamental issue through the introduction of inter-line current flow controllers (CFCs) into MTdc grids. An inter-line CFC is a low power rated controllable voltage source that can enhance system performance by suitably redirecting the current flow at the point of connection. It enables regulation of the dc line current flow by changing the voltage at the dc terminals where it is inserted. The research work presented in this thesis is aimed to realise the most feasible CFC topologies to facilitate flexible power flow between dc nodes. Themain contributions of this research work comprise of four parts, namely, (1) design and development of dc CFC topologies, (2) prototyping of the proposed CFCs (3) implementations of centralised and communication free control schemes for densely meshed dc grids, and (4) protection of inter-line CFCs. In the first phase, the characteristics, control and operation for five configurations of interline CFCs are studied, namely, resistive, RC circuit, capacitive, dual H-bridge, and single H-bridge based CFCs. A multi-port CFC is proposed to facilitate current regulation on multiple lines simultaneously. An experimental platform consisting of a three-terminal dc grid and small scale prototypes of the proposed CFCs have been developed to validate the concepts. It is clearly shown through experiments and time-domain simulations that all devices are capable of improving the system performance. A centralised hierarchical control system is proposed to coordinate the operation between multiple CFCs. A novel voltage sharing control scheme is demonstrated. It is shown that such ii Abstract scheme reduces the workload on a single CFC by sharing the required control voltage between multiple CFCs, and, additionally, can be used to avoid control conflicts among active CFCs during communication failure. New protection methodologies are implemented to protect the CFC during internal failures and dc faults. Small-scale dc circuit breakers have been developed to study the performances of 1B and 2B-CFCs under a pole-to-pole fault.
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Zhou, Jinghai. "High Frequency, High Current Density Voltage Regulators." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/27268.
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As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitorsâ number appears to be unrealistically large if we follow todayâ s approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency.
A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications.
Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer.
The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz.
All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction.<br>Ph. D.
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Hölling, Matthias. "Adaptive current and voltage measurement device for low voltage distribution in power nets /." [S.l.] : [s.n.], 2000. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13985.
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Rincon-Mora, Gabriel Alfonso. "Current efficient, low voltage, low drop-out regulators." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/13359.
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Dixon, Juan W. (Juan Walterio). "A DC voltage regulated, controlled current PWM rectifier /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65923.
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Moselle, Dagmara W. "A double-pole high voltage high current switch." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Dec%5FMoselle.pdf.
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Boudjelthia, H. "Corona suppression on high voltage direct current systems." Thesis, University of Southampton, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.235291.
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Baylis, Charles Passant. "Improved current-voltage methods for RF transistor characterization." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000249.
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Lochner, Georg Philip. "The voltage-current characteristic of the human skin." Pretoria : [s.n.], 2005. http://upetd.up.ac.za/thesis/available/etd-09212005-093111/.
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Baylis, Charles Passant II. "Improved Current-Voltage Methods for RF Transistor Characterization." Scholar Commons, 2004. https://scholarcommons.usf.edu/etd/950.
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In the development of a nonlinear transistor model, several measurements are used to extract equivalent circuit parameters. The current-voltage (IV) characteristic of a transistor is one of the measurement data sets that allows the nonlinear model parameters to be extracted. The accuracy of the IV measurement greatly influences the accuracy of the large-signal model.
Numerous works have reported the inadequacy of traditional static DC IV measurements to accurately predict radio-frequency (RF) behavior for many devices. This inaccuracy results from slow processes in the device that do not have time to completely respond to the quick changes in terminal conditions when the device is operating at high frequencies; however, these slow processes respond fully to reach a new steady-state condition in the DC sweep measurement. The two dominant processes are self-heating of the device and changes in trap occupancy. One method of allowing the thermal and trap conditions to remain in a state comparable to that of RF operation is to perform pulsed IV measurements to obtain the IV curves. In addition, thermal correction can be used to adjust the IV curves to compensate for self-heating in the case that the predominant effect in the device is thermal.
To gain a better understanding of pulsed IV measurement techniques, measurement waveforms of a commercially available pulsed IV analyzer are examined in the time domain. In addition, the use of bias tees with pulsed IV measurement is explored; such a setup may be desired to maintain stability or to enable simultaneous pulsed S-parameter and pulsed IV measurement. In measurements with bias tees, the pulse length setting must be long enough to allow the voltage across the inductor to change before the measurement is made.
In many circumstances, it is beneficial to compare different sets of IV curves for a device. The comparison of pulsed and static IV measurements, measured and modeled IV measurements, as well as two measurements with identical settings on the same instrument (to ascertain instrument repeatability) can be performed using the proposed normalized difference unit (NDU). This unit provides a comparison that equally weights the two sets of data to be compared. Due to the normalization factor used, the value of the NDU is independent of the size of the device for which the IV curves are compared. The variety of comparisons for which this unit can be used and its ability to present differences quantitatively allow it to be used as a robust metric for comparing IV curves. Examples of the use of the NDU shown include determination of measurement repeatability, comparison of pulsed and static IV data, and a comparison of model fits.
The NDU can also be used to isolate thermal and trapping processes and to give the maximum pulse length that can be used for pulsed IV measurement without contamination by each of these processes. Plotting the NDU comparing static and pulsed IV data versus pulse length shows this maximum pulse length that can be used for each effect, while a plot of the NDU comparing pulsed IV data for two quiescent bias points of equal power dissipation reveals only differences due to trapping effects. In this way, trapping effects can be distinguished from thermal effects.
Electrothermal modeling has arisen as a method of correcting for self-heating processes in a device with predominantly thermal effects. A parallel RC circuit is used to model channel temperature as a function of ambient temperature and power dissipated in the channel or junction. A technique is proposed for thermal resistance measurement and compared with a technique found in the literature. It is demonstrated that the thermal time constant can be measured from a plot of the NDU versus pulse length, and the thermal capacitance is then obtained using the thermal resistance and time constant.
Finally, the results obtained through the thermal resistance measurement procedures are used to thermally correct static IV curves. Because trapping effects are negligible, it is shown that IV curves corresponding to different quiescent bias points for a Si LDMOSFET can be synthesized from three sets of static IV data taken at different ambient temperatures. The results obtained from this correction process for two quiescent bias points are compared to the pulsed IV results for these quiescent bias points and found to be quite accurate.
Use of the methods presented in this work for obtaining more accurate transistor IV data data should assist in allowing more accurate nonlinear models to be obtained.
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McClusky, Scott Logan. "HIGH VOLTAGE RESONANT SELF-TRACKING CURRENT-FED CONVERTER." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/254.
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High voltage power supply design presents unique requirements, combining safety, controllability, high performance, and high efficiencies. A new Resonant Self-Tracking Current-Fed Converter (RST-CFC) is investigated as a proof-of-concept of a high voltage power supply particularly for an X-ray system. These systems require fast voltage rise times and low ripple to yield a clear image.
The proposed converter implements high-frequency resonance among discrete components and transformer parasitics to achieve high voltage gain, and the self-tracking nature ensures operation at maximum gain while power switches achieve zero-voltage switching across the full load range. This converter exhibits an inherent indefinite short-circuit capability. Theoretical results were obtained through simulations and verified by experimental results through a complete test configuration. Converter topology viability was confirmed through hardware testing and characterization.
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Naude, Neil. "Differential current sensor linearisation in low-voltage CMOS." Diss., University of Pretoria, 2017. http://hdl.handle.net/2263/62785.
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The viability of low cost, distributed, and autonomous wireless sensor networks is determined by the affordability of the integration and operation of each sensor node. Self-sufficient nodes which harvest energy from the local environment decrease operating and maintenance costs over extended periods of time. This affordability can be achieved by increasing the power usage efficiency of designs implemented in an older and cheaper CMOS process. This circumvents the use of a more compact technology node which trades increased efficiency for cost. The efficiency of power conversion is determined by topology, component quality, control scheme, and internal measurement accuracy. This research focuses on improving internal measurement during the power conversion process, in order to reduce conversion loss from the internal control error. A current sensing integrated circuit was proposed which is insensitive to dominant process characteristics which degrade the performance of other sensing solutions. In particular, the detrimental effect of channel length modulation is compensated for. This compensation is achieved by decoupling the sensor biasing and differential steering pair from being influenced by the external current being measured. Widely used solutions were studied and analysed in the context of implementation in a low cost and low-voltage CMOS process. Key process characteristics which negatively influenced these solutions were identified and formed the basis of developing an improved integrated current sensor. Current research in the literature is tightly focused on improved accuracy without the constraints of process costs, low operating voltage (800mV – 1.2 V), and prevalent second order effects of device operation. A study of the literature on CMOS-based integrated current sensing demonstrates a common goal towards improving sensor accuracy by developing either new topologies or augmenting known topologies. New and augmented topologies focus on novel analogue networks which aim to improve the linearity of CMOS based current sensing. The colloquially named SenseFET circuit is a foundation for many variations of integrated current sensor. This integrated circuit generates an estimate of the current flowing into a DC-DC boost-buck converter by sampling the current sourced into the converters inductor. The low maximum operating voltage of the chosen CMOS process restricts the application of typical published solutions. The sensitivity of other solutions to second order effects limits application as well. The proposed solution is based on such a sampling topology with a focus on achieving linearity in a process with pronounced channel-length modulation effects as well as a relatively low operating voltage. The goal of the improved design is to test if linearity can be improved by developing a circuit which is robust towards second-order process effects. Discreet and integrated boost-buck converters were studied and analysed to form the basis of further sensor developments. An integrated non-inverting converter topology suitable for single rail operation was identified and designed as the system environment for which an integrated sensor would be developed. This would allow for comparison of sensor designs in a known environment, both in simulation and in prototyping of the integrated system. The proposed integrated current sensor was developed analytically before being simulated both mathematically and at transistor gate level. This iterative process was applied to a known design as a performance baseline and to demonstrate the improvements achieved.<br>Dissertation (MEng)--University of Pretoria, 2017.<br>Electrical, Electronic and Computer Engineering<br>MEng<br>Unrestricted
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Ma, Shuhan. "Load-current response to severe changes of voltage." Thesis, KTH, Elektroteknisk teori och konstruktion, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-203894.
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Electric loads, such as computers, lamps, refrigerators and heaters connected to low-voltage distributionsystems in homes and offices differ widely in how their current responds to changes in the applied voltage.These voltage changes could be a total collapse of the voltage, a weak or strong reduction of amplitude,or a sudden phase-shift.This thesis investigates the currents into some modern power-electronic interfaced loads, at sub-cycletimescales, in response to sudden changes of AC voltage magnitude. One reason for this interest was anearlier project about fault-location methods in which the necessary level of modeling of loads wasquestioned [1]. A related issue that is also investigated is the response of such loads when Wye-connectedin a three-phase system with a high-impedance neutral such as a broken conductor.Several related matters have been studied a lot in other work. For example, active and reactive powerconsumptions of loads can change in response to the variation of voltage magnitude and frequency.Studies of power system oscillations, and angle and voltage stability, typically make use of such models.At distribution level, the relation of power consumption of loads to the feeder voltage has been includedin studies of Conservation Voltage Reduction (CVR). In these examples, the variation of voltage is typicallysmall, and the result is a value that summarizes an entire cycle (active or reactive power) without givinginformation about the current’s faster changes. Studies of voltage dip tolerance have instead workedwith larger changes of voltage, and short and variable durations, but without the resulting current beingthe interest.This thesis starts with a literature survey about different types of modern loads with differentcharacteristics, especially electronic loads which have become a far greater proportion of the totaldistribution-system load over the past several decades. It is known that the number of the electronicdevices has increased significantly due to the boom in the consumer electronic market. The most commonexamples of these loads include: computers, monitors, TVs and DVD players. Based on a survey of loadbehaviors and models, the current response of these loads to the voltage dips or recoveries are modeledby circuit simulation. Measurements of the currents into some computer equipment were performedwith voltage dips and recoveries, and compared to the results from models. The voltage amplitude dropsto 25%, 50% or 75% of its original value, and recovers afterwards. The current response is studied, focusingmainly during a short time period up to a few AC cycles. A similar mixture of simulation and measurementis then used to study the situation of the potential that arises at the neutral point of a three-phaseconnected electronic load when the neutral conductor has a high resistance.<br>Elektriska laster i hem och kontor, såsom datorer, lampor, kylskåp och värmare, anslutna tilllågspänningsdistributionsnätet, varierar kraftigt i hur deras strömmar reagerar till förändringar ispänningen, vilka kan exempelvis vara en svag eller stark minskning av spänningsamplituden eller enplötslig fasförskjutning.Denna avhandling undersöker strömmarna i vissa moderna slags laster, vilka har effektelektroniskgränsnitt mellan nätet och effektförbrukningen. Strömmarna betraktas även på tidsskalor mindre än enperiod av nätfrekvensen. En anledning till intresset var ett tidigare projekt om fellokaliseringsmetodersom ifrågasatte den nödvändiga nivån av lastmodellering [1]. En relaterad fråga som också utreds ärbeteendet av sådana laster när de är Y-anslutna i ett tre-fas system med hög impedans i nolledaren.Flera aspekter av lastmodellering har studerats i tidigare arbete. Aktiv och reaktiv strömförbrukning avlaster som konsekvens av spänningsamplitud och frekvensen har studerats för modellering av elsystemetssvängningar samt vinkel- och spänningsstabilitet. I distributionsnätet har förhållandet mellan lastersströmförbrukning spänningsamplituden inkluderats i studier av ”CVR” (conservation voltage reduction). Idessa exempel är variationen av spänningen vanligtvis små och resultatet är ett värde som sammanfattaren hel cykel (aktiv eller reaktiv effekt) utan att ge information om snabbare förändringar. Studier avtolerans av laster till spänningssjunkningar har istället arbetat med större ändringar av spänning och kortoch variabel varaktigheter, men utan att ta intresse på den resulterande strömmen.Avhandlingen inleds med en litteraturstudie om olika typer av moderna laster med olika egenskaper,särskilt elektroniska laster som har blivit en mycket större andel av distributionnätets belastning under desenaste decennierna. Antalet elektroniska enheter har ökat betydligt: vanliga exempel av sådana laster ärdatorer, bildskärmar, TV och DVD-spelare. Baserat på litteratur om sådana laster och deras modeller, harresponsen av dessa laster till spänningssjunkningar eller återställningar modelleras genomkretssimuleringar. Mätningar har också utförts, av strömmarna i några datorutrustningar, vid spänningarsom sjunker med 25%, 50% eller 75% av det ursprungliga värdet och återställs efteråt. Dessa mätningarjämförs med resultaten från modellerna. Tidsramen av intresse är från millisekunder upp till någraperioder av nätfrekvensen. En liknande kombination av simulering och mätning har också använts för attstudera situationen där faror kan uppstå vid bruten nolledare i ett trefassystem.
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Abu-Shahla, Osama Khader Hamed. "On-line self-testing of switched-current circuits and voltage-to-current converters." Thesis, University of Hull, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301474.
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Raczkowycz, Julian. "Monolithic data converters and integrated voltage reference sources." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.290740.
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Holmgren, Jens. "Investigation of alternative current measurements in high-voltage applications." Thesis, Linköping University, Department of Science and Technology, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8149.
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<p>ABB:s MACH2 system uses a number of currents to ignite thyristors for AC/DC-trassfformation and they are measured for control and protection. The measurement methods used today has major drawbacks. Two alternative techniques are investigated, one based on the Hall-Effect (HED) and the other based on Anisotropic Magnetoreistanse (AMR), both techniques sensing the magnetic field produced by currents in a conductor. The HED hawe low sensitivity so some kind of flux concentrators is needed. This adds volume, costs and complexity to the device. The AMR technique is much more sensitive than the HED. Unfortunately AMR are also much more sensitive for high over currents that may damage the devise, and they are not as common on te market. By testing linearity, step response and frequency dependency for some components, my conclusion is that HED components with toroidal flux concentrators utilizing magnetic feedback (Closed Loop, CL) may be used in this particular application. A drawback with CL are that they, when measuring sharp edged step signals, suffer from overshoots at the output that might activate the over current protection.</p>
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Pecuh, Ivan. "On-line current monitoring of low-voltage VLSI circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0012/MQ60163.pdf.
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Ren, Huilin. "Current Voltage Characteristics of a Semiconductor Metal Oxide Sensor." Fogler Library, University of Maine, 2001. http://www.library.umaine.edu/theses/pdf/RenH2001.pdf.
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Jonsson, Erik. "Load Current Interruption in Air for Medium Voltage Ratings." Doctoral thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elkraftteknikk, 2014. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-24327.
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Load break switches (LBSs) are common inside metal clad switchgear assemblies where space is a limiting factor. SF6 is usually used in this application due to its superior electrical characteristics, but is unfortunately also a strong greenhouse gas. Therefore development of new products, utilizing air which is an environmental friendly alternative, is in progress. Since air has much lower dielectric strength than SF6, the main challenge with this is therefore to reduce the size. Compact SF6 products have created a retrofit market, and in many existing installation sites larger products will not fit. Current interruption is a complex process and depends on several parameters, and it is not straight forward to optimize the design of a medium voltage (MV) switch. Numerical simulation which is a common for product development in other areas is difficult for this application. Due to the long dominance of SF6 products, little research has been published about the design criteria for LBS technology in air. The scope of the thesis covers current interruption of MV LBSs in air with respect to various design parameters, such as nozzle geometry, nozzle materials, gas flow, and contact movement. Both gas blow-assisted current interruption (associated with puffer breakers) and ablation-assisted current interruption are addressed. The material in the nozzle can enhance the interruption capability. Such a nozzle material is called ablation material. When the arc is burning close to the surface of an ablation material, gas is evaporated which cools the arc. This technology is used to some extent for low voltage switchgear, but much less for higher voltages. The objective is therefore to investigate the potential of this technology for the MV LBS application. All work is done experimentally with similar test conditions as are used for product type testing. A direct powered MV laboratory and a test switch are built. The test switch is designed particularly for parameter studies. The result from air blow experiments reveal the minimum upstream pressure drop required for current interruption for various basic nozzle geometries, and at different contact positions. One study is particular relevant for the 24 kV / 630 A class, and it is found that 0.25 - 0.3 bar upstream pressure drop appears to be a threshold value for successful interruption. It is also presented how the minimum upstream pressure drop varies for different MV LBS ratings. The results show that the needed pressure drop is approximately proportional, both towards the current and towards the rate of rise of recovery voltage. This investigation is made so that the majority of all MV LBS ratings (7 - 52 kV and up to 900 A) are covered. From the ablation experiments it was found that high content of hydrogen in the ablation material is favorable for enhancing the current interruption capability. In a comparison experiment between different polymers, polypropylene shows best interruption capability. This material was therefor applied as ablation material in the test switch, and tested in the MV laboratory. The results reveal high capability to interrupt the thermal phase (over the needs for most MV LBSs), but also that the transient recovery voltage several milliseconds after current zero often leads to dielectric re-ignition. This is opposite to a puffer breaker where the thermal interruption instead appears to be the crucial part.
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Chen, Shin-Liang, and 陳信良. "Temperature and supply voltage independent current reference and voltage reference." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07939159195316351904.
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碩士<br>北台科學技術學院<br>機電整合研究所<br>93<br>This paper presents two kinds of current references which are insensitive to supply voltage and without using resistors. The first current reference is composed of a positive supply voltage coefficient circuit and a negative supply voltage coefficient circuit. The positive supply voltage coefficient circuit exhibits the characteristic that the output current will increase as the supply voltage rises. However, the negative supply voltage coefficient circuit possesses the characteristic that the output current will decrease as the supply voltage rises. By combining these two components with adding operation, the supply voltage coefficient will be cancelled to zero and the output current will reject the variation of supply voltage. In addition, the second current reference is composed of two positive supply voltage coefficient circuits with subtraction operation. The output current of this current reference will also be insensitive to supply voltage. These two current references will be insensitive to supply voltage and identified not only by HSPICE simulation but also by the measured data from an integrated prototype. By applying the current references and the theory of the bandgap reference, we can derive a voltage reference insensitive to supply voltage and temperature.
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Chang, Ting-Wei, and 張庭瑋. "CMOS current reference and voltage reference design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/53278481139150247466.
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碩士<br>北台科學技術學院<br>機電整合研究所<br>94<br>This paper presents some new circuits including CMOS circuit reference and voltage reference.
The architecture of the current references is produced not only by adding a positive supply voltage coefficient current reference and a negative supply voltage coefficient current reference to cancel out the supply voltage variations but also by adding a positive temperature coefficient current reference and a negative temperature coefficient current reference to cancel out the temperature variation. About the negative supply voltage coefficient current reference, we can product it by subtracting two current references with different positive supply voltage coefficient.
This paper also presents a sub-1v voltage reference, which is different from the traditional bandgap reference. The main architecture of the voltage reference is composed of a positive temperature coefficient voltage reference and a negative temperature coefficient voltage reference. At first, by putting two different bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a positive temperature coefficient; Secondly, by putting a ground voltage and a bias voltage of the bipolar junction transistors into the differential pair and adjusting the transistor size, we can obtain a voltage reference with a negative temperature coefficient. Finally, by putting the positive coefficient voltage reference and the negative temperature coefficient voltage reference into the differential pair and adjusting the transistor size, we can obtain a voltage reference with less sensitive to temperature variation.
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Hsu, Kang-Yu, and 徐康禹. "Current Mode Bandgap Voltage Reference." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/xxdacb.
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碩士<br>逢甲大學<br>電機工程所<br>90<br>The objective of this thesis is to design a bandgap voltage reference that can be operated in the range from 3.3V to 5V. The main work is to design a circuit that utilizes a PTAT (proportional to absolute temperature) to compensate the negative temperature coefficient resulting from BJT. The ordinary bandgap voltage reference requires an operational amplifier to stabilize the output voltage. As a result, the circuit will consequently consume considerable area and power dissipation. To circumvent these problems, we propose a current mode bandgap voltage reference, which will not only decrease the temperature effect, but also significantly reduce the power consumption. The proposed current mode bandgap voltage reference can regulate a stabilized output voltage and maintain an excellent resistance to other external variables. Moreover, the output voltage is adjustable by external resistors. Many capability of this design has shown to be superior to those using operational amplifier as feedback.
Our circuit is fabricated bt UMC 0.5μm double-poly triple-metal N-well CMOS process.
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Mastovich, Stefan Noel. "A voltage reference using a temperature-dependent current to bias a junction diode." 2012. http://hdl.handle.net/2152/19702.
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Bandgap voltage-reference circuits generate an appropriate amount of a voltage that varies proportionately to absolute temperature (called PTAT), to cancel the complementary to absolute temperature voltage variation (known as CTAT) of a current biased p-n junction diode so that the sum of the two voltages remains constant with respect to temperature. The bandgap voltage of Silicon is approximately 1.1V. It is inconveniently large to generate and use in short-channel circuits where the supply voltage is limited 1.2V. So the idea presented here is to maintain a constant reference voltage of around half the supply voltage (700mV) across a junction diode. A simple circuit for generating the bias current with appropriate temperature dependence for biasing a diode is presented. Simulation results in 55 nanometer technology demonstrate the feasibility of this scheme. The performance that is achievable is a reference voltage with less than 1 percent variation in the temperature range of 0 to 100 degrees C.<br>text
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Wu, Zheng-Wei, and 吳政衛. "A Low-Voltage Low-Power 17 ppm/c Voltage Reference Using Simple Peaking Current Mirror Circuit." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/2my943.
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碩士<br>國立交通大學<br>電機與控制工程系所<br>92<br>This thesis presents a new and extremely simple low-voltage low-power voltage reference
circuit. The voltage reference circuit uses the peaking current mirror
circuit to extract the current with PTAT (proportional to
absolute temperature), and then the current, through a resistor, is used to compensate for the gate-source voltage
with the negative temperature coefficient. Since the transistors in the peaking current
mirror circuit are operated in weak inversion (subthreshold region), both the power consumption
and the required working supply voltage of the reference
circuit are all low. The
circuit only requires six elements, four transistors and two
resistors. The proposed circuit is implemented
using the TSMC 0.35um 3P3M SiGe BiCMOS technology. The design IC,
after post simulation, attains the minimum supply voltage 1.4 V, output reference voltage 710 mv,
temperature coefficient of 17 ppmC,$ power consumption 6.68 uW
and power supply noise rejection ratio -84 dB at 1MHz.
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Castilho, Miguel Alexandre Leandro. "Design of a Reference Buffer for a Delta-Sigma ADC with Current DAC." Master's thesis, 2019. http://hdl.handle.net/10362/91656.
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In analog to digital conversion, it’s necessary to provide a reference voltage to the Analog
to Digital Converter (ADC), in order to quantify the input signal. However, as the
ADC has a switch constantly commuting on its input it will cause perturbations on the
reference voltage provided by the Bandgap circuit. Thus, it will interfere with the normal
behaviour of the Bandgap circuit, which will longer be capable of provide the desired
reference voltage.
Besides, if the reference voltage is not constant in the desired value the output code generated
by the ADC will have errors.
In order to avoid conversion errors it will be needed to introduce a buffer between the
Bandgap and the ADC. Thus, taking advantage from the characteristics of the buffer (low
output impedance, high input impedance and unitary gain) the system will be capable of
recover from the perturbations introduced by the ADC in the reference voltage.
Therefore, in this thesis are studied some of the already existing architectures of buffers,
in order to see the advantages and disadvantages of each one. This way were chosen the
best three architectures from a theoretical point of view, to implement and simulate, to
obtain all the needed information in order to better compare them.
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Guerra, Duarte Miguel Ribeiro. "Advanced Electrical Characterization of Oxide TFTs Design of a Temperature Compensated Voltage Reference." Master's thesis, 2016. http://hdl.handle.net/10362/20682.
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Any electronic device, regardless of its function, needs a reference voltage
source that feeds reliably, i.e., which generates a constant voltage, upstream and
regardless of external environmental conditions, such as temperature. Since such
a characteristic negatively influences the behavior of the devices, whose base elements
are transistors, it is essential to design a circuit that provides a voltage
which is invariant over a temperature range.
In this work is designed a circuit that is responsible for generating a reference
voltage using only thin film transistors or TFTs, on glass substrate. However,
in order to validate the concept used in the mentioned transistors, it is also
dimensioned and simulated the proposed circuit in 130 nm CMOS technology,
where the respective results are expected to be comparative between the two
technologies. For CMOS technology, for a nominal reference voltage of 124,0 mV,
Cadence simulation reveals ±2,2 ppm/ºC temperature coefficient, between -20
°C and 100 °C. The power consumptions are and 1,434 mW and 4,566 mW for
both CMOS and IGZO-TFT technologies, respectively.
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Silva, António Egídio Guerreiro e. "Single-output reconfigurable voltage controlled voltage-current source." Master's thesis, 2017. http://hdl.handle.net/10400.8/2699.
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Atualmente, a operação de conversão de sinais digitais para analógicos é bastante utilizada. Este tipo de conversão, efetuada por conversores digitais-analógicos (DACs), pode ser encontrado em inúmeros circuitos integrados (ICs) comerciais. Hoje em dia, um DAC pode ter saída só em tensão, só em corrente ou em tensão e corrente, mas disponibilizadas em pinos distintos do IC. Estes últimos circuitos, para proporcionarem os dois tipos de saída utilizam circuitos específicos e distintos para as saídas em tensão e corrente, levando a um aumento de complexidade, de consumo de energia e da área de layout. Além disso, neste tipo de conversores as saídas em corrente são unipolares, o que diminui o leque de aplicações onde eventualmente podem ser usados. Com o intuito de aumentar a versatilidade, flexibilidade e ultrapassar alguns dos problemas enumerados, o circuito de saída de um DAC deve ser reconfigurável de forma a que a sua saída (no mesmo pino do IC) possa ser em corrente ou em tensão e ter características bipolares. Para além disso, a entrada deve também ser diferencial.
Neste trabalho é apresentado o circuito e o estudo de uma fonte de tensão-corrente controlada por tensão reconfigurável (RVCVCS) com entrada diferencial e saída única bipolar, podendo ser usada no circuito de saída de um DAC. A topologia do circuito é baseada na fonte corrente de Howland e no amplificador de tensão diferencial, podendo por isso operar como fonte de tensão controlada por tensão ou como fonte de corrente também controlada por tensão. O estudo da RVCVCS envolveu a determinação da transcondutância, do ganho de tensão, da resistência de saída, da rejeição em modo comum e tensão de offset para ambos os modos de operação.
Para demonstrar a funcionalidade do circuito proposto, foi desenvolvido uma RVCVCS em tecnologia CMOS de 130 nm. O desenvolvimento baseou-se nos resultados teóricos obtidos no estudo e análise do circuito. Os resultados obtidos mostram que o funcionamento da RVCVCS, quer em modo de tensão quer em modo de corrente, é o correto, podendo a RVCVCS ser comutada entre os dois modos sem ser necessário desligar a alimentação.
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Cheng, Chin-Hung, and 鄭欽鴻. "Bandgap Reference Voltage Generator." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/10794634026978236467.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>92<br>Precision voltage reference plays an important role in modern integrated circuits systems. It can produce a stable reference voltage insensitive to the variations of supply voltage and temperature. Voltage references are widely adopted in many integrated circuits, such as A/D or D/A converters, operational amplifiers, and linear regulators. They are used for defining input/output voltage range, biasing current source of differential pairs, and providing a comparison reference for comparators, etc.
The objective of this thesis is to design a bandgap reference voltage generator with input voltage 3V to 6V and output voltage around 1.25V. This reference voltage is intended for using in low dropout linear regulators (LDO). A pre-regulator circuit feeds the bandgap circuit with a regulated 2V to lower the supply voltage sensitivity. A new bandgap circuit topology is also presented. The final bandgap reference with supply voltage sensitivity less than 0.3 mV/V, and temperature coefficient around 7 ppm/℃, and power consumption lower than 100μW is achieved.
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Hsieh, Jen-Chung, and 謝荏仲. "Zero Voltage Zero Current Switching Three Phase Voltage Relay." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/f7vs63.
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碩士<br>聖約翰科技大學<br>電機工程系碩士班<br>106<br>The project presents a new three phase voltage protection relay, which use PIC18F27J13 microcontroller to implement the main protection function of the relay such as incorrect phase sequence, overvoltage, undervoltage, phase failure, asymmetry etc. In addition to these functions, we add on the adjustment of the switching phase angle of the relay contactor. While the relay is turn on at zero voltage and turn off at zero current, the spark of the contactor will be eliminated and the power dissipation is reduced, also the EMI is reduced and relay life is extended.
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Ruoh-Fei, Chaw, and 趙若飛. "Design of active filters employing the second generation current conveyors, differential voltage current conveyors and voltage or current followers." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/70905788768139095820.
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碩士<br>中原大學<br>電機工程研究所<br>86<br>It has been verified that the circuits constructed by active current-mode elements have the advantage of higher signal bandwidths, larger dynamic range, greater linearity, less power dissipation and simpler circuit structure. So, the circuits which are designed by employing the current conveyor and the current feedback amplifier have been received considerable attention recently. In addition, the differential voltage curre-nt conveyor was presented by H. O. Elwan and A. M. Soliman in 1997. This active element is a powerful building block, especially for applica-tion demanding differential or floating inputs like impedance converters and current-mode instrumentation amplifiers.We proposed two filters using the second-generation current conve-yor, which are one multifunction voltage-mode filter with one input and three outputs and one universal current-mode filter with three inputs and one output, respectively.Comparing with the published paper, the proposed circuits offer the following advantageous features: use fewer active and passive components, suit for integration and enjoy low active and passive sensitivities.Moreover, we design a serial voltage-mode or current-mode filters employing the differential voltage current conveyor. We also discuss their characteristics and feasibilities.The last, we proposed a current-mode filter with one input and three outputs using the voltage follower and current follower which are with low tracking errors.The results of experiments and simulations using the IC-AD844 or the Design Center 6.1 are obtained to confirm the theoretical predictions.
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Liu, Chzung-Tai, and 劉宗泰. "The study of low voltage bandgap voltage reference circuit." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/37524136168903290293.
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Huang, Kuei-Chen, and 黃癸禎. "Tempeature-Stable Voltage Reference, Transconductor, and Voltage-Controlled Oscillator." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/80295709853083861334.
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碩士<br>國立彰化師範大學<br>工業教育學系<br>88<br>In the recent years, small size, light weight, and reliable operation in any environment have become the basic requirement in the electronic products such as personal communication systems and notebooks. But smaller feature sizes, higher packing density and rising power consumption lead to dramatic temperature increases in current high-performance VLSI circuits. To achieve stable performance of circuits, we should consider the influence of the temperature variation in the circuit design. In this thesis, we focus on the performance of the voltage reference, transconductor, and voltage-controlled oscillator versus the temperature variations. And we will provide several ways to compensate the influence of temperature drift. Using these compensation circuits, the temperature-stable voltage reference, transconductor, and voltage-controlled oscillator can be obtained.
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Wu, Yi-Ping, and 吳一平. "Low Temperature-Coefficient Reference Voltage." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/pswyun.
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碩士<br>國立虎尾科技大學<br>電子工程系碩士班<br>103<br>This thesis is related to the design of cascade low temperature-coefficient reference voltage. The design principle is using both the positive and the negative temperature-coefficient parameters in BJT to compensate each other, and then a zero temperature-coefficient output reference voltage can be achieved. Two different circuit architectures have been simulated and discussed. As compared with the existed reference voltage circuits, the proposed circuits benefit from simpler circuit architecture, less chip area, and also there are no operational amplifiers included in the proposed circuits.
Detailed design principle has been disclosed in this thesis, and the HSPICE and LAKER simulation programs with 0.35-μm process parameters have been used to perform the layout and implement the circuits. According to the post-layout simulation results, where the supply voltage is 5V and the temperature ranges from -20°C-120°C, after first order temperature-compensation, as the output reference voltage is 3.014V, the maximum output voltage variation is 2.568mV, and when the output reference voltage is 2.495V, the maximum output voltage variation is 1.772mV, and finally if the output reference voltage is 1.249V, the maximum output voltage variation is 1.192mV. The corresponding power dissipation is 0.891mW. After second order temperature-compensation, the output reference voltage can be 2.489V with the maximum output voltage variation of only 1.127mV, and 1.127V with the maximum output voltage variation of 0.589mV. The corresponding power dissipation is 0.954mW.
All the simulation results are consistent with the theoretic analysis. The proposed low temperature-coefficient reference voltage circuits can be applied to vehicle electronic devices design and other digital and analog circuits.
Keywords: temperature coefficient, cascode, current mirror, reference voltage.
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Teixeira, Bruno Miguel da Silva. "Self calibrated current reference." Dissertação, 2015. https://repositorio-aberto.up.pt/handle/10216/90382.
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Teixeira, Bruno Miguel da Silva. "Self calibrated current reference." Master's thesis, 2015. https://repositorio-aberto.up.pt/handle/10216/90382.
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Chen, Suheng. "Low-power switched capacitor voltage reference." 2009. http://etd.utk.edu/2009/Spring2009Dissertations/ChenSuheng.pdf.
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Liao, Jia-Zheng, and 廖家正. "Design of A CMOS Reference Voltage." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/3h6nk8.
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碩士<br>國立虎尾科技大學<br>電子工程系碩士班<br>101<br>In this thesis, a CMOS differential-mode reference voltage circuit has been proposed. By properly using the positive and negative temperature coefficient parameters, a zero temperature-coefficient can be achieved. The proposed circuits are based on the traditional bandgap voltage reference circuit architecture with an additional current mirror and a proportional-to-absolute-temperature current source which is composed of current mirrors. As compared with the existed differential-mode reference voltage circuit, the proposed circuit does not need an operational amplifier, therefore it benefits from simpler circuit architecture, less chip area, and less power consumption. Besides the detailed design principle, the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to perform the pre-layout and post-layout simulation. According to the post-layout simulation results, as the supply voltages is 3.3V, the differential-mode output voltage reference circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 1.3mV(0.225%), the corresponding power dissipation is 2.354mW and the temperature-coefficient is 16.11 ppm/˚C. In addition, if a transistor and a resistor are removed from the proposed differential-mode output voltage reference circuit, a single-ended mode reference voltage with zero temperature coefficient can be obtained. According to the post-layout simulation results, when the supply voltages is 2.8V, and as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2.01mV(0.387%), the corresponding power dissipation is 1.412mW and the temperature-coefficient is 27.79 ppm/˚C.
All the simulation results are consistent with the theoretic analysis. The proposed circuits can be applied to different analog circuits.