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Relevant bibliographies by topics / Current converter

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Academic literature on the topic 'Current converter'

Author: Grafiati

Published: 4 June 2021

Last updated: 10 February 2022

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Journal articles on the topic "Current converter"

1

Kobori, Yasunori, Jing Li, Yi Fei Sun, Minh Tri Tran, Anna Kuwana, and Haruo Kobayashi. "Automatic Current Balance for Multi-Phase Switching Converters with Ripple Control or Soft Switch." Advanced Engineering Forum 38 (November 2020): 143–56. http://dx.doi.org/10.4028/www.scientific.net/aef.38.143.

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This paper proposes a new multi-phase switching converter with atuotomatic current barance technique. It is well-known that the multi-phase switching converter is suitable to handle large output current with small output voltage ripple for the buck converters which use the clock pulse. This paper investigates a multi-phase controlled method for the ripple-controlled converters and the soft switching converters, that use no clock pulse; for this reason, these converters are difficult to realize multi-phase converter configurations. There are some multi-phase hysteretic controlled converters; they utilize a main clock generator or an external sub-clock pulse, which has the master-slave synchronization method. But it is difficult to respond to a frequency change of the master converter. These multi-phase converters have not considered the imbalance among phase currents caused by variations of inductors and semiconductor switches in the power stage. For the commercialized multi-phase Voltage Regulating Modules (VRMs), the inductors and the semiconductor switches are selected to adjust the balance among the phase currents. However, there is no multi-phase soft switching converter.Then we have developed the multi-phase ripple-controlled converter and the multi-phase soft switching converter with the technique of detecting 180-degree from the variable operating frequency of the main converter. Moreover, in these converters, there appears the current imbalance because of the element variations among inductors and capacitors, if some cares are not taken there. Then we have developed the automatic correction for the current imbalance by modifying the width of the Constant On Time (COT) pulse or modifying the slope of the saw-tooth signal.

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Rashag, Hassan Farahan. "Optimization of efficiency for power system using three phase AC to AC matrix converter with the algorithm of fuzzy controller." International Journal of Applied Power Engineering (IJAPE) 8, no. 2 (August 1, 2019): 129. http://dx.doi.org/10.11591/ijape.v8.i2.pp129-133.

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This paper suggested a new contribution of three phase AC to AC matrix converter MC via fuzzy logic controller FLC to enhance the whole system. However, the weakness of matrix converter is that the input- output voltage transfer is control to 87% for input and output waveform. Also, matrix converter is more sensitive to the trouble of input voltage which deteriorates the system performance. To overcome these problems, and to improve the efficiency of system, FLC with matrix converter is proposed to minimize the sensitivity to the load, and to increase voltage transfer. In this paper the currents a,b,c are converted to alpha and beta current via Clarke transformation . In this method two FLC are used. The error (between alpha current and reference current) (e) and the change of this error (de) will apply to first FLC. The output of FLC is actual alpha current. In the other hand, the error of beta current and the change of error are also passes through the second FLC to produce the actual beta current. The actual alpha and beta current is converted to direct and quadrature d-q current by park transformation. The d-q current is converted to (a, b, c) out currents by inverse park transformation, the results of this method express that the matrix converter with FLC is more capable, high accuracy with better efficiency as compared with conventional matrix converter system.

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Benjanarasut, Jirawut, and Bunlung Neammanee. "Control Techniques to Directly Parallel Line-Side Converters for Wind Energy System." Applied Mechanics and Materials 704 (December 2014): 161–69. http://dx.doi.org/10.4028/www.scientific.net/amm.704.161.

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The direct paralleled converters can increase the power rating, reliability, efficiency, as well as decrease the cost and current/voltage ripples which are suitable for high power converters. However, when converters are in direct parallel, the circulating currents will be generated automatically. This will result in high current distortion which causes the line inductors saturation and damage the power switches; and therefore overall performance of the system will be degraded. This paper purposes a zero sequence current control technique to reduce the circulating current in directly parallel line-side converter of the wind energy conversion system. The case studies are carried out on a 2 MW wind turbine to investigate the effects of non-identical line inductors and PWM carrier phase shift of each converter to the circulating current. The simulation results confirm that zero sequence current controllers that can reduce the zero sequence current in any conditions. The dynamic responses of the direct parallel converters and a single converter are nearly the same but the direct parallel converters have better current ripple and THDi.

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Uma Maheswari, S., and K. V. Kandasamy. "Development of Zeta Converter for Permanent Magnet Brushless Direct Current Motor." Applied Mechanics and Materials 573 (June 2014): 102–7. http://dx.doi.org/10.4028/www.scientific.net/amm.573.102.

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Converter plays a vital role in modern transferable electronic devices and systems. In the battery operated transferable devices, the battery supplies an input voltage to the converter which in turn converts into the desired voltage. Buck-boost, Cuk, SEPIC and Zeta converter are meeting the operational requirements of DC-DC converters. The DC-DC converters are used in both buck function as well as boost function. But the advantage of Zeta converter is that, it does not suffer the polarity reversal problem. The aim of the proposed work is to design a Zeta converter which can be used to drive the Permanent Magnet Brushless Direct Current Motor. The proposed Zeta converter is suggested to control the speed of the Permanent Magnet Brushless Direct Current Motor, according to the generated switching sequence. The proposed work is generally used for low power applications and occasionally used for medium power applications.

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Kim, Sung-Hun, Bum-Jun Kim, Jung-Min Park, and Chung-Yuen Won. "Decentralized Control Method of ISOP Converter for Input Voltage Sharing and Output Current Sharing in Current Control Loop." Energies 13, no. 5 (March 2, 2020): 1114. http://dx.doi.org/10.3390/en13051114.

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Input-Series-Output-Parallel (ISOP) converters, a kind of modular converter, are used in high-input voltage and high-output current applications. In ISOP converters, Input Voltage Sharing (IVS) and Output Current Sharing (OCS) should be implemented for stable operation. In order to solve this problem, this paper proposes a decentralized control method. In the proposed control, output current reference is changed according to the decentralized control characteristic in individual current control loops. In this way, the proposed control method is able to implement IVS and OCS without communication. Also, this method can be easily used in current control loops and has high reliability compared to conventional control methods that require communication. In this paper, the operation principle is described to elucidate the proposed control and a small signal model of an ISOP converter is also implemented. Based on the small signal model, IVS stability analysis is performed using pole-zero maps with varying coefficients and control gains. In addition, the current control loop is designed in a stable region. In order to demonstrate the proposed control method, a prototype ISOP converter is configured using full-bridge converters. The performance of IVS and OCS in an ISOP converter is verified by experimental result.

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Muñoz, Juan-Guillermo, Guillermo Gallo, Fabiola Angulo, and Gustavo Osorio. "Slope Compensation Design for a Peak Current-Mode Controlled Boost-Flyback Converter." Energies 11, no. 11 (November 1, 2018): 3000. http://dx.doi.org/10.3390/en11113000.

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Peak current-mode control is widely used in power converters and involves the use of an external compensation ramp to suppress undesired behaviors and to enhance the stability range of the Period-1 orbit. A boost converter uses an analytical expression to find a compensation ramp; however, other more complex converters do not use such an expression, and the corresponding compensation ramp must be computed using complex mechanisms. A boost-flyback converter is a power converter with coupled inductors. In addition to its high efficiency and high voltage gains, this converter reduces voltage stress acting on semiconductor devices and thus offers many benefits as a converter. This paper presents an analytical expression for computing the value of a compensation ramp for a peak current-mode controlled boost-flyback converter using its simplified model. Formula results are compared to analytical results based on a monodromy matrix with numerical results using bifurcations diagrams and with experimental results using a lab prototype of 100 W.

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Wawryn, K., and R. Suszynski. "Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system." Bulletin of the Polish Academy of Sciences: Technical Sciences 61, no. 4 (December 1, 2013): 979–88. http://dx.doi.org/10.2478/bpasts-2013-0105.

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Abstract A low power, low voltage current mode 9 bit pipelined a/d converter and 8 bit self-calibrated d/a converter to interface a DSP system are presented in the paper. The a/d converter is built of 1.5 bit stages with digital error correction logic. The d/a converter is composed of 3 LSBs fine and 5 MSBs coarse current mode converters. The a/d and d/a converters were designed in 0.35 μm technology, then fabricated to verify the proposed concept. The performances of both converters are compared to the performances of known converter structures. The main advantages of the proposed converters are low power consumption and small chip area.

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Dheeraj, Alagu, and V. Rajini. "Center Clamped Forward Converter for High Current Applications." Journal of Computational and Theoretical Nanoscience 14, no. 1 (January 1, 2017): 395–402. http://dx.doi.org/10.1166/jctn.2017.6333.

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High current applications like Microprocessors, Fuel cells, Electric Hybrid Vehicles, Solar Cells etc., use interleaved isolated buck derived converter. Interleaving of converters for such high current applications converters is done to achieve reduced input capacitor ripple voltages, output capacitor ripple current cancellation and reduced peak currents of output inductors. Generally, interleaving requires a higher number of transformers through which distributed magnetics can be achieved. i.e., one bulky transformer can be replaced with low power profile transformers. The performance of forward converter depends on core resetting of the main transformer. The core’s magnetizing energy is recycled by resetting it. In the absence of core reset, the current builds up at each switching cycle, saturates the core, causes reverse recovery problem in the diode and the active clamp will no longer in zero voltage state during turn on of the main switch. The transformer secondary output is used as a gating pulse for Synchronous Rectifiers. These have very low forward drop which are most suitable for high current applications. Among various used clamping methods, the transformer core is optimized effectively by Active center clamp reset approach. The proposed method results in less number of switches and clamping capacitor, and lower cost compared to conventional forward converter. Reduction in voltage stress without losing duty-cycle ratio is also achieved by means of a series-parallel connected switch structure with Self Driven Synchronous Rectifiers. The proposed center clamp converter overcomes the Maximum Duty cycle limitation of 50%. This paper mainly focuses on active center clamp forward converter and is also compared with Active Positive Negative clamping techniques.

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Xie, Yan, Bo Chao Chen, and Yao Jun Chen. "Development and Current Status of Multi-Level Converter." Applied Mechanics and Materials 201-202 (October 2012): 95–98. http://dx.doi.org/10.4028/www.scientific.net/amm.201-202.95.

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The multi-level converter is one of the focuses in the current high-voltage high-power field of power conversion, and is found widely application in high power drive system. It generated so far for nearly three decades of history. During this period a large number of multi-level topology appeared, there are three most commonly used, which are diode clamped, capacitor and cascaded H-bridge. In this paper, the development of the multi-level converter is reviewed. The structure of three multi-level converter topologies are given, and then their advantages and disadvantages are given by analyzing and comparing their characteristics. Finally, a new modular multi-level converter (MMC) is introduced which is one of research focus of multi-level converter field at present. Its structure and working principle are described in detail. Multi-level converters will continue to be developed to meet the demand of high-voltage and high power applications.

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Dybko, Maxim, Sergey Brovanov, and Hong Hee Lee. "Multilevel NPC Converters in Parallel Connection for Power Conditioning Systems." Applied Mechanics and Materials 792 (September 2015): 189–96. http://dx.doi.org/10.4028/www.scientific.net/amm.792.189.

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This paper investigates a multilevel combined NPC converter for medium-and high-power energy storage systems and active power filters. The proposed multilevel NPC converter is composed of a parallel connection of multiple NPC converters using the current sharing reactors and involves the phase shifted PWM strategy for better energy quality performance. Using the switching function-based mathematical model, the proposed multilevel converter is evaluated to show the energy quality performance and fault tolerance of an energy storage system or active power filter. In addition, the switching frequency of circulating currents is analyzed to obtain its relationship with the converter parameters and maximum sharing reactor current ripple. The performance of the proposed multilevel converter is verified by simulation.

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Dissertations / Theses on the topic "Current converter"

1

Empringham, Lee. "Matrix converter current commutation." Thesis, University of Nottingham, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.342443.

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Chen, Haoning (William). "LLC Resonant Current Doubler Converter." Thesis, University of Canterbury. Electrical and Computer Engineering, 2013. http://hdl.handle.net/10092/8492.

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The telecommunications market is one of the large rapidly growing fields in today’s power supply industry due to the increasing demand for telecom distributed power supply (DPS) systems. The half-bridge LLC (Inductor-Inductor-Capacitor) resonant converter is currently the most attractive topology for the design and implementation of 24V/48V DC telecom power converters. The current doubler rectifier (CDR) converter topology was invented and described in the early 1950s which can offer the unique characteristic of halving the output voltage while doubling the output current compared to a standard rectifier. In this thesis, the current doubler converter topology with its unique characteristic is evaluated as a complementary solution to improve the LLC resonant converter performance, especially for the low output voltage and high output current telecommunication applications. A novel half-bridge LLC resonant current doubler converter (LLC-CDR) is proposed in this thesis which can offer several performance benefits compared to conventional LLC-standard rectifier design . The unique characteristics of the LLC-CDR topology can offer significant improvements by transformation of a 48V converter into a 24V converter with the same power density. This thesis introduces a new SPICE-based simulation model to analyse the operation of this novel LLC-CDR converter circuit design. This model can be used to define the critical component parameters for the LLC -CDR circuit output inductor values. It can also be used to predict the circuit overall performance under different load conditions. Both time-domain based transient simulation analysis and frequency-domain based AC analysis provided by this simulation model showed favourable results in comparison to bench measurement results on a prototype. The model provides a valuable insight to reveal some of the unique characteristics of this LLC -CDR topology. It demonstrates a proof of concept that the conventional LLC resonant converter can be easily redesigned for low voltage, high current applications by using the LLC-CDR topology without requiring a new design for the LLC resonant stage components and the power transformer. A new magnetic integration solution was proposed to significantly improve the overall performance in the LLC-CDR topology that had not been published before. The LLC-CDR converter hardware prototypes with two output inductors coupled and uncoupled configurations were extensively modelled, constructed and bench tested.Test results demonstrated the suitability of an integrated coupled inductors design for the novel LLC-CDR converter application. The integrated coupled inductors design can significantly improve the LLC-CDR converter frequency-domain based AC simulation analysis results. In addition, these results also illustrate the potential benefit of how the magnetic integration design in general could reduce the magnetic component size, cost, and weight compared to the uncoupled inductors design. Finally, a hardware prototype circuit was constructed based on a commercial 1800 W single phase telecom power converter to verify the operation of this novel half bridge LLC-CDR topology. The converter prototype successfully operated at both no load and full load conditions with the nominal output voltage halved from 48VDC to 24VDC, and doubled the output current to match the same output power density. It also demonstrates that the efficiency of this novel half bridge LLC –CDR is 92% compares to 90% of EATON’s commercial 24VDC LLC resonant converter, which can fulfill the research goals.

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Stihi, Omar. "Single phase controlled current PWM converter." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63844.

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Mai, Yuan Yen. "Current-mode DC-DC buck converter with current-voltage feedforward control /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20MAI.

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Kulkarni, Ashok. "Characteristics of a controlled current PWM converter." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66006.

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Nishimoto, Masahiro. "Analytical study of a controlled current PWM converter." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65432.

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Ho, Kwun-yuan Godwin, and 賀觀元. "A novel integrated synchronous rectifier for LLC resonant converter." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49618180.

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There is ever-increasing demand in telecommunication system, data server and computer equipment for low voltage, high current power supply. LLC resonant converter is a good topology on primary side of the converter because it has soft switching and resonant conversion. However, the passive rectifier in the secondary side has high power dissipation. Synchronous rectifier is a popular method to reduce this rectification loss. Although there are many types of synchronous rectifier for PWM converter, most of them do not function well in LLC resonant converters. It is because the wave form of LLC resonant converter is different from PWM. The objective of this research is to reduce the power dissipation and physical size at the same time. In this thesis, a novel current driven synchronous rectifier with saturable current transformer and dynamic gate voltage control for LLC resonant Converter is presented. This novel circuit reduces the rectification loss and size of the current transformer in the synchronous rectifier. This synchronous rectifier has several outstanding characteristics compared with generic voltage driven and current driven synchronous rectifier. The saturable feature reduces the current transformer turns. Inherent dynamic gate voltage controlled by saturable current transformer reduces gate loss in the MOSFET. A novel driving circuit is proposed for accurate turn off time. It reduces loss significantly. This synchronous rectifier is completely self-contained which can replace the rectifier diode as a drop in replacement. It is insensitive to parasitic inductance. In order to explain the current transformer saturable, a model of saturable current transformer is proposed. A prototype demonstrates the advantages of the proposed current driven synchronous rectifier. Furthermore, a novel integrated synchronous rectifier is presented which provides a more compact system. The synchronous rectifier current transformer is integrated with the main transformer which reduces the number of circuit joints in power path. Each soldering joint generates significance loss in power converter. A pair of 0.5mΩ soldering joint in 25A current path produces 0.62W loss. The placement of the integrated current transformer is important. A criterion for the placement of the current transformer within the main transformer is to avoid interference to the current transformer from the magnetic flux of the main transformer. Thus, a placement method to integrate the current transformer into the main transformer is proposed. An integrated current transformer model is suggested to explain the operation of the integrated synchronous rectifier. A prototype demonstrates the advantages of the integrated synchronous rectifier.
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Electrical and Electronic Engineering
Master
Master of Philosophy

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Crowe, Robert A. "Design, construction and testing of a reduced-scale cascaded multi-level converter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Jun%5FCrowe.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003.
Thesis advisor(s): Robert W. Ashton, John G. Ciezki, Douglas J. Fouts. Includes bibliographical references (p. 125-126). Also available online.

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McClusky, Scott Logan. "HIGH VOLTAGE RESONANT SELF-TRACKING CURRENT-FED CONVERTER." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/254.

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High voltage power supply design presents unique requirements, combining safety, controllability, high performance, and high efficiencies. A new Resonant Self-Tracking Current-Fed Converter (RST-CFC) is investigated as a proof-of-concept of a high voltage power supply particularly for an X-ray system. These systems require fast voltage rise times and low ripple to yield a clear image. The proposed converter implements high-frequency resonance among discrete components and transformer parasitics to achieve high voltage gain, and the self-tracking nature ensures operation at maximum gain while power switches achieve zero-voltage switching across the full load range. This converter exhibits an inherent indefinite short-circuit capability. Theoretical results were obtained through simulations and verified by experimental results through a complete test configuration. Converter topology viability was confirmed through hardware testing and characterization.

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Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

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Books on the topic "Current converter"

1

Li, Zhang Crowther, ed. Power converter circuits. New York: Marcel Dekker, 2004.

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Converter and filter circuits. Boston: Newnes, 1996.

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The modern converter and filter circuit encyclopedia. Blue Ridge Summit, PA: TAB Books, 1993.

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Singor, Henry W. High performance current scaling digital-to-analog converter design. Ottawa: National Library of Canada, 1990.

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Uster, Markus. Current-mode analog-to-digital converter for array implementation. Konstanz: Hartung-Gorre, 2003.

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Baronian, Sofia. Analysis and design of a high-current AC-DC switching converter. Ottawa: National Library of Canada, 1996.

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Henryk, Tunia, ed. Automatic control of converter-fed drives. Amsterdam: Elsevier, 1994.

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Li, Jia. Effect of geomagnetically induced current (GIC) on second harmonic instability of HVDC converter. Ottawa: National Library of Canada, 1993.

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Drieënhuizen, Bert Pieter van. Integrated electrostatic RMS-to-DC converter: Fabricated in a BIFET-compatible surface-micromachining process. Delft: Delft University Press, 1996.

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Cujec, Anne-Marie. An optimized bit cell design for a pipelined current-mode algorithmic A/D converter. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1992.

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Book chapters on the topic "Current converter"

1

Wu, Keng C. "Simulation of Flyback Converter with Current Mode Control." In Pulse Width Modulated DC-DC Converters, 208–16. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6021-0_14.

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Remya, K. G., Chikku Abraham, and Babita R. Jose. "A Slope Compensated Current Mode Controlled Boost Converter." In Eco-friendly Computing and Communication Systems, 69–76. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-32112-2_9.

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Roomi, Muhammad M., and Harikrishna R. Pinkymol. "Multilevel Converter-Based Flexible Alternating Current Transmission System." In Advanced Multilevel Converters and Applications in Grid Integration, 455–71. Chichester, UK: John Wiley & Sons, Ltd, 2018. http://dx.doi.org/10.1002/9781119476030.ch19.

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Chang, Henry, Edoardo Charbon, Umakanta Choudhury, Alper Demir, Eric Felt, Edward Liu, Enrico Malavasi, Alberto Sangiovanni-Vincentelli, and Iasson Vassiliou. "Current Source Digital-To-Analog Converter Design Example." In A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, 223–45. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4419-8752-5_9.

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Jiang, Dong, Zewei Shen, Qiao Li, Jianan Chen, and Zicheng Liu. "Current Ripple Prediction Model for Power Electronics Converter." In Advanced Pulse-Width-Modulation: With Freedom to Optimize Power Electronics Converters, 63–108. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4385-6_4.

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Buxbaum, Arne, Klaus Schierau, Alan Straughen, and R. Bonert. "Speed Control of a Converter Drive with Current Feedback." In Design of Control Systems for DC Drives, 162–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/978-3-642-84006-7_24.

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Das, S. K., and P. Syam. "Analysis of Different Current Commutation Technique in Matrix Converter." In Lecture Notes in Electrical Engineering, 485–96. New Delhi: Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-2119-7_49.

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Morawiec, Marcin, and Zbigniew Krzeminski. "The Electrical Drive Systems with the Current Source Converter." In Power Electronics for Renewable Energy Systems, Transportation and Industrial Applications, 630–63. Chichester, UK: John Wiley & Sons, Ltd, 2014. http://dx.doi.org/10.1002/9781118755525.ch20.

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Yang, Miao, Weifeng Sun, Shen Xu, Mu Li, and Shengli Lu. "A High-Accuracy Current Sensing Circuit with Clamping Current Compensation for Current-Mode DC-DC Buck Converter." In Lecture Notes in Electrical Engineering, 561–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_72.

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Shen, Tianfu, and Wenbo Shi. "Internal AC Fault of a Converter Station Based on Modular Multilevel Converter High Voltage Direct Current." In Proceedings of the Second International Conference on Mechatronics and Automatic Control, 249–57. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-13707-0_28.

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Conference papers on the topic "Current converter"

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Druzhinin, Anatoliy, Ihor Ostrovskii, and Iurii Kogut. "Alternating Current Converter." In 2006 International Conference - Modern Problems of Radio Engineering, Telecommunications, and Computer Science. IEEE, 2006. http://dx.doi.org/10.1109/tcset.2006.4404618.

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Popov, Vladimir, Evgeny Baranov, and Alexey Malnev. "Current source matrix converter." In 2015 16th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM). IEEE, 2015. http://dx.doi.org/10.1109/edm.2015.7184568.

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Mathew, M., K. Hayatleh, B. L. Hart, and F. J. Lidgey. "Linear differential voltage-current converter." In 2007 Ph.D Research in Microelectronics and Electronics Conference. IEEE, 2007. http://dx.doi.org/10.1109/rme.2007.4401851.

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Seevinck, E., R. F. Wassenaar, M. G. van Leeuwen, G. Boom, E. Holle, and Ron van der Wal. "Wideband Voltage-Current Converter Circuit." In 11th European Solid State Circuits Conference. IEEE, 1985. http://dx.doi.org/10.1109/esscirc.1985.5468027.

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Vlassis, Spyridon, Orfeas Felouris-Panetas, George Souliotis, and Fotis Plessas. "Linear Current-to-Time Converter." In 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS). IEEE, 2019. http://dx.doi.org/10.1109/dtis.2019.8734952.

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Himmelstoss, Felix A., and Michael Jungmayer. "Zero-Current-Switching Buck Converter." In 2019 International Conference on Electrical Drives & Power Electronics (EDPE). IEEE, 2019. http://dx.doi.org/10.1109/edpe.2019.8883913.

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Sooksatra, S., and C. Q. Lee. "Current driven series resonant converter." In Applied Power Electronics Conference and Exposition. IEEE, 1990. http://dx.doi.org/10.1109/apec.1990.66404.

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Yadav, R., K. R. Raghunandan, A. Dodabalapur, T. L. Viswanathan, and T. R. Viswanathan. "Operational current to frequency converter." In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2013. http://dx.doi.org/10.1109/mwscas.2013.6674795.

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Chien-Ming Wang, Chang-Hua Lin, Yu-Hao Lai, and Chien-Yeh Ho. "Zero-current-transition current-fed full-bridge PWM converter." In TENCON 2011 - 2011 IEEE Region 10 Conference. IEEE, 2011. http://dx.doi.org/10.1109/tencon.2011.6129261.

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R. F. B. de Souza, Victor, Luciano S. Barros, and Flavio B. Costa. "Performance Comparison of Converter Topologies for Double Fed Induction Generator-based Wind Energy Conversion Systems." In Congresso Brasileiro de Automática - 2020. sbabra, 2020. http://dx.doi.org/10.48011/asba.v2i1.1512.

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The advancements in power electronics have supported the widespread penetration of wind energy conversion systems (WECS) in electric grids. In this context, power converters have crucial functionality in the control of active and reactive power injection, moreover they are directly related to voltage and current harmonic distortion levels, mechanical and thermal stress that are experienced by the wind turbine. Currently, several topologies have been tested in order to improve the performance and increase the power processing of WECS to support the network demand. Based on the relevance of this issue, this paper presents a performance comparison of a Double Fed Induction Generator(DFIG)-based WECS employing three topologies of back-toback converters: two-level voltage source converter topology (2L-VSC), neutral point clamped (NPC) and modular multilevel converter (MMC). Simulation results present DFIG currents, voltages, torque, speed and the total harmonic distortion (THD), highlighting the performance improvement employing multilevel topologies and the impacts of using each topology.

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Reports on the topic "Current converter"

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Jin, Lei. Modeling of DC Link Capacitor Current Ripple for Electric Vehicle Traction Converter. Portland State University Library, September 2013. http://dx.doi.org/10.15760/trec.40.

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Roberts, Jesse D., Craig Jones, and Jason Magalen. Wave Energy Converter (WEC) Array Effects on Wave Current and Sediment Circulation: Monterey Bay CA. Office of Scientific and Technical Information (OSTI), September 2014. http://dx.doi.org/10.2172/1156603.

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Majeski, R., C. K. Phillips, and J. R. Wilson. Electron heating and current drive by mode converted slow waves. Office of Scientific and Technical Information (OSTI), August 1994. http://dx.doi.org/10.2172/10180185.

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Hermach, F. L. An investigation of the uncertainties of the NBS thermal voltage and current converters. Gaithersburg, MD: National Bureau of Standards, 1985. http://dx.doi.org/10.6028/nbs.ir.84-2903.

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Stuart, Thomas A. A Study of Two Control Methods for Full Bridge Converters: Soft Switch Bypass and Current Mode Control. Fort Belvoir, VA: Defense Technical Information Center, June 1990. http://dx.doi.org/10.21236/ada227136.

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Kuznetsov, Victor, Vladislav Litvinenko, Egor Bykov, and Vadim Lukin. A program for determining the area of the object entering the IR sensor grid, as well as determining the dynamic characteristics. Science and Innovation Center Publishing House, April 2021. http://dx.doi.org/10.12731/bykov.0415.15042021.

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Currently, to evaluate the dynamic characteristics of objects, quite a large number of devices are used in the form of chronographs, which consist of various optical, thermal and laser sensors. Among the problems of these devices, the following can be distinguished: the lack of recording of the received data; the inaccessibility of taking into account the trajectory of the object flying in the sensor area, as well as taking into consideration the trajectory of the object during the approach to the device frame. The signal received from the infrared sensors is recorded in a separate document in txt format, in the form of a table. When you turn to the document, data is read from the current position of the input data stream in the specified list by an argument in accordance with the given condition. As a result of reading the data, it forms an array that includes N number of columns. The array is constructed in a such way that the first column includes time values, and columns 2...N- the value of voltage . The algorithm uses cycles that perform the function of deleting array rows where there is a fact of exceeding the threshold value in more than two columns, as well as rows where the threshold level was not exceeded. The modified array is converted into two new arrays, each of which includes data from different sensor frames. An array with the coordinates of the centers of the sensor operation zones was created to apply the Pythagorean theorem in three-dimensional space, which is necessary for calculating the exact distance between the zones. The time is determined by the difference in the response of the first and second sensor frames. Knowing the path and time, we are able to calculate the exact speed of the object. For visualization, the oscillograms of each sensor channel were displayed, and a chronograph model was created. The chronograph model highlights in purple the area where the threshold has been exceeded.

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Williams, Michael, Marcial Lamera, Aleksander Bauranov, Carole Voulgaris, and Anurag Pande. Safety Considerations for All Road Users on Edge Lane Roads. Mineta Transportation Institute, March 2021. http://dx.doi.org/10.31979/mti.2021.1925.

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Edge lane roads (ELRs), also known as advisory bike lanes or advisory shoulders, are a type of shared street where two-way motor vehicle (MV) traffic shares a single center lane, and edge lanes on either side are preferentially reserved for vulnerable road users (VRUs). This work comprises a literature review, an investigation of ELRs’ operational characteristics and potential road user interactions via simulation, and a study of crash data from existing American and Australian ELRs. The simulation evaluated the impact of various factors (e.g., speed, volume, directional split, etc.) on ELR operation. Results lay the foundation for a siting criterion. Current American siting guidance relies only upon daily traffic volume and speed—an approach that inaccurately models an ELR’s safety. To evaluate the safety of existing ELRs, crash data were collected from ELR installations in the US and Australia. For US installations, Empirical Bayes (EB) analysis resulted in an aggregate CMF of .56 for 11 installations observed over 8 years while serving more than 60 million vehicle trips. The data from the Australian State of Queensland involved rural one-lane, low-volume, higher-speed roads, functionally equivalent to ELRs. As motor vehicle volume grows, these roads are widened to two-lane facilities. While the authors observed low mean crash rates on the one-lane roads, analysis of recently converted (from one-lane to two-lane) facilities showed that several experienced fewer crashes than expected after conversion to two-lane roads.

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