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1
Empringham, Lee. "Matrix converter current commutation." Thesis, University of Nottingham, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.342443.
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Chen, Haoning (William). "LLC Resonant Current Doubler Converter." Thesis, University of Canterbury. Electrical and Computer Engineering, 2013. http://hdl.handle.net/10092/8492.
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The telecommunications market is one of the large rapidly growing fields in today’s power supply industry due to the increasing demand for telecom distributed power supply (DPS) systems. The half-bridge LLC (Inductor-Inductor-Capacitor) resonant converter is currently the most attractive topology for the design and implementation of 24V/48V DC telecom power converters. The current doubler rectifier (CDR) converter topology was invented and described in the early 1950s which can offer the unique characteristic of halving the output voltage while doubling the output current compared to a standard rectifier. In this thesis, the current doubler converter topology with its unique characteristic is evaluated as a complementary solution to improve the LLC resonant converter performance, especially for the low output voltage and high output current telecommunication applications. A novel half-bridge LLC resonant current doubler converter (LLC-CDR) is proposed in this thesis which can offer several performance benefits compared to conventional LLC-standard rectifier design . The unique characteristics of the LLC-CDR topology can offer significant improvements by transformation of a 48V converter into a 24V converter with the same power density. This thesis introduces a new SPICE-based simulation model to analyse the operation of this novel LLC-CDR converter circuit design. This model can be used to define the critical component parameters for the LLC -CDR circuit output inductor values. It can also be used to predict the circuit overall performance under different load conditions. Both time-domain based transient simulation analysis and frequency-domain based AC analysis provided by this simulation model showed favourable results in comparison to bench measurement results on a prototype. The model
provides a valuable insight to reveal some of the unique characteristics of this LLC -CDR topology. It demonstrates a proof of concept that the conventional LLC resonant
converter can be easily redesigned for low voltage, high current applications by using the LLC-CDR topology without requiring a new design for the LLC resonant stage components and the power transformer. A new magnetic integration solution was proposed to significantly improve the overall performance in the LLC-CDR topology that had not been published before. The LLC-CDR converter hardware prototypes with two output inductors coupled and uncoupled configurations were extensively modelled, constructed and bench tested.Test results demonstrated the suitability of an integrated coupled inductors design for the novel LLC-CDR converter application. The integrated coupled inductors design can significantly improve the LLC-CDR converter frequency-domain based AC simulation analysis results. In addition, these results also illustrate the potential benefit of how the magnetic integration design in general could reduce the magnetic component size, cost, and weight compared to the uncoupled inductors design. Finally, a hardware prototype circuit was constructed based on a commercial 1800 W single phase telecom power converter to verify the operation of this novel half bridge LLC-CDR topology. The converter prototype successfully operated at both no load and full load conditions with the nominal output voltage halved from 48VDC to 24VDC, and doubled the output current to match the same output power density. It also demonstrates that the efficiency of this novel half bridge LLC –CDR is 92% compares to 90% of EATON’s commercial 24VDC LLC resonant converter, which can fulfill the research goals.
3
Stihi, Omar. "Single phase controlled current PWM converter." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63844.
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Mai, Yuan Yen. "Current-mode DC-DC buck converter with current-voltage feedforward control /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20MAI.
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Kulkarni, Ashok. "Characteristics of a controlled current PWM converter." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66006.
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Nishimoto, Masahiro. "Analytical study of a controlled current PWM converter." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65432.
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Ho, Kwun-yuan Godwin, and 賀觀元. "A novel integrated synchronous rectifier for LLC resonant converter." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49618180.
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There is ever-increasing demand in telecommunication system, data server and computer equipment for low voltage, high current power supply. LLC resonant converter is a good topology on primary side of the converter because it has soft switching and resonant conversion. However, the passive rectifier in the secondary side has high power dissipation. Synchronous rectifier is a popular method to reduce this rectification loss. Although there are many types of synchronous rectifier for PWM converter, most of them do not function well in LLC resonant converters. It is because the wave form of LLC resonant converter is different from PWM. The objective of this research is to reduce the power dissipation and physical size at the same time.
In this thesis, a novel current driven synchronous rectifier with saturable current transformer and dynamic gate voltage control for LLC resonant Converter is presented. This novel circuit reduces the rectification loss and size of the current transformer in the synchronous rectifier. This synchronous rectifier has several outstanding characteristics compared with generic voltage driven and current driven synchronous rectifier. The saturable feature reduces the current transformer turns. Inherent dynamic gate voltage controlled by saturable current transformer reduces gate loss in the MOSFET. A novel driving circuit is proposed for accurate turn off time. It reduces loss significantly. This synchronous rectifier is completely self-contained which can replace the rectifier diode as a drop in replacement. It is insensitive to parasitic inductance. In order to explain the current transformer saturable, a model of saturable current transformer is proposed. A prototype demonstrates the advantages of the proposed current driven synchronous rectifier.
Furthermore, a novel integrated synchronous rectifier is presented which provides a more compact system. The synchronous rectifier current transformer is integrated with the main transformer which reduces the number of circuit joints in power path. Each soldering joint generates significance loss in power converter. A pair of 0.5mΩ soldering joint in 25A current path produces 0.62W loss. The placement of the integrated current transformer is important. A criterion for the placement of the current transformer within the main transformer is to avoid interference to the current transformer from the magnetic flux of the main transformer. Thus, a placement method to integrate the current transformer into the main transformer is proposed. An integrated current transformer model is suggested to explain the operation of the integrated synchronous rectifier. A prototype demonstrates the advantages of the integrated synchronous rectifier.published_or_final_version
Electrical and Electronic Engineering
Master
Master of Philosophy
8
Crowe, Robert A. "Design, construction and testing of a reduced-scale cascaded multi-level converter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Jun%5FCrowe.pdf.
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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003.Thesis advisor(s): Robert W. Ashton, John G. Ciezki, Douglas J. Fouts. Includes bibliographical references (p. 125-126). Also available online.
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McClusky, Scott Logan. "HIGH VOLTAGE RESONANT SELF-TRACKING CURRENT-FED CONVERTER." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/254.
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High voltage power supply design presents unique requirements, combining safety, controllability, high performance, and high efficiencies. A new Resonant Self-Tracking Current-Fed Converter (RST-CFC) is investigated as a proof-of-concept of a high voltage power supply particularly for an X-ray system. These systems require fast voltage rise times and low ripple to yield a clear image.
The proposed converter implements high-frequency resonance among discrete components and transformer parasitics to achieve high voltage gain, and the self-tracking nature ensures operation at maximum gain while power switches achieve zero-voltage switching across the full load range. This converter exhibits an inherent indefinite short-circuit capability. Theoretical results were obtained through simulations and verified by experimental results through a complete test configuration. Converter topology viability was confirmed through hardware testing and characterization.
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Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.
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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
11
Liu, Kwang-Hwa. "High-frequency quasi-resonant converter techniques." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/74737.
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Two waveform-shaping techniques to reduce or eliminate the switching stresses and switching losses in switching-mode power conversion circuits are developed: the zero-current switching technique and the zero-voltage switching technique.
Based on these two techniques two new families of quasi-resonant converters are derived. Since the stresses on semiconductor switching devices are significantly alleviated, these quasi-resonant (QRC) converters are suitable for high-frequency operations with much improved performances and equipment power density.
Employing the duality principle, the duality relationship between these two families of quasi-resonant converters are derived. The establishment of the duality relationship provides a framework allowing the knowledge obtained from one converter family to be readily transferred to the other.
Further topological refinements are derived through the utilization of parasitic elements in the devices and the circuit. In particular, the two most significant parasitic elements, the leakage inductance of the transformer and the junction capacitances of the semiconductor switch, are incorporated as part of the resonant-tank circuit required by these quasi-resonant converters. Consequently, the detrimental effects due to these parasitic elements are eliminated, and the converters can be operated at very high frequencies.Ph. D.
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Ho, Wing-choi. "Loss analysis and design of a novel soft switching converter /." Hong Kong : University of Hong Kong, 1997. http://sunzi.lib.hku.hk/hkuto/record.jsp?B18865501.
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Lee, John C. "Magamp post-regulator applied to a quasi-resonant converter and magamp operation under extreme load condition in a PWM converter." Thesis, This resource online, 1988. http://scholar.lib.vt.edu/theses/available/etd-11072008-063123/.
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Bland, Michael. "An investigation of matrix converter losses and soft switching techniques." Thesis, University of Nottingham, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.289478.
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Current research and the price of semiconductors are making Matrix Converter topologies more attractive and practically viable for many applications. One of the key benefits claimed for the matrix approach is the possibility of greater power density due to the absence of a DC link. To capitalise on this it is necessary to make the input filter small by having a sufficiently high switching frequency. In order to arrive at optimised solutions in terms of filtering, heatsinking and packaging, it is important to have accurate models to predict power circuit losses as a function of operating point and switching frequency. This aim of this thesis is to further the understanding of Matrix Converter current commutation with a focus on switching losses. The commutation process is analysed in detail and a complete loss model for Matrix Converter circuits is developed. The use of circuit simulation software in the prediction of switching losses is investigated and comparisons are made with experimentally measured results. The loss model is used to compare Matrix Converter losses with a functionally equivalent sinusoidal front end inverter. A review of soft switching techniques for Matrix Converter circuits is given. A new auxiliary resonant soft switching Matrix Converter is presented which overcomes many of the problems of the previously proposed circuits. The design, construction and testing of a 6kW prototype soft switching Matrix Converter is presented to evaluate the feasibility of the topology.
15
Lujara, Nelson Kakuru. "Construction and test of a SPWM current source converter." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59898.
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The thesis describes a stand-alone, unity power factor, current-regulated SPWM rectifier. The topology is based on the series connection of 3 single-phase, 4-valve rectifier bridges, which allows 2-state logic SPWM strategy to be used without interphase interference. The issues and problems of LdI$ sb{ rm dc}$/dt voltage and low harmonic waveform distortion are identified. Solutions are found by using a dc snubber circuit and a simple local notch filter feedback circuit which performs the dual function of stabilizing and active filtering. From the clarification given by this more expensive but less constrained topology, the stage is set for the next step in incorporating the lessons learnt here to the more economical topology based on the 6-valve, 3-phase parallel bridge, which requires a tri-state logic for PWM control when operating in the current-source configuration.
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Uster, Markus. "Current-mode analog-to-digital converter for array implementation /." [S.l.] : [s.n.], 2003. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=15252.
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Chen, Christine M. Eng Massachusetts Institute of Technology. "Integrated DC-DC converter with ultra-low quiescent current." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84879.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 93-94).
Based on the LTC3588, the design of a bandgap reference and a comparator for use in the control circuitry of DC-DC converter with an ultra-low quiescent current of 150nA is presented here. Not only will this thesis discuss the challenges encountered over the course of designing circuits to operate at such low current levels, but it will also provide proof of concept silicon evaluation data of modified LTC3588 chips demonstrating that such low current operation is viable.
by Christine Chen.
M.Eng.
18
Lentz, Nathan H. "A Modified Boost Converter with Reduced Input Current Ripple." DigitalCommons@CalPoly, 2017. https://digitalcommons.calpoly.edu/theses/1740.
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Battery-powered trends in consumer electronics, transportation, and renewable energy sectors increase demands on DC/DC converter technology. Higher switching frequency and efficiency reduces solution size and cost, while increasing power capabilities. Still, switching noise remains the primary drawback associated with any DC/DC converter. Reducing a converter’s input ripple helps prevent switching noise from spreading to other systems on a shared DC power bus. This thesis covers the analysis, simulation, and implementation of a recently-proposed boost converter topology, alongside an equivalent standard boost converter, operating in steady-state, continuous conduction mode. A Matlab-based simulation predicts each converter’s input ripple performance using a state-space model. The converters’ hardware implementation minimizes component and layout differences to create an equivalent comparison. The simulation and hardware measurements demonstrate a 40% input current ripple reduction using the modified topology. Replacing standard boost converters with the modified topology minimizes the switching noise conducted through a system’s DC power network.
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Yu, Jianghui. "DC Fault Current Analysis and Control for Modular Multilevel Converters." Thesis, Virginia Tech, 2016. http://hdl.handle.net/10919/78054.
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Recent research into industrial applications of electric power conversion shows an increase in the use of renewable energy sources and an increase in the need for electric power by the loads. The Medium-Voltage DC (MVDC) concept can be an optimal solution. On the other hand, the Modular Multilevel Converter (MMC) is an attractive converter topology choice, as it has advantages such as excellent harmonic performance, distributed energy storage, and near ideal current and voltage scalability.
The fault response, on the other hand, is a big challenge for the MVDC distribution systems and the traditional MMCs with the Half-Bridge submodule configuration, especially when a DC short circuit fault happens. In this study, the fault current behavior is analyzed. An alternative submodule topology and a fault operation control are explored to achieve the fault current limiting capability of the converter.
A three-phase SiC-based MMC prototype with the Full-Bridge configuration is designed and built. The SiC devices can be readily adopted to take advantage of the wide-bandgap devices in MVDC applications. The Full-Bridge configuration provides additional control and energy storage capabilities. The full in-depth design, controls, and testing of the MMC prototype are presented, including among others: component selection, control algorithms, control hardware implementation, pre-charge and discharge circuits, and protection scheme.
Systematical tests are conducted to verify the function of the converter. The fault current behavior and the performance of the proposed control are verified by both simulation and experiment. Fast fault current clearing and fault ride-through capability are achieved.Master of Science
20
Li, Qiang. "A single-phase dual output converter with high quality input waveforms." Lexington, Ky. : [University of Kentucky Libraries], 2003. http://lib.uky.edu/ETD/ukyelen2003t00111/thesislq.pdf.
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Thesis (M.S.)--University of Kentucky, 2003.Title from document title page (viewed Sept. 10, 2004). Document formatted into pages; contains xi, 128 p. : ill. Includes abstract and vita. Includes bibliographical references (p. 127-128).
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Jiang, Xu [Verfasser]. "Protection Schemes for Modular Multilevel Converter Based High Voltage Direct Current Transmission System Converters / Xu Jiang." Aachen : Shaker, 2019. http://d-nb.info/1188550845/34.
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Chen, Qing. "Analysis and design of multiple-output forward converter with weighted voltage control /." This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10032007-171757/.
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Chen, Wei. "Low Voltage High Current Power Conversion with Integrated Magnetics." Diss., Virginia Tech, 1998. http://hdl.handle.net/10919/30518.
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Very low voltage, high current output requirement have necessitated improvements in power supply's density and efficiency. Existing power conversion techniques cannot meet very stringent size and efficiency requirements. By applying the proposed magnetic integration procedure, new integrated magnetic circuits featuring low loss, simple structure, and ripple cancellation technique are then developed to overcome the limitations of prior art. Both cores and windings are integrated. Consequently, the power loss and the size of the integrated magnetic device are greatly reduced. Detailed analysis and design considerations of the proposed circuits are presented. As a result of applying the proposed technique, very high density, high efficiency, low voltage, high current power modules were developed. A typical example features an isolated 3.3V/30A power module with a power density of 130W/in3 and an efficiency of 90% at 500 KHz switching frequency.Ph. D.
24
Ye, Zhihong. "Modeling and Control of Parallel Three-Phase PWM Converters." Diss., Virginia Tech, 2000. http://hdl.handle.net/10919/29476.
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This dissertation studies modeling and control issues of parallel three-phase pulse-width modulated (PWM) converters. The converters include three-phase boost rectifiers, voltage source inverters, buck rectifiers and current source inverters.
The averaging of the parallel converters is performed based on a generic functional switching unit, which is called a phase leg in boost rectifiers and voltage source inverters, and a rail arm in buck rectifiers and current source inverters. Based on phase-leg and rail-arm averaging, the developed models are not only equivalent to the conventional three-phase converter models that are based on phase-to-phase averaging, but they also preserve common-mode information, which is critical in the analysis of the parallel converters. The models reveal such parallel dynamics as reactive power circulation and small-signal interaction.
A unique feature of the parallel three-phase converters is a zero-sequence circulating current. This work proposes a novel zero-sequence control concept that uses variable zero-vectors in the space-vector modulation (SVM) of the converters. The control can be implemented within an individual converter and is independent from the other control loops for the converter. Therefore, it greatly facilitates the design and expansion of a parallel system.
Proper operation of the parallel converters requires an explicit load-sharing mechanism. In order to have a modular design, a droop method is recommended. Traditionally, however, a droop method has to compromise between voltage regulation and load sharing. After parametric analysis, a novel droop method using a gain-scheduling technique is proposed. The numeric analysis shows that the proposed droop method can achieve both good voltage regulation and good load sharing.
An interleaving technique is often used in parallel converter systems in order to reduce current ripples. Because of its symmetrical circuit structure, the parallel three-phase converter system can reduce both differential-mode and common-mode noise with a center-aligned symmetrical SVM.
Based on the concept that a symmetrical circuit can reduce common-mode dv/dt noise, a conventional three-phase, four-leg inverter is modified so that its fourth leg is symmetrical to the other three legs. The common-mode dv/dt noise can be practically eliminated with a new modulation strategy. Meanwhile, with a modified control design, the new four-leg inverter still can handle low-frequency common-mode components that occur due to unbalanced and nonlinear load.Ph. D.
25
Sze, Ngok Man. "Switching converter techniques for energy harvesting applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20SZE.
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何永財 and Wing-choi Ho. "Loss analysis and design of a novel soft switching converter." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31237022.
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Law, Yiu-yip Charles, and 羅耀業. "Loss analysis of a stepping inductor VRM converter." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2003. http://hub.hku.hk/bib/B29477918.
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Saini, Dalvir K. "True-Average Current-Mode Control of DC-DC Power Converters: Analysis, Design, andCharacterization." Wright State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=wright1531776568809249.
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Lau, Wai Keung. "Current-mode DC-DC buck converter with dynamic zero compensation /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20LAU.
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Chang, Shan-Wen, and 張獻文. "Current-Mode Pipelined A/D Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/88821925942456651374.
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碩士逢甲大學
電機工程所
91
In recent days, the CMOS digital integrated circuits have been successfully utilized in many applications. It is highly relied on the data converters to improve the overall systems performance. In this thesis, a current-mode pipelined A/D converter (IADC) without sample-and-hold circuit is designed and analyzed. In the IADC architecture, each 1-bit pipelined stage consists of current-mirror circuits, one current comparator, and delay elements. This architecture can achieve a very high conversion rate due to the lack of sample/hold circuit. From HSPICE simulation results, the proposed IADC can achieve 6-bit accuracy with 280MHz sampling rate. The pipelined A/D converter is designed by using tsmc 0.35μm COMS 2P4M technology. It occupies an area of 0.556×0.658mm2 and has power consumption of 7.7mW from a 3.3-V supply.
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Lai, Chien-Hung, and 賴建宏. "Switched-Current Digital to Analog Converter." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/09696832865076703720.
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碩士國立臺北科技大學
電腦通訊與控制研究所
89
The switched-current digital to analog converter has the advantages of small chip size and low power dissipation compared with the other kinds of converters. Therefore, the proposed DAC in this thesis adopts this kind of architecture. Because usual switched-current D/A converters convert signals in serial-input way, their speeds are not pretty well. In order to improve this shortcoming our proposed DAC compromises between serial-input and parallel-input ways to speed up the conversion rate. In this thesis, we design and implement a 10-bit digital to analog converter with TSMC 0.35mm 1P4M CMOS process technology. Basically, the switched-current D/A converter is comprised of a 5-bit weighted current source and a current divider by 32. The major difference between our proposed DAC and other switched-current D/A converters is that we adopt a new algorithm named combined-input algorithm. The algorithm first deals with 5LSBs(b1~b5) and then 5MSBs(b6~b10) by adding the preceding result of 5LSBs. This architecture presents the reduction of the number of transistors, chip size and power consumption. With the loads of 200W and 5pF to our proposed D/A converter, the simulation results show that our proposed switched-current digital to analog converter occupies an area of 0.35mm2 and consumes a power of 26.1mW with the speed up to 31.25MS/s.
32
Liao, Shih-Chieh, and 廖士傑. "Low current, pulse-frequency modulation converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/86023484578794714759.
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碩士逢甲大學
電子工程所
92
In recent years, the CMOS integrated circuit technology has been successfully applied to a lot of systems. In order to provide efficient power for portable devices, the low voltage and low current circuits would be the trend for current CMOS development. To deal with faster and more complicated analog signals, most of research directions for pulse modulation circuits focus on the precise output waveform and fast response time. The design of pulse modulation circuit is in a mature stage now, however, due to the advance of process technology, how to achieve a low voltage, low power consumption, and fast response time is the main topic for my research. In this thesis, I will concentrate on the design of an accurate comparator, effective discharging route, as well as precise control of oscillator. This design is suitable for standard CMOS technology implementation and easy to make an IP circuit to use widely. From HSPICE simulation results, the operating frequency can achieve 200kHz and the operating voltage is 1.4V. The circuit of this thesis is designed by using tsmc 0.35μm CMOS 2P4M technology. It occupies an area of 0.438×0.391 mm2 and has a power consumption of 66μW from a 3.3V power supply.
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Shih, Li-Wei, and 施立緯. "Flyback Converter with Current Ripple Reduction." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/47er9a.
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碩士國立臺灣科技大學
電機工程系
103
Employing Power over Ethernet (PoE) technology, power devices (PDs), such as VoIP, security cameras and wireless LAN system node are thus powered over the cable without connecting to an AC source. Therefore, system reliability is increased and a DC-DC converter is built in the power device. Currently, flyback converter with RCD clamped topology is the most commonly used in power device due to it’s simple and low cost for PoE applications. To investigate the pros and cons, a thorough discussion will be provided in the chapter 2. However, it suffers from the power dissipations in the RCD network. It occupies precious space and degrades the power efficiency. To improve the efficiency, a lossless passive snubber circuit is used instead and a flyback converter with current ripple reduction (FYRR) topology for the PoE applications is proposed in this thesis. In addition to saving the RCD loss, it also has an input current ripple reduction function by utilizing the clamp capacitor and the leakage inductance of the transformer as an embedded notch filter. Consequently, the EMI noise level can be attenuated with smaller EMI filter components to meet the EMI regulation. In addition to the descriptions of the operation principle, theoretical analysis, and design considerations, two hardware circuits, the flyback with RCD snubber and the FYRR, with 250 kHz, 44-57V input and 12V/24W output specifications are built and tested.
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劉育廷. "Digital Current Mode DC-DC Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/91935440386309142214.
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William, Tuang. "An Improved Over Current Protection for Current Mode Controlled Converter." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0017-1901200710281463.
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Kuo, You-chen, and 郭祐辰. "Low Input Current Ripple LLC Converter with Current Doubler Rectifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/32846773820794366626.
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碩士國立臺灣科技大學
電機工程系
102
The LLC converter has several advantages, such as zero-voltage switching on the MOSFETs and zero-current switching on the rectifier diodes from no load to full load conditions, high efficiency, high power density, low EMI. However, the LLC converter lacks an output inductor resulting in having large current ripple of the output capacitor. Thus, numerous capacitors have to be connected in parallel to reduce the output voltage ripple. It limits the power density performance. To reduce the output voltage ripple, current doubler rectifier technique has been proposed. It offers a current ripple cancellation mechanism and reduces the rectifier current ripple. To apply this technique, LLC converter can meet the output voltage ripple with a small number of the output capacitor. Therefore, the power density can be increased. The LLC converter with current double rectifier (LLC-CD) is thus proposed in Chapter 2. However, the input current of LLC-CD is pulsating and causes the EMI problems. In general, larger input filter is added to meet the EMI regulation. It limits the power density performance. To reduce the input current ripple, an input ripple cancellation mechanism can be applied to the LLC-CD and input current ripple reduction LLC-CD (RR-LLC-CD) is thus proposed in Chapter 3. To inherit the advantages of its predecessor, the RR-LLC-CD has an additional built-in input current ripple reduction function. As a result, the EMI regulation can be met by using smaller EMI filter components. Consequently, higher power density can be achieved. In addition to the descriptions of the operation principle, theoretical analysis, and design considerations, three hardware circuits, the LLC-CT, the LLC-CD, and the RR-LLC-CD, with 300-400-V input and 12-V/240-W output specification are built and tested to demonstrate their feasibility.
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Tuang, William, and 唐永強. "An Improved Over Current Protection for Current Mode Controlled Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23955732617813190280.
Full textAbstract:
碩士中原大學
電機工程研究所
94
The UC384X series is a high performance fixed frequency current mode controllers especially design for off-line and DC−to−DC converter applications. It was used about two decades. Its integrated circuits feature a trimmed oscillator for precise duty cycle control, gain error amplifier, current sensing comparator, and a high current totem pole output for driving a power MOSFET. And it included a protective feature consisting of input and reference under-voltage lockouts each with hysteresis, cycle−by−cycle current limiting for output over current protection. Unfortunately, it needs to use lots of external circuits to achieve. In this thesis, a PWM controller has a saw-tooth limit for output power protection of DC-DC converter without input voltage compensation circuits is presented. This PWM controller will turn off its output when the current-sense signal of the PWM controller is higher than the reference saw-tooth limited voltage. At the mean while, this PWM controller has an excellent output power protection of DC-DC converter by a short delay time of current-sensing signal to its output. This feature makes external circuits of PWM controller simple and improves the mean time between failures (MTBF) of converter by decreasing part counts simultaneously. The experimental waveform and test result on a 5V/2A power board are shown to verify the feasibility of the proposal. The results are satisfactory.
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LIN, JIA-MING, and 林佳銘. "Buck Converter with Active-Current-Sensing Techniques and Hysteretic-Voltage-Controlled Buck Converter with Pseudo-Current-Sensing Techniques." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t6xmfj.
Full textAbstract:
碩士國立臺北科技大學
電子工程系
107
In the first converter, the active-current-sensing technique is used to sense the inductor current, which can reduce the glitch caused by switching. The proposed circuit not only performs with fast transient response time, but also improves the conversion efficiency. The first converter is implemented with TSMC 0.35-µm COMS process. The chip area is roughly 1.488×1.433 mm2, the input voltage is 3.3 V，and the output voltage varies from 1.0 V to 2.5 V, When the output voltage is 2.5 V and the output current is 200 mA, the highest efficiency is 87.2%. The second converter of the paper is the hysteretic-voltage-controlled buck converter with pseudo-current-sensing technique. This architecture of the proposed circuit is simple and easy to design. Compared with traditional converter circuit, the proposed comments are faster transient response, more stability, and reduce power consumption. TSMC CMOS 0.35-µm process is used to design converters. The chip area is 1.500×1.373 mm2, the input voltage is 3.3 V, and the output voltage ranges from 1.0 V to 2.5 V. When the output voltage is 2.5 V and the output current is 250 mA, the peak efficiency is roughly 90.6%.
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Maleki, Mohammad. "Current-mode flash analog-to-digital converter." Thesis, 1992. http://hdl.handle.net/1957/37347.
Full textAbstract:
This thesis describes the development of a flash analog-to-digital converter based on
current-mode technique. The advantages of current -mode technique are higher speed,
smaller chip area, and simple division of reference current based on current mirror. A
current-mode comparator is designed consisting of a cascode current mirror and a
current sense amplifier used as a latch. The new method allows effective and simple
high-speed A/D conversion where the input is a current signal and the output of the
latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using
current sense amplifier comparator is designed and simulated in 1-micron CMOS
technology. Simulation results show that for ADC with resolution below six-bit, this
technique offers a comparable accuracy with the existing voltage-mode methods at
much higher speed.Graduation date: 1993
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Lin, Jeff, and 林時毅. "Current-Cell Matrix Digital to Analog Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/27655992063157976458.
Full textAbstract:
碩士中華技術學院
電子工程研究所碩士班
96
This thesis proposes a new matrix digital to analog converter. All the results are simulated by TSMC 0.18m CMOS technology. The INL and DNL are 0.26 and 0.25 LSB for the 4 bit DAC, respectively. The INL and DNL are 0.23 and 0.25 LSB for the 8 bit DAC, respectively. The power consumption of 8-bit DAC is about 8.9mW. The proposed DAC also has advantages of simple encoder circuit to control current sources. It will decrease the size of circuit area. The DAC can also expand to more bit in the unit of 4 bits, for example, 8, 12 etc. It could be competitive with conventional matrix DAC.
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Wu, Ming-Shian, and 吳明憲. "A Linear CMOS Voltage to Current Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/42037852180078379348.
Full textAbstract:
碩士國立雲林科技大學
電子與資訊工程研究所
93
An improved CMOS voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the non-linear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. Consequently, the non-linearity of the large-signal transresistance of the converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. In order to compensate the resultant voltage inversion created by the switching from NMOS transistors to PMOS transistors in the resistor-replacement and voltage-level shifting in the proposed circuit, a voltage-inversion sub-circuit is devised and employed in our converter. The voltage-to-current converter is designed and fabricated in a 0.35μm CMOS technology. The fabricated circuit occupies an area of 267μm×197μm（~0.053mm2） and dissipates less than 3.92mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 input voltage, the total harmonic distortion (THD) of the output current is less than 1.5%.
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"Digitally Controlled Average Current Mode Buck Converter." Master's thesis, 2011. http://hdl.handle.net/2286/R.I.14481.
Full textAbstract:
abstract: During the past decade, different kinds of fancy functions are developed in portable electronic devices. This trend triggers the research of how to enhance battery lifetime to meet the requirement of fast growing demand of power in portable devices. DC-DC converter is the connection configuration between the battery and the functional circuitry. A good design of DC-DC converter will maximize the power efficiency and stabilize the power supply of following stages. As the representative of the DC-DC converter, Buck converter, which is a step down DC-DC converter that the output voltage level is smaller than the input voltage level, is the best-fit sample to start with. Digital control for DC-DC converters reduces noise sensitivity and enhances process, voltage and temperature (PVT) tolerance compared with analog control method. Also it will reduce the chip area and cost correspondingly. In battery-friendly perspective, current mode control has its advantage in over-current protection and parallel current sharing, which can form different structures to extend battery lifetime. In the thesis, the method to implement digitally average current mode control is introduced; including the FPGA based digital controller design flow. Based on the behavioral model of the close loop Buck converter with digital current control, the first FPGA based average current mode controller is burned into board and tested. With the analysis, the design metric of average current mode control is provided in the study. This will be the guideline of the parallel structure of future research.Dissertation/Thesis
M.S. Electrical Engineering 2011
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Shen, Cheng-Fu, and 沈承賦. "Implementation of Zero Current Transition Boost Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/16074326494288641683.
Full textAbstract:
碩士崑山科技大學
電機工程研究所
101
This thesis is focused on the design and implementation of a boost converter in discontinuous conduction mode (DCM) with zero current transition (ZCT) circuit. Due to the operation in DCM, the main switches turn-on occurs naturally under zero current and the reverse recovery losses of the output diodes are minimized. The use of auxiliary commutation circuits, which contains an active switch and a LC resonant circuit, provides ZCT at main switches during the turn-off period, minimizing the related turn-off losses. In this study, detailed operating principles, theoretical analysis, design guidelines and a design example of the ZCT boost converter are described and verified experimentally by a 300 W and 100 kHz prototype. Experiment results shown that ZCT boost converter has better efficiency than traditional boost converters with hard switching under heavy load.
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Yeh, Soung-Poul, and 葉松柏. "Flyback Converter with Current Ripple Reduction (FYRR)." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/30280155530000096555.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
98
Flyback converter with current ripple reduction (FYRR) is proposed and investigated in this thesis. The input current ripple reduction is achieved by utilizing the clamp capacitor and the leakage inductances of the transformer. Therefore, the EMI noise caused by the pulsating input current waveform can be reduced. Moreover, the EMI noise level can be further reduced by utilizing the clamp capacitor and the leakage inductance of the transformer as an embedded notch filter. To further improve the efficiency of the FYRR by utilizing a high-voltage switch cell, two-switch flyback converter with current ripple reduction (2SFYRR) is also proposed and investigated in this thesis. To demonstrate their feasibility, the operation principles as well as the experimental results with 150 kHz, 40-60V input and 5V/20A output are described in this thesis.
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Chen, Ping. "Soft-switched, power factor corrected, discontinuous current mode AC-to-DC boost converters and extension to interleaved converter." 2004. http://hdl.handle.net/1828/584.
Full text
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Chen, Chih-Chiang, and 陳志強. "Hysteresis-Current-Controlled Buck/ Buck-Boost Converter Using Active Current Sensing Circuit." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/7q3egk.
Full textAbstract:
碩士國立臺北科技大學
電腦與通訊研究所
94
In this thesis, We design a new active current sensing circuit and apply this technology fo hysteresis-current-controlled buck/buck-boost converter using active current sensing circuit for portable applications. In the proposed DC-DC converter, the key building blocks includes power MOS, Voltage-current conversion circuit, hysteresis-current comparator, driving circuit, non-overlapping circuit and current sensing circuit. The current sensing circuit can fully sense the inductor current and be used to construct buck/buck-boost converter. The hysteresis-current-controlled can be worked in parallel. The proposed circuits have been designed with TSMC 0.35um DPQM CMOS processes. The experimental results show that the buck/ buck-boost converter works well with the following features: the maximum inductor current up to 750mA; the input voltage range is 3~6V; the output voltage range from 0.45 to input voltage-0.4V; the maximum power efficiency up to 93.6%.
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Theron, Philippus Coenraad. "The partial series resonant converter." Thesis, 2014. http://hdl.handle.net/10210/10242.
Full textAbstract:
D.Ing. (Electrical and Electronic Engineering)increased dramatically during the past few years. This progress can mainly be attributed to recent developments in power electronic switching devices. Switching times are reduced, resulting in lower switching power loss, on-state voltage is reduced leading to lower conduction power losses, and higher voltage and current capabilities are possible. These advances are mainly responsible for a reduction in physical size of the converters, especially of the reactive components; an increase in dynamic response; and also, to a lesser extent, have an influence on the converter behaviour. Different applications of DC-DC converters require different characteristic behaviour, and the trend to obtain these different characteristics is usually accomplished by adding additional components to existing DC-DC converters. The disadvantage of such an approach is that it adds to the complexity of the converter topology and controller, and consequently increases the manufacturing cost, and reduces reliability. In this thesis, the objective is to identify a galvanic isolated DC-DC converter having inherent short circuit protection, sinusoidal transformer current, a low number of components and a simple controller. Hard switched DC-DC converters are approached from a fundamental point of view, weighing simplicity against characteristics, and a systematical classification is addressed. In order to address the issue of sinusoidal transformer current and inherent short circuit protection, a systematic classification of simple resonant converters is also addressed. The partial series resonant converter, which is a new converter topology, is identified and analysed. It does not follow the trend of increased converter and controller complexity with different characteristics, and meets all the objectives mentioned above. In addition to these objectives, it has the following characteristics: Output current can be controlled without any current measurement, while obtaining inherent short circuit protection. Switching losses are ultra low due to zero voltage switching at reduced turn-off current, enabling the use of insulated gate bipolar transistors at switching frequencies in excess of 50 kHz, which, among others, benefits dynamic response. The output load line resembles a natural constant output power load line at constant switchingfrequency. The combination of these characteristics is shown to provide major advances in low inductance load applications, such as arc welding and battery charging. Furthermore, all the magnetic components are integrated into one physical structure, which benefits, among others, manufacturability and cooling. The analysis and feasibility of the partial series resonant converter is verified by the construction of multi kilowatt prototypes for both battery charging and arc welding.
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HSU, WEI-CHIEH, and 徐葦婕. "A Hysteretic-Controlled Buck Converter with New Integral Current-Sensing Techniques and A Pseudo-Current-Controlled Buck Converter with Rail-to-Rail Current-Sensing Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/8g4w5p.
Full textAbstract:
碩士國立臺北科技大學
電子工程系
107
The thesis proposed two different current-sensing circuits and different controlled- mode buck converters. The first proposed converter is a hysteretic-control buck converter with new integral current-sensing techniques. Its controlled circuit uses hysteretic control to reduce transient-response time and use a new integrated current-sensing circuit to improve overall efficiency and reduce power loss. This chip has been fabricated with TSMC 0.35µm CMOS process and the chip area is 1.404×1.5 〖mm〗^2. The range of the input voltage is from 3V to 3.6V. The range of the output voltage is from 1V to 2.5V. When the output voltage is 2.5 V and the output current is 250 mA, the converter has the highest efficiency of 92.9%. The second chip is a pseudo-current-controlled buck converter with rail-to-rail current-sensing circuits. Its controlled circuit uses pseudo-current-controlled and rail-to-rail current-sensing techniques. The rail-to-rail current-sensing circuit does not produce current spike, and it can make the overall circuit more stable, and does not need to pass the voltage dividing resistor to reach a wider working rang. This chip has been fabricated with TSMC 0.35µm CMOS process and the chip area is 1.479×1.456 〖mm〗^2. The range of the input voltage is from 3V to 3.6V. The range of the output voltage is from 1V to 2.5V. When the output voltage is 2.5 V and the output current is 300 mA, the converter has the highest efficiency of 90.8%.
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邱士峰. "Quasi-Resonant Zero-Current Switch and Buck Converter with Current Feedback DC-DC Power Converter Implementation, Analysis and Controllers Design." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/34107209406684137381.
Full textAbstract:
碩士國立成功大學
工程科學研究所
85
In this dissertation, the linearized small signal mathematical models of a buck converter with current feedback and a unidirection zero current switch quasi-resonant converter (ZCS-QRC) are well established. Then, two kinds of controllers are designed to achieve desirable performance. For the buck converter with current feedback, the state space averaging method is employed to derive the linearized small-signal model for a PWM switching converter. Together with the algebraic constrained equation generated by current feedback, a generalized state space model is obtained. On the other hand, based on the derived model of the PWM switching converter, the mathematical model of a ZCS-QRC can be derived by taking into consideration of the behavior of the resonant circuit. With help of the models of two converters, robust controllers are designed to satisfy the specifications by applying the theory of Modified Integral Variable Structure Control (MIVSC). Finally, simulations and experiments are used to verify the feasibility of control theory of MIVSC.
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Hsieh, Li-Hsiung, and 謝禮雄. "Zero-Current-Switching Buck Converter for Battery Chargers." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54900046370594056741.
Full textAbstract:
碩士國立臺灣海洋大學
電機工程學系
100
The resonant converter provides the advantages of low switching losses, small circuit volume, light weight and high power density. Various high-frequency switching converters have replaced traditional hard -switching converters. This thesis presents zero-current-switching buck converter for battery chargers to control resonant converters flexibly. An auxiliary switch is inserted into the resonant loop in the proposed battery charger to control the resonant time precisely. The developed charger has the advantages of the hard-switching converter and the resonant converter with constant -frequency control, reduced resonant time and the operation of all switching components in the charger under the zero-current-switching condition to reduce significantly the switching losses. The developed charger circuit is highly suitable for high-frequency operation and high charging efficiency. This thesis employs the control mode for the switching of two active switches. The operation modes of the circuit and the equivalent circuits are constructed by analyzing the operating principles of the circuit, based on the turn-on conditions of the active switches. The equations used to determine the circuit parameters are derived from the equivalent circuits. Experimental results have demonstrated the theoretical effectiveness of the proposed battery charger circuit. A practical mean charging efficiency of over 90% is obtained.