Relevant bibliographies by topics / Current mode Flash ADC

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Current mode Flash ADC'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Current mode Flash ADC"

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Bhatia, Veepsa, and Neeta Pandey. "Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs." Journal of Electrical and Computer Engineering 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/8245181.

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A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lower currents and lower power dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a power supply of 1.8 V. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated.
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NESHANI, SARA, and SEYED JAVAD AZHARI. "A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H." Journal of Circuits, Systems and Computers 22, no. 08 (2013): 1350074. http://dx.doi.org/10.1142/s0218126613500746.

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In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.
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Jia, Hanbo, Xuan Guo, Xuqiang Zheng, et al. "A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process." Electronics 9, no. 10 (2020): 1733. http://dx.doi.org/10.3390/electronics9101733.

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This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.
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Rafika, Ageng Setiani, Sudaryono Sudaryono, and Wisnu Dwi Andoyo. "PROTOTYPE PERANCANGAN SISTEM OTOMATIS PEMBACA SUHU RUANGAN MENGGUNAKAN OUTPUT KIPAS DAN SENSOR LM35 BERBASIS MIKROKONTROLER ATMEGA 16." CCIT Journal 8, no. 2 (2015): 102–11. http://dx.doi.org/10.33050/ccit.v8i2.327.

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The fan is a tool that we usually find in everyday life. This is because the fan is a tool commonly used to lower the temperature or refrigerate something. However, the current use of the fan can be developed into a cooling device that can be controlled using an electronic device such as a microcontroller. Therefore we need a system for room temperature control in order to create a good temperature in conducting cooling system. Not just make the climate control, but also made the monitoring system. The data obtained from the LM35 temperature sensor is processed and then displayed in real time in the form of graphs and tables that can be seen by the computer using an LCD that can show the actual temperature in a room that has been installed LM35 sensor. Atmega16 microcontroller used is an 8-bit microcontroller which has a high capability and low power, in addition to all of the instructions executed in one clock cycle. AVR has 32 general-purpose registers, timer / counters flexible with compare modes, internal interrupt and power saving mode, the internal ADC and PWM. AVR also has in programmable system-on-chip flash program memory allows the system to be re-programmed using the serial SPI relationship.
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Jovanović, Jelena, and Dragan Denić. "Mixed-mode Method Used for Pt100 Static Transfer Function Linearization." Measurement Science Review 21, no. 5 (2021): 142–49. http://dx.doi.org/10.2478/msr-2021-0020.

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Abstract Pt100 is a resistance temperature detector characterized by a relatively linear resistance/temperature relationship in a narrow temperature range. However, the Pt100 sensor shows a certain degree of static transfer function nonlinearity of 4.42 % in the range between −200 °C and 850 °C, which is unacceptable for some applications. As a solution to this problem, a mixed-mode linearization method based on a special dual-stage piecewise linear ADC design is proposed in this paper. The first stage of the proposed dual-stage piecewise linear ADC is performed with a low-complex and low-power flash ADC of a novel sequential design. The novelty of the proposed sequential design is reflected in the fact that the number of employed comparators is equal to the flash ADC resolution. The second stage is performed with a delta-sigma ADC with a differential input and differential reference. Using the 6-bit flash ADC of novel design and the 24-bit delta-sigma ADC, the nonlinearity error is reduced to 2.6·10−3 %, in the range between −200 °C and 850 °C. Two more ranges are examined, and the following results are obtained: in the range between 0 °C and 500 °C, the nonlinearity error is reduced from 1.99 % to 5·10−4 %, while in the range between −50 °C and 150 °C, the nonlinearity error is reduced from 0.755 % to 2.15·10−4 %.
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JIA Hua-yu, 贾华宇, 刘丽 LIU Li, and 张建国 ZHANG Jian-guo. "Wide band current-mode amplifier for pipelined ADC." Optics and Precision Engineering 22, no. 10 (2014): 2855–60. http://dx.doi.org/10.3788/ope.20142210.2855.

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Nambiar, Neena, Benjamin J. Blalock, and M. Nance Ericson. "A novel current-mode multi-channel integrating ADC." Analog Integrated Circuits and Signal Processing 63, no. 2 (2009): 283–91. http://dx.doi.org/10.1007/s10470-009-9393-8.

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Handkiewicz, Andrzej, Marek Kropidłowski, Szymon Szczȩsny, and Mariusz Naumowicz. "ADC based on a fully differential current mode integrator." Analog Integrated Circuits and Signal Processing 100, no. 2 (2019): 327–34. http://dx.doi.org/10.1007/s10470-019-01456-4.

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Chen, Chun-Ying, Michael Q. Le, and Kwang Young Kim. "A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration." IEEE Journal of Solid-State Circuits 44, no. 4 (2009): 1041–46. http://dx.doi.org/10.1109/jssc.2009.2014701.

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Sugiura, Kazuhide, MyoengSoo Oh, and Kiyoharu Aizawa. "A Current Mode Successive Approximation ADC for Focal Plane Integration." IEEJ Transactions on Sensors and Micromachines 120, no. 8-9 (2000): 405–9. http://dx.doi.org/10.1541/ieejsmas.120.405.

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Dissertations / Theses on the topic "Current mode Flash ADC"

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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa<br>More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
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Baskaran, Balakumaar, and Hari Shankar Elumalai. "High-Speed Hybrid Current mode Sigma-Delta Modulator." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060.

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The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.
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Eilertsen, Bård Egil. "Current-Mode SAR-ADC In 180nm CMOS Technology." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-18820.

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This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented.
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Agarwal, Anuj. "Low-power current-mode ADC for CMOS sensor IC." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2706.

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A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate with very low duty cycle due to limited energy. Ideally these sensor networks will be massive in size and dense in order to promote redundancy. In addition the networks will be collectively intelligent and adaptive. To achieve these goals, distributed sensor networks will require very small,inexpensive nodes that run for long periods of time on very little energy. One component of such network nodes is an A/D converter. An ADC acts as a crucial interface between the sensed environment and the sensor network as a whole. The work presented here focuses on moderate resolution, and moderate speed, but ultra-low-power ADCs. The 6 bit current-mode algorithmic pipelined ADC reported here consumes 8 pJ/bit samples at 0.65V supply and 130 kS/s. The current was chosen as the information carrying quantity instead of voltage as it is more favorable for low-voltage and low-power applications. The reference current chosen was 150nA. All the blocks are using transistors operating in subthreshold or weak inversion region of operation, to work in low-voltage and low current supply. The DNL and INL plots are given in simulation results section. The area of the overall ADC was 0.046 mm2 only.
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Haaheim, Bård. "A sub-1µW, 16kHz Current-Mode SAR-ADC for Neural Spike Recording." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-14371.

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This thesis presents an ultra-low-power 8-bit asynchronous current-modesuccessive approximation (SAR) ADC for single channel neuron spike recording.The novel design exploits current mode operating in weak inversion forhigh power efficiency and is designed to operate at a 1.8V supply. The ADC isrunning at a 16kHz sampling frequency using under 1uW of power, thoughis adjustable using the featured calibration registers. A finished layout ispresented, occupying less than 0.078mm2. Linear operation through mismatchand process variations is obtained using a current calibration circuitconnected to both the current mode DAC and all the biases. This ensuresINL &lt; 0.5 and DNL &lt; 1, yielding no missing codes and a 3sigma productionyield. Calibration is needed because of the relatively large mismatch causedby sub-threshold operation of the current mirrors. The design also offers anewly developed current comparator with high resolution and fast settlingrelative to the current level and is completable with other state-of-the-art solutions,though still feature some voltage scaling issues left for future work.
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Shahzad, Khurram. "Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20314.

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<p>In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.</p><p>In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB.</p><p>The design is simulated in UMC 0.18um technology in Cadence environment. The choice of technology is made as the target application for the ADC, 'X-ray Detector System' is designed in the same technology. The simulation results obtained in-term of ENOB and power consumption are satisfactory for the target application.</p>
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Elkafrawy, Abdelrahman [Verfasser]. "Concept and design of a high speed current mode based SAR ADC / Abdelrahman Elkafrawy." Ulm : Universität Ulm, 2016. http://d-nb.info/1108434592/34.

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Silva, Alexandre Herculano Mendes. "Pipelined analog-to-digital conversion using current-mode reference shifting." Master's thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8265.

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Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores<br>Pipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs. To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power. The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step.
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Zatloukal, Tomáš. "Platforma pro ladění spínaných zdrojů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-433291.

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The following work deals with a design of power supply testbench with design of their replaceable modules and circuits for their measurement. The final product should be used for faster design and tuning of switching power supplies. In this essay, there is detailed description of switching power supplies, analysis of support circuits and calculations for design. Based on theoretical background and selected parameters, a connection concept will be created. This concept will be validated by a device that will consist of main board, changeable modules and measurement circuits.
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Zeman, Pavel. "Návrh a realizace pěti-úrovňového kvantovacího obvodu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218776.

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The work deals with design and realisation of the five-levels high-speed quantizer using switched-current technique (SI). The main aim is to use an advantage of switched-current technique like potential of the high-speed operation and to minimize disadvantages at all. Flash structure of the quantizer is used to ensure high-speed operation. It is supposed that the quantizer will be part of greater integrated systems such as higher-order delta-sigma modulators. Simulations are performed in CADENCE simulation tool using AMIS CMOS 0,7 µm technologic process.
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Books on the topic "Current mode Flash ADC"

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Maleki, Mohammad. Current-mode flash analog-to-digital converter. 1992.

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Maleki, Mohammad. Current-mode flash analog-to-digital converter. 1992.

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Book chapters on the topic "Current mode Flash ADC"

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Bedford, Kate. "Innovation Framing, Regulation, and User Adaptation Online." In Bingo Capitalism. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780198845225.003.0009.

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Chapter 8 explores the role of regulation in shaping the interface between online and land-based bingo. It locates discussion of online bingo within debates about whether regulation by code is replacing the rule of law, and whether virtual life undermines sociality and community, including through its role in monetizing social networks and exploiting users’ participation. The chapter also seeks to add an online component to existing accounts of place competition and gambling—focused mostly on casino resorts—by showing that the where of play remained a crucial element of the UK debate about online gambling. The remainder of the chapter narrows the focus to online bingo regulation, to better flesh out the distinctive lessons it holds for a study of rule-making, game standardization, and technology. It outlines the current regulatory system for online bingo, before turning to the role of users (workers, players, and land-based bingo operators seeking an online presence) in game adaptation. The chapter shows that the agency of workers and players to adapt products and practices varies significantly between online and offline forms of bingo. Because workers have limited connection to players in online bingo games, and the infrastructures upon which the bingo relies allow for so little user adaptation, the capacity to ‘re-playify’ the game is far more restricted, and the designers of the technology have significantly more power. Moreover, software providers are able to capture far more profit from instrumentalizing players’ social ties than is possible for land-based operators. The chapter concludes with a call to revisit the enthusiasm for straightforwardly pluralistic approaches to categorization and definition.
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Conference papers on the topic "Current mode Flash ADC"

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Sharma, Jyoti, Pallavi Bansal, Ayushi, and Veepsa Bhatia. "Design of 3-bit Current Mode Flash ADC." In 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2018. http://dx.doi.org/10.1109/rteict42901.2018.9012379.

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Chuenarom, S., S. Maitreechit, P. Roengruen, and V. Tipsuwampron. "Low Power Current-Mode Algorithmic ADC in Half Flash (BCD)." In APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/apccas.2006.342341.

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Goel, Aayush, Ankit Gupta, Maninder Kumar, Neeta Pandey, and Veepsa Bhatia. "Design of 3-bit current mode flash ADC using WTA based current comparator." In 2017 2nd International Conference on Telecommunication and Networks (TEL-NET). IEEE, 2017. http://dx.doi.org/10.1109/tel-net.2017.8343531.

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Bhatia, Veepsa, Mohini Madan, Baljeet Kaur, Neeta Pandey, and Asok Bhattacharyya. "A novel CC-II based current comparator and its application as current mode flash ADC." In 2013 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT). IEEE, 2013. http://dx.doi.org/10.1109/mspct.2013.6782122.

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Chang-Joon Park, Hemasundar Mohan Geddada, Aydin Ilker Karsilayan, Jose Silva-Martinez, and Marvin Onabajo. "A current-mode flash ADC for low-power continuous-time sigma delta modulators." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571802.

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Gupta, Navneet, Hitesh Shrimali, Adam Makosiej, Andrei Vladimirescu, and Amara Amara. "Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC." In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2021. http://dx.doi.org/10.1109/mwscas47672.2021.9531911.

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Vinayaka, Vikas, Sachin P. Namboodiri, Shadden Abdalla, et al. "Monolithic 8x8 SiPM with 4-bit Current-Mode Flash ADC with Tunable Dynamic Range." In GLSVLSI '19: Great Lakes Symposium on VLSI 2019. ACM, 2019. http://dx.doi.org/10.1145/3299874.3318005.

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He, Zhezhi, and Deliang Fan. "A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator." In ISLPED '16: International Symposium on Low Power Electronics and Design. ACM, 2016. http://dx.doi.org/10.1145/2934583.2934642.

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Krishna, Siva R., Maryam Shojaei Baghini, and Jayanta Mukherjee. "Current-mode CMOS pipelined ADC." In IEEE EUROCON 2009 (EUROCON). IEEE, 2009. http://dx.doi.org/10.1109/eurcon.2009.5167631.

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Pal, Suparno, and Dipankar Pal. "Modified Time-Based Current Mode ADC." In TENCON 2018 - 2018 IEEE Region 10 Conference. IEEE, 2018. http://dx.doi.org/10.1109/tencon.2018.8650441.

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