Dissertations / Theses on the topic 'Current mode Flash ADC'

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores<br>Pipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs. To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power. The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step.

The following work deals with a design of power supply testbench with design of their replaceable modules and circuits for their measurement. The final product should be used for faster design and tuning of switching power supplies. In this essay, there is detailed description of switching power supplies, analysis of support circuits and calculations for design. Based on theoretical background and selected parameters, a connection concept will be created. This concept will be validated by a device that will consist of main board, changeable modules and measurement circuits.

The work deals with design and realisation of the five-levels high-speed quantizer using switched-current technique (SI). The main aim is to use an advantage of switched-current technique like potential of the high-speed operation and to minimize disadvantages at all. Flash structure of the quantizer is used to ensure high-speed operation. It is supposed that the quantizer will be part of greater integrated systems such as higher-order delta-sigma modulators. Simulations are performed in CADENCE simulation tool using AMIS CMOS 0,7 µm technologic process.

The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most of the conventional CT ΔΣ ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ΔΣ ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.

This thesis describes the development of a flash analog-to-digital converter based on current-mode technique. The advantages of current -mode technique are higher speed, smaller chip area, and simple division of reference current based on current mirror. A current-mode comparator is designed consisting of a cascode current mirror and a current sense amplifier used as a latch. The new method allows effective and simple high-speed A/D conversion where the input is a current signal and the output of the latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using current sense amplifier comparator is designed and simulated in 1-micron CMOS technology. Simulation results show that for ADC with resolution below six-bit, this technique offers a comparable accuracy with the existing voltage-mode methods at much higher speed.<br>Graduation date: 1993

碩士<br>國立中興大學<br>電機工程學系<br>89<br>ABSTRACT In many applications, such as portable MP3 players, cellular phones, digital cameras, and other hand-held equipments, flash memories have been widely used as a media for mass storage of audio and video information. Similar to other memories, there is a growing demand for high-density, low-cost and low-power memory cells. Recently, the multilevel cell technique introduced by Intel Corp. realizing high capacity and low-cost flash memories, draw many people’s attention. In this work, we present a novel current mode sense amplifier for multilevel flash memories. The sensing scheme based on the parallel approach achieves high-speed and low power dissipation. A test chip of the circuit has been integrated in TSMC 1P3M 0.6mm process. The measurement results are tally with the simulation. In order to reduce operation voltage without decreasing the performance, we propose a new 1.8V current mode sensing mechanism instead of conventional voltage mode read circuit. This circuit greatly reduces the delay’s dependence on the supply voltage.

碩士<br>國立中興大學<br>電機工程學系<br>88<br>Abstract In recent years, several types of Flash memories have been proposed to enhance the density. Non-volatile memories storing more than one bit per cell are the attractive solution for semiconductor mass storage due to higher storage density without shrinking the memory cell. Therefore, the cost per bit and density can be reduced. To achieve n-bit-per cell storage, the number of distinguishable threshold levels in a cell should be m=2n. Hence, more complicated sensing architectures with short sensing time and high resolution are required to identify different levels. In this thesis, the full-custom design method was used to implement the new parallel current-mode multilevel identifying circuit to achieve high sensing speed at low supply voltage in small chip area. It was fabricated by TSMC 0.6mm SPDM process, and measured by HP4145、8110A 150Mhz pulse generator and oscilloscope. Two versions of high-speed parallel current-mode identifying circuit were proposed and verified by simulation and measurement. The time required to switch from one level to another level is about 3.5nsec by simulation and 5.5nsec by measurement for the first version. The second version with controlled clocks reaches 0.3nsec by simulation and reasonably agrees with the measurement.

碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>95<br>There are many different structures existed due to analog to digital converter using different sampling methods. The Flash Analog to Digital Converter (FLASH ADC) is the parallel structure used for low resolution which can provide better sampling performance. Using series of structure of Pipe-Lined ADC would increase higher resolution (more than 6-bits) and reduce the number of comparator and power consumption which was suitable for medium speed application. Sigma-delta modulator (SDM) became another modulation method to provide the high resolution for low speed application. In using was over-sampling and noise shaping techniques. This paper proposed a new structure of “Pseudo-Flash Current-Mode Analog to Digital Converter” which used well current tracking of current conveyer. The major circuit is altered from current conveyer such as current-mirror, current amplifier, current-mode sample-and-hold circuit. The new structure is same as pipe-lined ADC, but it is not alike all. The Pseudo-Flash like FLASH ADC can get all data in one clock cycle. All of the circuit has connected seven sample-stages and one reference current source. Each 1-bit/stage has included three current conveyers and one comparator. The whole circuit implemented with process of TSMC CMOS 0.35μm mixed-signal 2P4M polycide. The sampling rate is 12.5MHz, DNL is -0.38~+0.22LSB, INL is -0.08~+0.5LSB, respectively total power consumption and die size are 112.3mW and 1.208x1.351mm2.

Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area efficient, integrated sensor interface for applications like capacitance, temperature and dielectric-constant measurement. In addition, potential applica-tions for this work are in Cognitive Radios, Software Defined Radios, Capacitance Sensors, and location monitoring. The key contributions in the thesis are: 1 High Sensitivity Frequency-domain CMOS Capacitance Interface: A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. It exhibits a maximum sensitivity of 8.1 mV/fF across a 300 fF capacitance range. 2 Sensitivity Enhancement for capacitance sensor: The sensitivity of an oscillator-based differential capacitance sensor has been improved by proposing a novel frequency domain capacitance-to-voltage (FDC) measurement technique. The capacitance sensor interface system is fabricated in a 130-nm CMOS technology with an active area of 0.17mm2 . It exhibits a maximum sensitivity of 244.8 mV/fF and a measurement resolution of 13 aF in a 10-100 fF measurement range, with a 10 pF nominal sensor capacitance and an 8-bit ADC. 3 Frequency to Digital Converter for Time/Distance measurement: A new architecture for a Vernier-based frequency-to-digital converter (VFDC) for location monitoring is pre¬sented, in which, a time interval measurement is performed with a frequency domain approach. Location monitoring is a common problem for many mobile robotic applica¬tions covering various domains, such as industrial automation, manipulation in difficult areas, rescue operations, environment exploration and monitoring, smart environments and buildings, robotic home appliances, space exploration and probing. The proposed architecture employs a new injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital convert¬ers. It consumes 14.4 µW and 1.15 mW from 0.4 V and 1.2 V supplies, respectively. The proposed VFDC thus achieves a large detectable range, fine time resolution, small die size and low power consumption simultaneously. The measured time-difference error is less than 50 ps at 1.2 V, enabling a resolution of 3 mm/kHz frequency shift. 4 A bio-sensor array for dielectric constant measurement: A CMOS on-chip sensor is presented to measure the dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of a current controlled os¬cillator (CCO) upon the change of the sensor capacitance when exposed to the liquid. The CCO is embedded in an open-loop frequency synthesizer to convert the frequency change into voltage, which can be digitized using an off-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. 5 Integrated Temperature Sensor for thermal management: An integrated analog temper¬ature sensor which operates with simple, low-cost one-point calibration is proposed. A frequency domain technique to measure the on-chip silicon surface temperature, was used to measure the effects of temperature on the stability of a frequency synthesizer. The temperature to voltage conversion is achieved in two steps i.e. temperature to frequency, followed by frequency to voltage conversion. The output voltage can be used to com¬pensate the temperature dependent errors in the high frequency circuits, thereby reduc¬ing the performance degradation due to thermal gradient. Furthermore, a temperature measurement-based on-chip self test technique to measure the 3 dB bandwidth and the central frequency of common radio frequency circuits, was developed. This technique shows promise in performing online monitoring and temperature compensation of RF circuits.