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Journal articles on the topic 'Current mode Flash ADC'

Author: Grafiati

Published: 4 June 2021

Last updated: 8 February 2022

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1

Bhatia, Veepsa, and Neeta Pandey. "Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs." Journal of Electrical and Computer Engineering 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/8245181.

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A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lower currents and lower power dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS techn

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2

NESHANI, SARA, and SEYED JAVAD AZHARI. "A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H." Journal of Circuits, Systems and Computers 22, no. 08 (2013): 1350074. http://dx.doi.org/10.1142/s0218126613500746.

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In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size

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3

Jia, Hanbo, Xuan Guo, Xuqiang Zheng, et al. "A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process." Electronics 9, no. 10 (2020): 1733. http://dx.doi.org/10.3390/electronics9101733.

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This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in t

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4

Rafika, Ageng Setiani, Sudaryono Sudaryono, and Wisnu Dwi Andoyo. "PROTOTYPE PERANCANGAN SISTEM OTOMATIS PEMBACA SUHU RUANGAN MENGGUNAKAN OUTPUT KIPAS DAN SENSOR LM35 BERBASIS MIKROKONTROLER ATMEGA 16." CCIT Journal 8, no. 2 (2015): 102–11. http://dx.doi.org/10.33050/ccit.v8i2.327.

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The fan is a tool that we usually find in everyday life. This is because the fan is a tool commonly used to lower the temperature or refrigerate something. However, the current use of the fan can be developed into a cooling device that can be controlled using an electronic device such as a microcontroller. Therefore we need a system for room temperature control in order to create a good temperature in conducting cooling system. Not just make the climate control, but also made the monitoring system. The data obtained from the LM35 temperature sensor is processed and then displayed in real time

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5

Jovanović, Jelena, and Dragan Denić. "Mixed-mode Method Used for Pt100 Static Transfer Function Linearization." Measurement Science Review 21, no. 5 (2021): 142–49. http://dx.doi.org/10.2478/msr-2021-0020.

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Abstract Pt100 is a resistance temperature detector characterized by a relatively linear resistance/temperature relationship in a narrow temperature range. However, the Pt100 sensor shows a certain degree of static transfer function nonlinearity of 4.42 % in the range between −200 °C and 850 °C, which is unacceptable for some applications. As a solution to this problem, a mixed-mode linearization method based on a special dual-stage piecewise linear ADC design is proposed in this paper. The first stage of the proposed dual-stage piecewise linear ADC is performed with a low-complex and low-powe

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6

JIA Hua-yu, 贾华宇, 刘丽 LIU Li, and 张建国 ZHANG Jian-guo. "Wide band current-mode amplifier for pipelined ADC." Optics and Precision Engineering 22, no. 10 (2014): 2855–60. http://dx.doi.org/10.3788/ope.20142210.2855.

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7

Nambiar, Neena, Benjamin J. Blalock, and M. Nance Ericson. "A novel current-mode multi-channel integrating ADC." Analog Integrated Circuits and Signal Processing 63, no. 2 (2009): 283–91. http://dx.doi.org/10.1007/s10470-009-9393-8.

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Handkiewicz, Andrzej, Marek Kropidłowski, Szymon Szczȩsny, and Mariusz Naumowicz. "ADC based on a fully differential current mode integrator." Analog Integrated Circuits and Signal Processing 100, no. 2 (2019): 327–34. http://dx.doi.org/10.1007/s10470-019-01456-4.

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9

Chen, Chun-Ying, Michael Q. Le, and Kwang Young Kim. "A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration." IEEE Journal of Solid-State Circuits 44, no. 4 (2009): 1041–46. http://dx.doi.org/10.1109/jssc.2009.2014701.

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10

Sugiura, Kazuhide, MyoengSoo Oh, and Kiyoharu Aizawa. "A Current Mode Successive Approximation ADC for Focal Plane Integration." IEEJ Transactions on Sensors and Micromachines 120, no. 8-9 (2000): 405–9. http://dx.doi.org/10.1541/ieejsmas.120.405.

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11

Yong, Sun, Lai Fengchang та Ye Yizheng. "Current mode ADC design in a 0.5-μm CMOS process". Journal of Semiconductors 30, № 6 (2009): 065002. http://dx.doi.org/10.1088/1674-4926/30/6/065002.

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12

Faure, Nicolaas, and Saurabh Sinha. "High-speed Cherry Hooper flash analog-to-digital converter." Microelectronics International 34, no. 1 (2017): 22–29. http://dx.doi.org/10.1108/mi-08-2015-0075.

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Purpose The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies. Design/methodology/approach The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain b

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13

Zhang, Shuo, Zong Min Wang, and Liang Zhou. "An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC." Applied Mechanics and Materials 598 (July 2014): 365–70. http://dx.doi.org/10.4028/www.scientific.net/amm.598.365.

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This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total curr

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14

Yang, Jie, Yan Jun Yang, and Yun Zeng. "A 10bit 35MS/s Pipeline ADC with Low Power Consumption Applied in Medical Image Sensor." Advanced Materials Research 934 (May 2014): 193–98. http://dx.doi.org/10.4028/www.scientific.net/amr.934.193.

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In this paper, a Pipeline ADC applied in medical image sensor was designed, and the analog / digital operating voltage was 3.3/1.2V respectively, the area was 0.326mm2. Because the gain bootstrap op-amp structure has been improved and the dynamic comparator was used, which reduced the overall power consumption of the ADC. The simulation results showed that in the normal working mode, the total current of ADC was about 6.5 mA; when the sampling rate was lower than 17.5 MHz, the working mode was switched to the LP (low power) mode, and the total current was 4.5 mA. In addition, the tapeout test

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15

Seong-Won Kim and Soo-Won Kim. "Current-mode cyclic ADC for low power and high speed applications." Electronics Letters 27, no. 10 (1991): 818–20. http://dx.doi.org/10.1049/el:19910514.

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16

Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversi

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17

Chen, Zhenhai, Zongguang Yu, Jinghe Wei, Dejin Zhou, Xiaobo Su, and Jiaxuan Zou. "A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC." Journal of Semiconductors 38, no. 8 (2017): 085008. http://dx.doi.org/10.1088/1674-4926/38/8/085008.

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18

Shen, Xiao Feng, Rong Bin Hu, and Xi Chen. "A Novel R-2R Current-Mode DAC Used for Digital-Calibrated ADC." Advanced Materials Research 753-755 (August 2013): 2479–82. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2479.

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In this paper, a kind of novel DAC architecture is proposed. Compared to the traditional DAC architecture, the proposed is a multistage one. In order to improve precision, we use a kind of feedback bias circuit, which can minimize the effect of the base currents. A 16-bit DAC transistor-level circuit is implemented in 0.18um SiGe process. The simulation results show that the DAC using the proposed architecture has higher resolution, and better static and dynamic performances than the traditional one.

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19

SUNG, Guo-Ming, Leenendra Chowdary GUNNAM, Wen-Sheng LIN, and Ying-Tzu LAI. "A Third-Order Multibit Switched-Current Delta-Sigma Modulator with Switched-Capacitor Flash ADC and IDWA." IEICE Transactions on Electronics E100.C, no. 8 (2017): 684–93. http://dx.doi.org/10.1587/transele.e100.c.684.

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20

Li, Jiquan, Yingmei Chen, Pan Tang, Zhen Zhang, Hui Wang та Hao Huang. "A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS". Journal of Circuits, Systems and Computers 28, № 10 (2019): 1950167. http://dx.doi.org/10.1142/s0218126619501676.

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High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local

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21

Ono, Koichi, Masahiro Segami, and Masao Hotta. "A Current-Subtraction-Type Offset-Cancellation Technique for Comparator Circuit and its Application for Flash-Type ADC." IEEJ Transactions on Electronics, Information and Systems 129, no. 8 (2009): 1465–70. http://dx.doi.org/10.1541/ieejeiss.129.1465.

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22

Chang, Meng-Fan, Yu-Fan Lin, Yen-Chen Liu, et al. "An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros." IEEE Journal of Solid-State Circuits 50, no. 9 (2015): 2188–98. http://dx.doi.org/10.1109/jssc.2015.2424972.

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23

Choi, Seungnam, Yunjae Suh, Joohyun Lee, et al. "A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 7 (2017): 1706–17. http://dx.doi.org/10.1109/tcsi.2017.2676105.

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24

Real, P., D. H. Robertson, C. W. Mangelsdorf, and T. L. Tewksbury. "A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals." IEEE Journal of Solid-State Circuits 26, no. 8 (1991): 1103–9. http://dx.doi.org/10.1109/4.90063.

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25

Briseno-Vidrios, Carlos, Dadian Zhou, Suraj Prakash, et al. "A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs." IEEE Journal of Solid-State Circuits 53, no. 11 (2018): 3280–92. http://dx.doi.org/10.1109/jssc.2018.2863959.

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26

Hanfoug, Salah, Fateh Moulahcene, and Nour-Eddine Bouguechal. "Contribution to the Modeling and Simulation of Current Mode Pipeline ADC Based On Matlab." International Journal of Hybrid Information Technology 8, no. 3 (2015): 83–96. http://dx.doi.org/10.14257/ijhit.2015.8.3.09.

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27

Hung, Chung Wen, Li Sheng Zhang, and Lung Chu Lu. "A Digital Peak Current-Mode Control PFC with Bifurcation Control." Applied Mechanics and Materials 300-301 (February 2013): 1419–22. http://dx.doi.org/10.4028/www.scientific.net/amm.300-301.1419.

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A boost power factor correction (PFC) in continuous conduction mode (CCM) by the digital peak current-mode control method with bifurcation control is discussed in this paper. The proposed method is used to prevent the inductor current bifurcation behavior, which is caused by sub-harmonic oscillation when the duty cycle is upon to 50 percent. The bifurcation behavior will increase the inductor current ripple and dissipation, then reduce the Power Factor (PF). Different from the ramp compensation signal performed with analog IC in some papers, a MCU is used to be the controller and also provides

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28

Fan, Xiang Ning, Hao Zheng, Yu Tao Sun, and Xiang Yan. "Design and Implementation of a 12-Bit 100MS/s ADC." Applied Mechanics and Materials 229-231 (November 2012): 1507–10. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1507.

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In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to fur

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29

Pankiewicz, Bogdan. "Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors." Metrology and Measurement Systems 24, no. 1 (2017): 79–89. http://dx.doi.org/10.1515/mms-2017-0017.

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Abstract In this paper a programmable input mode instrumentation amplifier (IA) utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA), which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC). IA is designed in AMS 0.

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Esmailiyan, Ali, Filippo Schembari, and Robert Bogdan Staszewski. "A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 6 (2020): 1789–802. http://dx.doi.org/10.1109/tcsi.2020.2969804.

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31

Moon, Jong-Ho, Woo-Chul Jung, Jin-Tae Kim, Kee-Won Kwon, Young-Hyun Jun, and Jung-Hoon Chun. "A 2.0-GS/s 5-b Current Mode ADC-Based Receiver with Embedded Channel Equalizer." Journal of the Institute of Electronics and Information Engineers 49, no. 12 (2012): 184–93. http://dx.doi.org/10.5573/ieek.2012.49.12.184.

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32

Yunchu Li and E. Sanchez-Sinencio. "A wide input bandwidth 7-bit 300-msample/s folding and current-mode interpolating adc." IEEE Journal of Solid-State Circuits 38, no. 8 (2003): 1405–10. http://dx.doi.org/10.1109/jssc.2003.814429.

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33

Peric, Ivan, Tim Armbruster, Manuel Koch, Christian Kreidl, and Peter Fischer. "DCD – The Multi-Channel Current-Mode ADC Chip for the Readout of DEPFET Pixel Detectors." IEEE Transactions on Nuclear Science 57, no. 2 (2010): 743–53. http://dx.doi.org/10.1109/tns.2010.2040487.

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34

Park, Daejin. "Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method." Journal of Circuits, Systems and Computers 25, no. 07 (2016): 1650068. http://dx.doi.org/10.1142/s0218126616500687.

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The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binar

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35

S. Marathe, Dipak, and Uday P. Khot. "A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN." International Journal of Image, Graphics and Signal Processing 11, no. 11 (2019): 43–50. http://dx.doi.org/10.5815/ijigsp.2019.11.06.

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36

Hanfoug, Salah, Nour-Eddine Bouguechal, and Samir Barra. "Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADC by using Simulink." International Journal of u- and e-Service, Science and Technology 8, no. 3 (2014): 85–102. http://dx.doi.org/10.14257/ijunesst.2014.7.3.09.

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37

del Olmo, Rubén, Marta Mohedano, Beatriz Mingo, Raúl Arrabal, and Endzhe Matykina. "LDH Post-Treatment of Flash PEO Coatings." Coatings 9, no. 6 (2019): 354. http://dx.doi.org/10.3390/coatings9060354.

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This work investigates environmentally friendly alternatives to toxic and carcinogenic Cr (VI)-based surface treatments for aluminium alloys. It is focused on multifunctional thin or flash plasma electrolytic oxidation (PEO)-layered double hydroxides (LDH) coatings. Three PEO coatings developed under a current-controlled mode based on aluminate, silicate and phosphate were selected from 31 processes (with different combinations of electrolytes, electrical conditions and time) according to corrosive behavior and energy consumption. In situ Zn-Al LDH was optimized in terms of chemical compositio

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38

Yussouf, Nusrat, Katie A. Wilson, Steven M. Martinaitis, Humberto Vergara, Pamela L. Heinselman, and Jonathan J. Gourley. "The Coupling of NSSL Warn-on-Forecast and FLASH Systems for Probabilistic Flash Flood Prediction." Journal of Hydrometeorology 21, no. 1 (2020): 123–41. http://dx.doi.org/10.1175/jhm-d-19-0131.1.

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AbstractThe goal of the National Oceanic and Atmospheric Administration’s (NOAA) Warn-on-Forecast (WoF) program is to provide frequently updating, probabilistic model guidance that will enable National Weather Service (NWS) forecasters to produce more continuous communication of hazardous weather threats (e.g., heavy rainfall, flash floods, damaging wind, large hail, and tornadoes) between the watch and warning temporal and spatial scales. To evaluate the application of this WoF concept for probabilistic short-term flash flood prediction, the 0–3-h rainfall forecasts from NOAA National Severe

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39

Jain, Prateek, and Shyam Akashe. "Design and optimization of Flash type Analog to Digital converter using Augmented Sleep Transistors with Current Mode Logic." Radioelectronics and Communications Systems 56, no. 10 (2013): 472–80. http://dx.doi.org/10.3103/s0735272713100026.

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Huang, Chong-Cheng, Guo-Ming Sung, Xiong Xiao, Shan-Hao Sung, and Chao-Hung Huang. "Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive." Electronics 10, no. 7 (2021): 830. http://dx.doi.org/10.3390/electronics10070830.

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This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multipl

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Yau, Yeu-Torng, Kuo-Ing Hwu, and Jenn-Jong Shieh. "Applying FPGA Control with ADC-Free Sampling to Multi-Output Forward Converter." Electronics 10, no. 9 (2021): 1010. http://dx.doi.org/10.3390/electronics10091010.

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In this paper, a forward converter with multiple outputs is employed to build up a circuit system with full-digital control without any analog-to-digital (ADC) converter adopted. In this circuit, all the output voltages can be regulated by individual feedback control loops. As transient load variations due to the main output happens, the secondary outputs are affected quite slightly. Furthermore, the output voltage with the largest output current adopts not only the voltage mode control but also the interleaved control and current sharing control. Therefore, if this circuit system adopts full-

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42

You, Donggeun, Hyungseup Kim, Jaesung Kim, et al. "Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors." Applied Sciences 10, no. 1 (2020): 348. http://dx.doi.org/10.3390/app10010348.

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This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offset

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43

Wang, Ming-Shyan, Ika Noer Syamsiana, and Feng-Chi Lin. "Sensorless Speed Control of Permanent Magnet Synchronous Motors by Neural Network Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/321892.

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The sliding mode control has the merits with respect to the variation of the disturbance and robustness. In this paper, the sensorless sliding-mode observer with least mean squared error approach for permanent magnet synchronous motor (PMSM) to detect the rotor position by counter electromotive force and then compute motor speed is designed and implemented. In addition, the neural network control is also used to compensate the PI gain tuning to increase the speed accuracy without regarding the errors of the current measurement and motor noise. In this paper, a digital signal processor TMS320F2

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44

Кононов, Владимир, and Vladimir Kononov. "DESIGN FEATURES OF MULTI-BIT CMOS-CNI-ADC TO CREATE MULTI-CHANNEL HIGH-SPEED DSP SYSTEMS WITH INCREASED FAULT TOLERANCE." Modeling of systems and processes 12, no. 3 (2019): 59–64. http://dx.doi.org/10.12737/2219-0767-2019-12-3-59-64.

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The features and possibilities of using foreign and domestic foundry technologies in the creation of CMOS-ADC for high-speed multichannel DSP systems with increased fault resistance to the effects of TKCH are considered. The architecture and technique of ADC balancing, which provide an increase in the conversion rate when several ADCS operate in the alternating mode, are presented. The technique of double reservation of sources of «weight» currents is considered. The necessity of using an additional current source and dual series-connected CMOS transistors instead of single transistors of the

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A. Jyotsna, K., P. Satish Kumar, B. K. Madhavi, and I. Swaroopa. "Implementation of 16 Bit SAR ADC in CMOS and sub threshold cml techniques." International Journal of Engineering & Technology 7, no. 2.12 (2018): 257. http://dx.doi.org/10.14419/ijet.v7i2.12.11298.

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The trends of the VLSI technology is advancing, due to this majority of the industry players are showing interest in development of the devices with ultra low power applications. Analog-to-Digital converters are getting extensively used in Medical implant machines and in lots of Sensor machines, because it is serving an imperative role in interfacing between analog signal and digital signal. This paper presents a modernistic technique called as Sub threshold Current Mode Logic (CML) for ultra low power digital components. Here 16 bit SAR ADC is designed and compared with the techniques like CM

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Długosz, Rafał, and K. Iniewski. "Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks." VLSI Design 2007 (June 27, 2007): 1–13. http://dx.doi.org/10.1155/2007/45269.

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A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital converter (ADC) has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tuned to work with different sampling rates, number of bits of resolution, and power consumption levels. Due to its very low-power consumption and flexibility, the converter is particularly suitable for application in wireless sensor networks. Compared to other solutions presented in the literature, the proposed converter achieves very high figur

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Figueiredo, Michael, Edinei Santin, João Goes, Guiomar Evans, and Nuno Paulino. "A reference-free 7-bit 500 MS/s pipeline ADC using current-mode reference shifting and quantizers with built-in thresholds." Analog Integrated Circuits and Signal Processing 75, no. 1 (2013): 53–65. http://dx.doi.org/10.1007/s10470-013-0030-1.

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Kim, Sung Jin, Dong Gyu Kim, Seong Jin Oh, et al. "A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors." Sensors 19, no. 10 (2019): 2420. http://dx.doi.org/10.3390/s19102420.

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This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consump

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Moon, Kyoung-Jun, Dong-Shin Jo, Wan Kim, Michael Choi, Hyung-Jong Ko, and Seung-Tak Ryu. "A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS." IEEE Journal of Solid-State Circuits 54, no. 9 (2019): 2532–42. http://dx.doi.org/10.1109/jssc.2019.2926648.

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Thanachayanont, Apinunt. "A 1-V, 330-nW, 6-Bit Current-Mode Logarithmic Cyclic ADC for ISFET-Based $$p\!H$$ p H Digital Readout System." Circuits, Systems, and Signal Processing 34, no. 5 (2014): 1405–29. http://dx.doi.org/10.1007/s00034-014-9908-0.

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