Journal articles: 'Current reuse transconductance'

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Chary, Udari Gnaneshwara, and Kakarla Hari Kishore. "HSPICE simulation and analysis of current reused operational transconductance amplifiers for biomedical applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 1 (2025): 196. http://dx.doi.org/10.11591/ijece.v15i1.pp196-207.

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The proposed work focuses on the design of a current-reused biomedical amplifier; it is a microwatt-level electrocardiogram (ECG) analog circuit design that addresses low power consumption and noise efficiency. As implantable devices require unobtrusiveness and longevity, the current reuse technique in this circuit effectively enhances power and noise efficiencies. Using 90 nm technology enables efficient circuit implementation, yielding promising simulation results. At 100 Hz, the noise performance reaches 62.095 nV/√Hz, while the power consumption is only 8.3797 µW. These advancements are pivotal for next-generation implantable devices, ensuring reliable operation and reducing frequent battery replacements, improving patient convenience. Moreover, the high noise efficiency ensures that ECG signals are captured with high fidelity, crucial for accurate monitoring and diagnosis. This research addresses the challenges in implantable ECG analog circuit design and sets a benchmark for future developments. The techniques employed can be adapted for other bio signal monitoring devices, broadening the impact on healthcare technology. Ultimately, this advancement contributes to more efficient, reliable, and long-lasting medical devices, enhancing patient monitoring and healthcare on a broader scale.

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Muh-Dey Wei, Sheng-Fuh Chang, Shih-Wei Huang, Yung-Jhih Yang, and Renato Negra. "Investigation of Sub-Milliwatt Current-Reuse VCOs With Mono-Spontaneous Transconductance Match Technique." IEEE Transactions on Microwave Theory and Techniques 62, no. 2 (2014): 332–40. http://dx.doi.org/10.1109/tmtt.2013.2294604.

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Ma, Jintao, Jinhui Liang, Yanling Li, and Jiangping He. "A high-gain high-drive operational amplifier." Journal of Physics: Conference Series 2785, no. 1 (2024): 012004. http://dx.doi.org/10.1088/1742-6596/2785/1/012004.

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Abstract This paper presents a high-gain, high-drive operational amplifier based on the 0.18 μm technology. The first stage employs a current-reuse common-source common-gate structure to enhance gain, while the second stage utilizes a transconductance-enhanced push-pull output stage. This design achieves high-drive performance while retaining a high gain. Simulation using Cadence software demonstrates that, under a 5 V power supply voltage, the amplifier exhibits a low-frequency gain of 120 dB, with output sink and source current capabilities reaching 17.7 mA and 2.53 mA, respectively.

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Vitee, Nandini, Harikrishnan Ramiah, Wei-Keat Chong, Gim-Heng Tan, Jeevan Kanesan, and Ahmed Wasif Reza. "50 MHz–10 GHz Low-Power Resistive Feedback Current-Reuse Mixer with Inductive Peaking for Cognitive Radio Receiver." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/683971.

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A low-power wideband mixer is designed and implemented in 0.13 µm standard CMOS technology based on resistive feedback current-reuse (RFCR) configuration for the application of cognitive radio receiver. The proposed RFCR architecture incorporates an inductive peaking technique to compensate for gain roll-off at high frequency while enhancing the bandwidth. A complementary current-reuse technique is used between transconductance and IF stages to boost the conversion gain without additional power consumption by reusing the DC bias current of the LO stage. This downconversion double-balanced mixer exhibits a high and flat conversion gain (CG) of 14.9 ± 1.4 dB and a noise figure (NF) better than 12.8 dB. The maximum input 1-dB compression point (P1dB) and maximum input third-order intercept point (IIP3) are −13.6 dBm and −4.5 dBm, respectively, over the desired frequency ranging from 50 MHz to 10 GHz. The proposed circuit operates down to a supply headroom of 1 V with a low-power consumption of 3.5 mW.

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Abbasi, Arash, and Frederic Nabki. "A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications." Electronics 11, no. 9 (2022): 1493. http://dx.doi.org/10.3390/electronics11091493.

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This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130 nm CMOS technology and occupies an active area of 0.025 mm2. It achieves a wideband input matching of less than −10 dB from 0.8 GHz to 3.4 GHz. A conversion-gain of 39.5 dB, IIP3 of −28 dBm and a double-sideband (DSB) NF of 5.6 dB is simulated at a local-oscillator (LO) frequency of 2.4 GHz and an intermediate frequency (IF) of 10 MHz, while consuming 1.92 mA from a 1.2 V supply.

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Yin, Tao, Guocheng Huang, Xiaodong Xu, Yachao Zhang, Xinxia Cai, and Haigang Yang. "A 790 nW Low-Noise Instrumentation Amplifier for Bio-Sensing Based On Gm-RSC Structure." Journal of Circuits, Systems and Computers 27, no. 10 (2018): 1850157. http://dx.doi.org/10.1142/s0218126618501578.

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This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance ([Formula: see text]) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27[Formula: see text][Formula: see text]VRMS ([Formula: see text][Formula: see text]Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40[Formula: see text]dB. The common mode rejection ratio and power supply rejection ratio at 50[Formula: see text]Hz are 72 and 78[Formula: see text]dB, respectively. The IA consumes only 660[Formula: see text]nA current at 1.2[Formula: see text]V supply and the active area of the IA is only 0.035[Formula: see text]mm2.

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7

Chary, Udari Gnaneshwara, and Kakarla Hari Kishore. "HSPICE simulation and analysis of current reused operational transconductance amplifiers for biomedical applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 1 (2025): 196–207. https://doi.org/10.11591/ijece.v15i1.pp196-207.

Full text

Abstract:

The proposed work focuses on the design of a current-reused biomedicalamplifier; it is a microwatt-level electrocardiogram (ECG) analog circuitdesign that addresses low power consumption and noise efficiency. Asimplantable devices require unobtrusiveness and longevity, the current reusetechnique in this circuit effectively enhances power and noise efficiencies.Using 90 nm technology enables efficient circuit implementation, yieldingpromising simulation results. At 100 Hz, the noise performance reaches62.095 nV/√Hz, while the power consumption is only 8.3797 µW. Theseadvancements are pivotal for next-generation implantable devices, ensuringreliable operation and reducing frequent battery replacements, improvingpatient convenience. Moreover, the high noise efficiency ensures that ECGsignals are captured with high fidelity, crucial for accurate monitoring anddiagnosis. This research addresses the challenges in implantable ECG analogcircuit design and sets a benchmark for future developments. The techniquesemployed can be adapted for other bio signal monitoring devices, broadeningthe impact on healthcare technology. Ultimately, this advancement contributesto more efficient, reliable, and long-lasting medical devices, enhancingpatient monitoring and healthcare on a broader scale.

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8

Chong, Wei Keat, Harikrishnan Ramiah, and Nandini Vitee. "A 0.12-${\hbox{mm}}^{2} $ 2.4-GHz CMOS Inductorless High Isolation Subharmonic Mixer With Effective Current-Reuse Transconductance." IEEE Transactions on Microwave Theory and Techniques 63, no. 8 (2015): 2427–37. http://dx.doi.org/10.1109/tmtt.2015.2448073.

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9

Zhou, Ye, Wengao Lu, Shanzhe Yu, Dunshan Yu, Yacong Zhang, and Zhongjian Chen. "A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System." Journal of Sensors 2022 (October 3, 2022): 1–12. http://dx.doi.org/10.1155/2022/5304613.

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As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

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10

Chen, Xi, Taishan Mo, Peng Wu та Bin Wu. "A Capacitive-Feedback Amplifier with 0.1% THD and 1.18 μVrms Noise for ECG Recording". Electronics 13, № 2 (2024): 378. http://dx.doi.org/10.3390/electronics13020378.

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This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm2. The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mVpp output. The amplifier can provide a noise level of 1.18 μVrms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μVrms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

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11

Abbasi, Arash, and Frederic Nabki. "A Comparison of Off-Chip Differential and LC Input Matching Baluns in a Wideband and Low-Power RF-to-BB Current-Reuse Receiver Front-End." Electronics 11, no. 21 (2022): 3527. http://dx.doi.org/10.3390/electronics11213527.

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A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, requiring less area. The transimpedance amplifier (TIA) and low-noise transconductance amplifier (LNTA) share the bias current from a single supply to reduce power consumption. It employs both an active-inductor (AI) and a 1/f noise-cancellation technique to improve the NF and RF bandwidth performance. A passive mixer is utilized for RF to BB conversion, which does not require any DC power and voltage headroom. Both CRR1 and CRR2 are fabricated in TSMC 130 nm CMOS technology on a single die and packaged using a QFN48. CRR1 occupies an active area of 0.54 mm2. From 1 to 1.7 GHz, it achieves a conversion gain of 41.5 dB, a double-sideband (DSB) NF of 6.5 dB, S11<−10 dB, and an IIP3 of −28.2 dBm, while the local-oscillator (LO) frequency is at 1.3 GHz. CRR2 occupies an active area of 0.025 mm2. From 0.2 to 1 GHz, it achieves an average conversion gain of 37 dB, an average DSB NF of 8 dB, and an IIP3 of −21.5 dBm while the LO frequency is at 0.7 GHz. Both CRR1 and CRR2 consume 1.66 m from a 1.2 V supply voltage.

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12

Muh-Dey Wei, Sheng-Fuh Chang, and Shih-Wei Huang. "An Amplitude-Balanced Current-Reused CMOS VCO Using Spontaneous Transconductance Match Technique." IEEE Microwave and Wireless Components Letters 19, no. 6 (2009): 395–97. http://dx.doi.org/10.1109/lmwc.2009.2020035.

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13

Yin, Yue, Xinbing Zhang, Ziting Feng, et al. "An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing." Micromachines 15, no. 9 (2024): 1108. http://dx.doi.org/10.3390/mi15091108.

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In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the “current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs” structure, the bulk-driven pseudo-differential pair during the input common-mode range (ICMR) is stabilized and enhanced. The proposed OTA based on this technology is simulated using the TSMC 0.18 μm process in a Cadence environment. The proposed OTA consumes a power below 30 nW at a 0.4 V voltage supply with a DC gain of 54.9 dB and a gain-bandwidth product (GBW) of 14.4 kHz under a 15 pF capacitance load. The OTA has a high small signal figure-of-merit (FoM) of 7410 and excellent common-mode voltage (VCM) stability, with a transconductance variation of about 1.35%. Based on a current-scaling version of the proposed OTA, an OTA-C low-pass filter (LPF) for ECG signal processing with VCM stability is built and simulated. With a −3 dB bandwidth of 250 Hz and a power consumption of 20.23 nW, the filter achieves a FoM of 3.41 × 10−13, demonstrating good performance.

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Chang, Yu-Hsin, and Yong-Lun Luo. "CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures." Electronics 13, no. 2 (2024): 440. http://dx.doi.org/10.3390/electronics13020440.

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This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

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Li, Yi, Meiqi Xi, Xuehao Zhu, Lan Bai, Yu Cao, and Xuelei Liang. "High Quality Carbon Nanotube Thin Films for Transistor Application." ECS Meeting Abstracts MA2024-02, no. 35 (2024): 2436. https://doi.org/10.1149/ma2024-02352436mtgabs.

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Semiconducting carbon nanotubes (s-CNTs) are promising channel materials for both high-performance ultra-scaled field-effect transistors (FETs) and thin film transistors (TFTs) due to their excellent electronic properties. Many research groups have demonstrated the application of s-CNTs in either logical computing circuits or large area electronics. However, before the CNT-based electronics technology takes real impact, many challenges should be overcome, such as achieving high purity of s-CNTs, reliable methods for their deposition and alignment, development of scalable and cost-effective production techniques, and corresponding quality characterization metrology. In this presentation, we will report our progress on the s-CNT materials and their application for FETs and TFTs. Conjugated polymer wrapping method was used to extract s-CNTs from the raw CNT materials. We have developed a closed-loop recycling strategy, in which raw materials (CNTs and polymers) and solvents were all recycled and reused for multiple separation cycles, thus high-purity (99.9999%) and high structural quality s-CNTs were mass produced. The cost was reduced to ~ 1% in comparison with commercially available products, and total yield was increased to 36% in comparison with 2%–5% of usual separation methods. Highly unform and density-controllable thin films of random-oriented CNTs (R-CNTs) were fabricated by a dip-coating method on 4-inch/8-inch Si wafers and 2.5th generation (G2.5) backplane glasses (370 mm × 470 mm). Ultra-clean wafer-scale aligned s-CNTs (A-CNTs) were fabricated by a modified dimension-limited self-alignment (m-DLSA) method. To quantify the overall quality of both R-CNT and A-CNT films, we proposed a four-parameter metrology which includes the local tube density (DL), global density uniformity (Cv), local degree of order (OL), and the relative tube proportion in a certain orientation (Pθ) at a location. The four-parameter metrology is not only powerful for overall quality evaluation of CNT films, but also able to predict the performance fluctuation of fabricated devices. TFTs fabricated using the R-CNTs show mobility of 45-55 cm2/Vs with a high-performance uniformity (Cv ≈ 11%–13%) on a 4-inch wafer. A micro-LED display with 32×32 pixels were driven successfully by 2T1C AMTFT back plane based on R-CNT TFTs. Top-gated FETs based on A-CNTs exhibit excellent electronic performance with an on-state current (Ion) of 2.2 mA/μm, peak transconductance (gm) of 1.1 mS/μm, low contact resistance (Rc) of 191 Ω•μm and negligible hysteresis, among the best reported performance of CNT FETs. We believe our progress in the s-CNT materials will greatly push the CNT-based electronics technology into practical applications.

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Wu, Jingwei, Benqing Guo, Huifen Wang, Haifeng Liu, Lei Li та Wanting Zhou. "A 2.4 GHz 87 μW low-noise amplifier in 65 nm CMOS for IoT applications". Modern Physics Letters B, 24 вересня 2021, 2150485. http://dx.doi.org/10.1142/s0217984921504856.

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As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, [Formula: see text]-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based [Formula: see text]-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a [Formula: see text] power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 [Formula: see text]W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

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Zou, Wei, Lei Li, Zhengwang Cheng, et al. "A Four‐Core Dual‐Mode VCO With a Frequency Range of 19.92–40.17 GHz Using Current Reuse and Transconductance Unit Switching Techniques." International Journal of Circuit Theory and Applications, March 17, 2025. https://doi.org/10.1002/cta.4524.

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ABSTRACTA four‐core dual‐mode wideband voltage‐controlled oscillator (VCO) is proposed for 5G communication systems. The design features a novel complementary VCO structure, which differs from the traditional PMOS and NMOS complementary cross‐coupled structure. The fundamental oscillation unit is composed of transconductance units (Gmc units) and PMOS cross‐coupled pairs. Different oscillation modes are achieved by switching between different Gmc units, resulting in an extended tuning range. Current reuse techniques are employed to reduce the VCO's start‐up conditions and lower power consumption, thereby enhancing robustness. Using the 65‐nm CMOS process, the designed four‐core dual‐mode VCO achieves a frequency coverage of 19.92–40.17 GHz. The maximum power consumption is 14.22 mW, phase noise ranges from −112.60 to −101.64 dBc/Hz at a 1‐MHz offset, and FoMT varies from 198.28 to 205.84 dBc/Hz. The core area occupies 0.21 mm2.

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Bijari, Abolfazl, Fereshte Khoshbinahmadi, and Mohammad‐Amin Mallaki. "An ultra‐low‐power low‐noise amplifier using a combination of current reuse and self‐forward body bias techniques for biomedical applications." International Journal of Circuit Theory and Applications, June 16, 2024. http://dx.doi.org/10.1002/cta.4128.

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SummaryLow‐power low noise amplifiers (LNAs) are critical block in the radio frequency (RF) front‐end of medical device radiocommunications service (MedRadio) receivers for amplifying weak received signals while introducing minimal noise. Despite the inherently low transconductance of MOS transistors, it is possible to achieve low noise, high gain, and good linearity in low power LNAs. This paper presents a combination of techniques to realize an ultra‐low‐power LNA with a compact size and high performance. The proposed LNA utilizes multiple gm‐boosting and self‐forward body bias techniques, with certain transistors operating in weak inversion. Additionally, the Multi‐Objective Inclined Planes System Optimization algorithm is employed to determine the optimal values of the circuit components, thereby achieving the best compromise among the various performance parameters. The proposed LNA with buffer is designed and simulated using an 180 nm CMOS process over the frequency band of 0.3–1 GHz. Simulated results show that the proposed LNA achieves a gain of 19.6 dB, a noise figure of 5.1 dB, good input matching (S11 < −10 dB), and a third‐order intermodulation intercept point (IIP3) of 3.8 dBm. Additionally, it consumes 320 μW (without buffer) from a 1 V power supply, and the chip area is 235 μm × 372 μm. The simulated results demonstrate that the proposed ultra‐low power LNA is a promising candidate for biomedical applications.

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Guermaz, M. B., T. B. Berbar, B. Lehouidj, M. T. Belaroussi, and L. Bouzerara. "An Improved Comparator Based on Current Reuse and a New Frequency Compensation Technique used in an OTA for Pipeline ADCs." Journal of Circuits, Systems and Computers, April 17, 2021, 2150214. http://dx.doi.org/10.1142/s0218126621502145.

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In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35[Formula: see text][Formula: see text]m CMOS AMS process technology with [Formula: see text][Formula: see text]V supply voltage and an input common-mode range of [Formula: see text][Formula: see text]V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of [Formula: see text][Formula: see text]mV with [Formula: see text][Formula: see text]mV 3[Formula: see text] deviation, a slew rate of [Formula: see text]V/ns with [Formula: see text]V/ns 3[Formula: see text] deviation, and a propagation delay of [Formula: see text][Formula: see text]ns with [Formula: see text][Formula: see text]ns 3[Formula: see text] deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of [Formula: see text], and a high-gain of [Formula: see text]dB with [Formula: see text] and [Formula: see text]dB 3[Formula: see text], respectively, by using [Formula: see text] load capacitance.

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Mansour, Marwa, and Islam Mansour. "Battery‐free ultra‐low‐power radio‐frequency receiver for mm‐wave applications using 130‐nm CMOS technology with harvested DC supplies." International Journal of Circuit Theory and Applications, May 24, 2024. http://dx.doi.org/10.1002/cta.4101.

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SummaryThis paper presents a battery‐free ultra‐low‐power (ULP), highly integrated, and wide‐bandwidth low‐IF radio‐frequency (RF) receiver designed for millimeter‐wave (mm‐Wave) applications, utilizing 130‐nm CMOS technology. The suggested RF receiver is suitable for K‐band (n258) at 26 GHz, Ka‐band (n261 and n257) at 28 GHz, and the LMDS band at 28 GHz in fifth‐generation applications. The proposed radio receiver consists of a low‐noise driver stage implemented using a complementary current‐reuse common gate with an active shunt feedback configuration and an in‐phase/quadrature‐phase (I/Q) demodulator. The proposed RF receiver employs transformer coupling to isolate the DC path between the transconductance stage (RF stage) and the switching stage (IF stage). The driver stage expands the RF input impedance while maintaining acceptable linearity and gain with ultra‐low DC power dissipation. The DC supplies for the proposed mm‐Wave RF receiver are generated using two novel energy‐harvesting voltage doubler circuits to provide positive and negative voltages. The proposed mm‐Wave radio receiver consumes 0.475 mW from a 1.1 V DC supply and exhibits a power conversion gain (CG) of 6.3 dB, with a 3 dB frequency bandwidth extending from 22 to 32 GHz. The input 1‐dB compression point (P1dB) of the RF receiver is −2.65 dBm, and the input third‐order intercept point (IIP3) is 7.35 dBm. With a sensitivity of −66.5 dBm at a 100 MHz channel bandwidth and a dynamic range of 63.85 dB, the suggested receiver demonstrates notable performance characteristics. The proposed radio receiver boasts an excellent figure of merit (FoM) at 215 dB, surpassing published works by a margin of 8–31 dB. The primary positive supply voltage is derived from a double‐band positive voltage doubler with series resonance feedback and parallel resonance networks, efficiently achieving the desired DC voltage and output current (1.1 V and 450 μA). Meanwhile, the negative gate bias is provided by a negative voltage doubler, ensuring the necessary negative voltage (−0.5 V) without any current conditions.

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Journal articles on the topic 'Current reuse transconductance'

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