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Relevant bibliographies by topics / Current Starved Inverter

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Journal articles
Dissertations / Theses
Book chapters
Conference papers

Academic literature on the topic 'Current Starved Inverter'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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Journal articles on the topic "Current Starved Inverter"

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Cao, Yuan, Wenhan Zheng, Xiaojin Zhao, and Chip-Hong Chang. "An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function With Enhanced Temperature Stability." IEEE Access 7 (2019): 105287–97. http://dx.doi.org/10.1109/access.2019.2932022.

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Kurra, Anil, and Usha Nelakuditi. "Design of a Reliable Current Starved Inverter Based Arbiter Physical Unclonable Functions (PUFs) for Hardware Cryptography." Ingénierie des systèmes d information 24, no. 4 (October 10, 2019): 445–54. http://dx.doi.org/10.18280/isi.240413.

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Dash, Sandeep, Satya Mishra, and Nirmal Rout. "Design of efficient delay block for low frequency application." Facta universitatis - series: Electronics and Energetics 33, no. 3 (2020): 489–98. http://dx.doi.org/10.2298/fuee2003489d.

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In recent years researchers have been focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of 17MHz with a power consumption of 420?W.

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Liu, Chao Qun, Yuan Cao, and Chip Hong Chang. "ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 12 (December 2017): 3138–49. http://dx.doi.org/10.1109/tcsi.2017.2729941.

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Minati, Ludovico, Mattia Frasca, Natsue Yoshimura, Leonardo Ricci, Pawel Oswiecimka, Yasuharu Koike, Kazuya Masu, and Hiroyuki Ito. "Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades." IEEE Access 7 (2019): 54638–57. http://dx.doi.org/10.1109/access.2019.2912903.

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Yaacob, Nor Samida. "Low Power Ring Oscillator Design in 130nm CMOS Technology." Journal of Engineering and Science Research 3, no. 3 (June 28, 2019): 14–18. http://dx.doi.org/10.26666/rmp.jesr.2019.3.3.

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A temperature-stable, low-power ring oscillator design for implementation in an Application-Specific Integrated Circuit (ASIC) is presented. In this work, the design uses a new arrangement of chain delay elements consisting of a current-starved inverter and a CMOS capacitor. This power consumption improvement ring oscillator design was built in the environment of 130nm CMOS process technology using Mentor Graphics environment with voltage supply 1V. The simulation results show a maximum power consumption of 1.036 nW and it shows that the presented design is applicable in low power advanced sensing systems application including biomedical, chemical, and other sensors.

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Park, Sangwoo, and Sangjin Byun. "A 0.026 mm2 Time Domain CMOS Temperature Sensor with Simple Current Source." Micromachines 11, no. 10 (September 28, 2020): 899. http://dx.doi.org/10.3390/mi11100899.

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This paper presents a time domain CMOS temperature sensor with a simple current source. This sensor chip only occupies a small active die area of 0.026 mm2 because it adopts a simple current source consisting of an n-type poly resistor and a PMOS transistor and a simple current controlled oscillator consisting of three current starved inverter delay cells. Although this current source is based on a simple architecture, it has better temperature linearity than the conventional approach that generates a temperature-dependent current through a poly resistor using a feedback loop. This temperature sensor is designed in a 0.18 μm 1P6M CMOS process. In the post-layout simulations, the temperature error was measured within a range from −1.0 to +0.7 °C over the temperature range of 0 to 100 °C after two point calibration was carried out at 20 and 80 °C, respectively. The temperature resolution was set as 0.32 °C and the temperature to digital conversion rate was 50 kHz. The energy efficiency is 1.4 nJ/sample and the supply voltage sensitivity is 0.077 °C/mV at 27 °C while the supply voltage varies from 1.65 to 1.95 V.

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Kim, Jun-Tae, Bo-Ram Heo, and Ickjin Kwon. "An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors." Sensors 21, no. 4 (February 18, 2021): 1426. http://dx.doi.org/10.3390/s21041426.

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An ultralow-power ultrawideband (UWB) transmitter with an energy-efficient injection-locked radio frequency (RF) clock harvester that generates a carrier from an RF signal is proposed for RF energy-harvesting Internet-of-Things (IoT) sensor applications. The energy-efficient RF clock harvester based on the injection-locked ring oscillator (ILRO) is proposed to achieve optimal locking range and minimum input sensitivity to obtain an injection-locked 450 MHz clock in ultralow-power operation. A current-starved inverter-based delay stage is adopted that allows delay adjustment by bias voltage to minimize dynamic current consumption while maintaining a constant delay regardless of changes in process, supply voltage, and temperature (PVT). To minimize static current consumption, a UWB transmitter based on a digital-based UWB pulse generator and a pulse-driven switching drive amplifier is proposed. The proposed injection-locked RF clock harvester achieves the best RF input sensitivity of −34 dBm at a power consumption of 2.03 μW, enabling energy-efficient clock harvesting from low RF input power. In ultralow-power operation, a 23.8% locking range is achieved at the RF injection power of −15 dBm to cope with frequency changes due to PVT variations. The proposed UWB transmitter with RF clock harvester achieves the lowest energy consumption per pulse with an average power consumption of 97.03 μW and an energy consumption of 19.41 pJ/pulse, enabling operation with the energy available in RF energy-harvesting applications.

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Vázquez, Nimrod, Luz del Carmen García, Claudia Hernández, Eslí Vázquez, Héctor López, Ilse Cervantes, and Juan Iturria. "A Grid-Connected Multilevel Current Source Inverter and Its Protection for Grid-Disconnection." International Journal of Photoenergy 2013 (2013): 1–10. http://dx.doi.org/10.1155/2013/575309.

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Traditionally DC-AC converters are considered with voltage source inverters (VSI); although less studied and discussed, it has started recently to be used current source inverters (CSI). Another possibility for DC/AC conversion is the multilevel configuration. This paper shows experimental operation and simulation analysis of a grid-connected multilevel current source inverter (MCSI), which includes a circuit for equipment safety reasons due to grid disconnections.

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Nease, Stephen, Aaron Lanterman, and Jennifer Hasler. "Applications of Current-Starved Inverters to Music Synthesis on Field Programmable Analog Arrays." Journal of the Audio Engineering Society 66, no. 1/2 (February 14, 2018): 71–79. http://dx.doi.org/10.17743/jaes.2017.0044.

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Dissertations / Theses on the topic "Current Starved Inverter"

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Liu, Jingbo. "Modeling, analysis and design of integrated starter generator system based on field oriented controlled induction machines." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1132763176.

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Bautista, Harold H. 1979. "Performance analysis of different voltage controlled delay lines in a delay-locked loop." Thesis, 2012. http://hdl.handle.net/2152/ETD-UT-2012-05-5416.

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Bus interfaces keep getting faster and thus requiring designers to build custom physical fabrics that are able to delay clock and(or) data, on their transmitter and receivers, in order to properly receive and send data with enough setup and hold times. Delay locked loops (DLLs) have become fundamental building blocks that address such problems. Not only are they present in physical layers in integrated circuits but they also solve the problem of VLSI systems that suffer from clock skew and jitter. This report focuses on the implementation of a standard DLL and three different voltage controlled delay topologies. The different topologies are designed and compared for metrics such as linearity, delay range, and sensitivity to power supply.
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Thulukkameetheen, Mohideen Raiz. "Highly Linear Current to Delay converter and its application in ADC design." 2014. http://hdl.handle.net/10222/44103.

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In this work a low voltage and highly linear current-mode current to delay (CTD) converter is presented. The proposed current to delay converter has the improved linearity of about 23.5% when compared with a conventional–delay inverter over the input dynamic current range of 50µA. When used as front-end block in current-mode delay-mode analog to digital converter an 11-bit resolution is obtained. The design is implemented in TSMC 90 nm CMOS technology. Monte Carlo analysis and process corner analysis is performed on the proposed circuit to analyze the amount of mismatch that will degrade the performance of the circuit in a system level. A Process, Voltage, and Temperature (PVT) variation insensitive circuit is used to bias the designed CTD converter to obtain 57% reduction of variation when compared with the simple current mode biasing technique.

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Book chapters on the topic "Current Starved Inverter"

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Bindu Katikala, Hima, and G. Ramana Murthy. "A Design of Current Starved Inverter-Based Non-overlap Clock Generator for CMOS Image Sensor." In Algorithms for Intelligent Systems, 115–23. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2248-9_12.

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Conference papers on the topic "Current Starved Inverter"

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Mokhtar, Siti Musliha Ajmal Binti, and Wan Fazlida Hanim Wan Abdullah. "Memristor based delay element using current starved inverter." In 2013 IEEE Regional Symposium on Micro and Nanoelectronics (RSM). IEEE, 2013. http://dx.doi.org/10.1109/rsm.2013.6706478.

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Liu, Chao Qun, Yuan Cao, and Chip-Hong Chang. "Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFs." In 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2016. http://dx.doi.org/10.1109/apccas.2016.7804080.

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Wilson, W., T. Chen, and R. Selby. "A current-starved inverter-based differential amplifier design for ultra-low power applications." In 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS). IEEE, 2013. http://dx.doi.org/10.1109/lascas.2013.6519040.

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Kumar, Raghavan, Vinay C. Patil, and Sandip Kundu. "Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain." In 2011 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2011. http://dx.doi.org/10.1109/isvlsi.2011.82.

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Azadmehr, Mehdi, and Yngvar Berg. "Cascade of Current-Starved Pseudo Floating-Gate inverters." In 2008 15th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2008). IEEE, 2008. http://dx.doi.org/10.1109/icecs.2008.4675032.

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Fouad, Ahmed, Yehea Ismail, and Hassan Mostafa. "Design of a time-based capacitance-to-digital converter using current starved inverters." In 2017 29th International Conference on Microelectronics (ICM). IEEE, 2017. http://dx.doi.org/10.1109/icm.2017.8268882.

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Lyu, Yinxuan, Jianhua Feng, Hongfei Ye, Chunhua He, and Dunshan Yu. "A 0.32uW physically unclonable fuction with BER <1.18E-5 using current starved inverters." In 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2016. http://dx.doi.org/10.1109/edssc.2016.7785263.

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Azadmehr, Mehdi, and Yngvar Berg. "Bi-directional Band pass / Band stop filter based on Current-Starved Pseudo Floating-Gate inverters." In 2008 NORCHIP. IEEE, 2008. http://dx.doi.org/10.1109/norchp.2008.4738294.

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Musumeci, Salvatore, Filippo Scrimizzi, Filadelfo Fusillo, Radu Bojoi, Giuseppe Longo, and Carmelo Mistretta. "Low Voltage High Current Trench-Gate MOSFET Inverter for Belt Starter Generator Applications." In 2019 AEIT International Conference of Electrical and Electronic Technologies for Automotive (AEIT AUTOMOTIVE). IEEE, 2019. http://dx.doi.org/10.23919/eeta.2019.8804598.

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Kim, Sang Min, and Taesuk Kwon. "A Method to Minimize Current Ripple of DC Link Capacitor for 48V Inverter Integrated Starter/Generator." In 2018 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2018. http://dx.doi.org/10.1109/ecce.2018.8557935.

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