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Journal articles on the topic 'Current Steering DAC'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 April 2022

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1

Dai, Lan, Guo Zhi Xu, and Ke Qing Ning. "Dynamic-Performance-Improved Algorithm for 14 Bits 200MHz Current-Steering DAC." Applied Mechanics and Materials 380-384 (August 2013): 1721–24. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.1721.

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Performance of high-speed and high-resolution current-steering DAC is hardly suffered from non-ideal factors such as current-steering source mismatches. This paper presents a dynamic performance improved algorithm for current sources selection of current-steering DAC, the most attractive features of the algorithm are random direction and random origination address during current sources selection. The simulation results show this algorithm enhances randomness during current sources selection and exhibits better dynamic performance than many other methods.

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2

Patel, Jayeshkumar J., and Amisha P. Naik. "Design and implementation of 4 bit binary weighted current steering DAC." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 6 (December 1, 2020): 5642. http://dx.doi.org/10.11591/ijece.v10i6.pp5642-5649.

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A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

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3

Zurita, Marcos E. P. V., Loick Le Guevel, Gerard Billiot, Adrien Morel, Xavier Jehl, Aloysius G. M. Jansen, and Gael Pillonnet. "Cryogenic Current Steering DAC With Mitigated Variability." IEEE Solid-State Circuits Letters 3 (2020): 254–57. http://dx.doi.org/10.1109/lssc.2020.3013443.

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4

XIA, FAN, YIQIANG ZHAO, and GONGYUAN ZHAO. "A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION." Journal of Circuits, Systems and Computers 23, no. 04 (April 2014): 1450053. http://dx.doi.org/10.1142/s0218126614500534.

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In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

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5

Mathurkar, Piyush K. "CMOS 8-Bit Binary Type Current-Steering DAC." International Journal of Embedded Systems and Applications 2, no. 3 (September 30, 2012): 67–74. http://dx.doi.org/10.5121/ijesa.2012.2307.

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6

Shimizu, Akio, Takuro Noguchi, Yohei Ishikawa, and Sumio Fukai. "Current-Steering DAC for Urinary Bladder Volume Measurement." IEEJ Transactions on Electronics, Information and Systems 139, no. 5 (May 1, 2019): 632–33. http://dx.doi.org/10.1541/ieejeiss.139.632.

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7

Rekha, P., and N. Vijayanandam. "High Resolution Display Systems Using Current-Steering DAC." i-manager's Journal on Electronics Engineering 4, no. 2 (February 15, 2014): 28–33. http://dx.doi.org/10.26634/jele.4.2.2623.

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8

Tafir Mustaffa, Mohd, Yong Cheng Lim, and Choon Yan Teh. "Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN)." Indonesian Journal of Electrical Engineering and Computer Science 5, no. 3 (March 1, 2017): 643. http://dx.doi.org/10.11591/ijeecs.v5.i3.pp643-649.

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DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. Thus, in this research, a new DEM algorithm is proposed on Current-Steering DAC with Partial Binary Tree Network (PBTN) algorithm that utilizes a lower complexity circuit to produce output signals with less glitches. Simulation results for 6-bit 1-MSB PBTN DAC produces 0.3184LSB of DNL, 0.0062LSB of INL, and a power consumption of 14.13 mW, while using only 126 transmission gates.

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9

Li, Weng Yuan, and Teng Xiao Jiang. "A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit." Applied Mechanics and Materials 513-517 (February 2014): 4555–58. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4555.

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In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

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10

Bramburger, Stefan, and Dirk Killat. "10-bit tracking ADC with a multi-bit quantizer, variable step size and segmented current-steering DAC." Advances in Radio Science 17 (September 19, 2019): 161–67. http://dx.doi.org/10.5194/ars-17-161-2019.

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Abstract. This paper presents a 10-bit tracking ADC using a multi-bit quantiser and a segmented current-steering DAC. The quantiser allows a dynamical adjustment of the step size dependent on the input signal waveform. This mitigates the limited slew rate of delta encoded ADCs. Energy consumption induced by 1 LSB ripple is removed by the quantiser. The segmented current-steering DAC allows simple control, good monotonicity and improved transient response when compared to previous design as well as potential power reduction.

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11

Xue, Xiao Bo, Hong Wei Si, Qi Feng Shi, and Le Nian He. "A 12-Bit 1GS/s Current-Steering DAC with Matching Capacitor in Switched Current Cell." Advanced Materials Research 588-589 (November 2012): 944–47. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.944.

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This paper presents a 12-bit 1GS/s current-steering DAC with matching capacitor in switched current cell, which has been designed to enhance the DAC’s dynamic performance. Compared with traditional designs, the switched current cell with an matching capacitor can suppress the output-dependent delay differences effect. The Chip was designed by using TSMC 0.18μm CMOS mixed model, and the post-simulation results show that the DAC achieves 74.1 and 68.9 dBc SFDR at 1GS/s with 50MHz and 450MHz output frequency, respectively.

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12

Stoops, David J., Jenny Kuo, Paul J. Hurst, Bernard C. Levy, and Stephen H. Lewis. "Digital Background Calibration of a Split Current-Steering DAC." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 8 (August 2019): 2854–64. http://dx.doi.org/10.1109/tcsi.2019.2901626.

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13

Razavi, Behzad. "The Current-Steering DAC [A Circuit for All Seasons]." IEEE Solid-State Circuits Magazine 10, no. 1 (2018): 11–15. http://dx.doi.org/10.1109/mssc.2017.2771102.

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14

Monfaredi, Khalil, and Sara Jan Mohammadi. "Dynamic Foreground Calibration of Binary-Weighted Current-Steering DAC." Iranian Journal of Science and Technology, Transactions of Electrical Engineering 43, no. 4 (April 23, 2019): 699–716. http://dx.doi.org/10.1007/s40998-019-00198-3.

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15

Kwon, Chan-Keun, Junil Moon, and Soo-Won Kim. "A 12-Bit 500-MS/s Current Steering CMOS DAC for High-Speed PLC Modems." Journal of Circuits, Systems and Computers 25, no. 10 (July 22, 2016): 1650122. http://dx.doi.org/10.1142/s021812661650122x.

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A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-[Formula: see text]m CMOS process with an active area of 2.445[Formula: see text]mm2, which achieves a differential non linearity (DNL) of 0.25[Formula: see text]LSB and an integral non-linearity (INL) of 0.19[Formula: see text]LSB. Additionally, the SFDR increases by 13.2[Formula: see text]dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176[Formula: see text]mW from a 1.8-V supply voltage.

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16

Tian, Y., P. Yang, Q. Wang, W. Zhou, X. Niu, J. Huang, and C. Zhao. "Development of an on-chip configurable DAC module for monolithic active pixel sensor." Journal of Instrumentation 17, no. 03 (March 1, 2022): C03006. http://dx.doi.org/10.1088/1748-0221/17/03/c03006.

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Abstract This paper describes an on-chip configurable Digital to Analog Converter (DAC) module for monolithic active pixel sensor. The DAC module consists of four 10-bit voltage DACs, seven 8-bit current DACs, a bandgap circuit, and a configure interface. The voltage DAC is implemented with an R-2R resistor ladder network, and each LSB corresponds to 3 mV. The current DAC is in the current-steering type with a thermometer code. Each LSB of the current DAC corresponds to 10 nA. The bandgap circuit provides a stable, temperature-independent reference voltage of 1.25 V to the DACs. All the DACs can be accessed and configured with the configure interface. The DAC module covers 3074 µm × 400 µm, and the total power consumption is 46.2 mW. This paper will discuss the design and performance of this DAC module.

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17

Nagpara, Bharat H. "A 45 nm 6 Bit Low Power Current Steering Digital to Analog Converter Using GDI Logic." TELKOMNIKA Indonesian Journal of Electrical Engineering 16, no. 1 (October 1, 2015): 46. http://dx.doi.org/10.11591/tijee.v16i1.1586.

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<p><strong><em> </em></strong>In this paper, The Design and Implementation low power Current Steering Digital to Analog Converter in 45 nm technology using GDI Logic using TANNER TOOL, V15 is presented. This architecture gives the most optimized results in terms of speed, resolution and power. The designed 6-bit DAC operates with two supply voltages, 1 V and 3.3 V. The simulation result shows the transient analysis waveforms of current Steering DAC. The average power dissipation is 364.06 μW. The tool used for simulation is Tanner S-Edit and T-Spice. Comparisons show that using GDI logic, it consists low power as compare to the CMOS logic.</p>

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18

Huang, Qinjin, and Fengqi Yu. "A high output swing current-steering DAC using voltage controlled current source." Microelectronics Journal 68 (October 2017): 32–39. http://dx.doi.org/10.1016/j.mejo.2017.08.014.

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19

Liu, Renzhi, and Larry Pileggi. "Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC." IEEE Transactions on Circuits and Systems II: Express Briefs 62, no. 7 (July 2015): 651–55. http://dx.doi.org/10.1109/tcsii.2015.2404222.

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20

Bringas, R., F. Dy, and O. J. Gerasta. "10-bit segmented current steering DAC in 90nm CMOS technology." IOP Conference Series: Materials Science and Engineering 79 (June 10, 2015): 012005. http://dx.doi.org/10.1088/1757-899x/79/1/012005.

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21

Qiu, Dong, Sheng Fang, Ran Li, Renzhong Xie, Ting Yi, and Zhfflang Hong. "A current-steering self-calibration 14-bit 100-MSPs DAC." Journal of Semiconductors 31, no. 12 (December 2010): 125007. http://dx.doi.org/10.1088/1674-4926/31/12/125007.

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22

Panov, Georgi, Angel Popov, and Georgy Mihov. "A SAR ADC with current steering DAC and voltage input." Analog Integrated Circuits and Signal Processing 89, no. 2 (September 9, 2016): 411–15. http://dx.doi.org/10.1007/s10470-016-0856-4.

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23

Pal, Neelanjana, Prajit Nandi, Riju Biswas, and Ashvinkumar G. Katakwar. "Placement-Based Nonlinearity Reduction Technique for Differential Current-Steering DAC." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 1 (January 2016): 233–42. http://dx.doi.org/10.1109/tvlsi.2015.2399971.

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24

Bandali, Mehdi, Alireza Hassanzadeh, Masoume Ghashghaie, and Omid Hashemipour. "An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure." Journal of Circuits, Systems and Computers 28, no. 10 (September 2019): 1950172. http://dx.doi.org/10.1142/s021812661950172x.

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In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

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25

XUE, XIAOBO, XIAOLEI ZHU, QIFENG SHI, and LENIAN HE. "A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450004. http://dx.doi.org/10.1142/s0218126614500042.

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In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

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26

Bertotti, G., A. Laifi, E. Di Gioia, M. Masoumi, N. Dodel, E. F. Scarselli, and R. Thewes. "An 8 bit current steering DAC for offset compensation purposes in sensor arrays." Advances in Radio Science 10 (September 18, 2012): 201–6. http://dx.doi.org/10.5194/ars-10-201-2012.

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Abstract. An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10 μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 μW at 2.6 MHz operation frequency. Total area is 38.6 × 2933.0 μm2.

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27

Nazari, Masoud, Leila Sharifi, Meysam Akbari, and Omid Hashemipour. "Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic." Journal of Circuits, Systems and Computers 24, no. 06 (May 26, 2015): 1550086. http://dx.doi.org/10.1142/s0218126615500863.

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In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

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28

Cui, Zhi-Yuan, Hua-Lan Piao, and Nam-Soo Kim. "A 10-bit Current-steering DAC in 0.35-μm CMOS Process." Transactions on Electrical and Electronic Materials 10, no. 2 (April 25, 2009): 44–48. http://dx.doi.org/10.4313/teem.2009.10.2.044.

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29

Deveugele, J., and M. S. J. Steyaert. "A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC." IEEE Journal of Solid-State Circuits 41, no. 2 (February 2006): 320–29. http://dx.doi.org/10.1109/jssc.2005.862342.

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30

Atkin, E., and I. Sagdiev. "5 bit current steering low power DAC for threshold voltage adjustment." Journal of Physics: Conference Series 798 (January 2017): 012193. http://dx.doi.org/10.1088/1742-6596/798/1/012193.

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31

Grasso, Alfio Dario, Carmelo Alessandro Mirabella, and Salvatore Pennisi. "CMOS current-steering DAC architectures based on the triple-tail cell." International Journal of Circuit Theory and Applications 36, no. 3 (2008): 233–46. http://dx.doi.org/10.1002/cta.421.

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32

Jinshan, Yu, Fu Dongbing, Li Ruzhang, Yao Yafeng, Yan Gang, Liu Jun, Zhang Ruitao, Yu Zhou, and Li Tun. "A direct digital frequency synthesizer with high-speed current-steering DAC." Journal of Semiconductors 30, no. 10 (October 2009): 105006. http://dx.doi.org/10.1088/1674-4926/30/10/105006.

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33

Mao, Wei, Yongfu Li, Chun-Huat Heng, and Yong Lian. "High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 5 (May 2018): 995–99. http://dx.doi.org/10.1109/tvlsi.2018.2791462.

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34

Cui, Zhi‐Yuan, Joong‐Ho Choi, Yeong‐Seuk Kim, Shi‐Ho Kim, and Nam‐Soo Kim. "Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC." Microelectronics International 26, no. 3 (July 31, 2009): 35–40. http://dx.doi.org/10.1108/13565360910981544.

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35

WANG, Yuan, Wei SU, Guangliang GUO, and Xing ZHANG. "Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology." IEICE Transactions on Electronics E98.C, no. 12 (2015): 1193–95. http://dx.doi.org/10.1587/transele.e98.c.1193.

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36

Myderrizi, Indrit, and Ali Zeki. "A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC." Analog Integrated Circuits and Signal Processing 65, no. 1 (January 21, 2010): 67–75. http://dx.doi.org/10.1007/s10470-009-9448-x.

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37

Lei, Jianming, Hanshu Gui, and Beiwen Hu. "A low glitch 12-bit current-steering CMOS DAC for CNC systems." Journal of Semiconductors 34, no. 2 (February 2013): 025007. http://dx.doi.org/10.1088/1674-4926/34/2/025007.

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38

Bechthum, Elbert, Georgi Radulov, Joost Briaire, Govert Geelen, and Arthur van Roermund. "Classification for synthesis of high spectral purity current-steering mixing-DAC architectures." Analog Integrated Circuits and Signal Processing 85, no. 3 (September 23, 2015): 497–504. http://dx.doi.org/10.1007/s10470-015-0633-9.

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39

Esmaili, Arash, and Hadiseh Babazadeh. "A robust calibration method for R-2R ladder-based current-steering DAC." AEU - International Journal of Electronics and Communications 111 (November 2019): 152887. http://dx.doi.org/10.1016/j.aeue.2019.152887.

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40

Danesh, Mohammadhadi, Aishwarya Bahudhanam Venkatasubramaniyan, Gaurav Kapoor, Naveen Ramesh, Sudarsan Sadasivuni, Sanjeev Tannirkulam Chandrasekaran, and Arindam Sanyal. "Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 11 (November 2020): 2280–89. http://dx.doi.org/10.1109/tvlsi.2020.3011648.

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41

Ting, Hsin-Wen, Soon-Jyh Chang, and Su-Ling Huang. "A Design of Linearity Built-in Self-Test for Current-Steering DAC." Journal of Electronic Testing 27, no. 1 (November 4, 2010): 85–94. http://dx.doi.org/10.1007/s10836-010-5187-2.

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42

Yang, Byung-Do, and Bo-Seok Seo. "10-Bit 200-MS/s Current-Steering DAC Using Data-Dependant Current-Cell Clock-Gating." ETRI Journal 35, no. 1 (February 1, 2013): 158–61. http://dx.doi.org/10.4218/etrij.13.0212.0286.

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43

Kolm, R., and H. Zimmermann. "A 3rd-order current-mode filter in 0.12 μm CMOS." Advances in Radio Science 6 (May 26, 2008): 201–4. http://dx.doi.org/10.5194/ars-6-201-2008.

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Abstract. For software radio applications in system-on-chips, a 3rd-order current-mode Butterworth filter in 120 nm CMOS is realized. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power can be reduced by using a current-mode architecture. The cut-off frequency of this filter is switchable between 1 MHz and 4 MHz, the current consumption is 4.5 mA at VDD=1.5 V, the inband noise density is 100 pA/√Hz and it has a dynamic range up to 65 dB.

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44

Wang, Guo, Zhou, Wu, Luan, Liu, Ding, Wu, and Liu. "A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology." Electronics 8, no. 4 (April 25, 2019): 464. http://dx.doi.org/10.3390/electronics8040464.

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A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.

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45

Gulati, Neha, and Vemu Sulochana. "Design and Analysis of CMOS Thermometer Current Steering DAC to Remove Non-Linearity." International Journal of Computer Applications 118, no. 17 (May 20, 2015): 33–36. http://dx.doi.org/10.5120/20839-3570.

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46

Kim, Si-Nai, Wan Kim, Chang-Kyo Lee, and Seung-Tak Ryu. "A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure." JSTS:Journal of Semiconductor Technology and Science 12, no. 3 (September 30, 2012): 270–77. http://dx.doi.org/10.5573/jsts.2012.12.3.270.

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Li, Di, Yintang Yang, Zuochen Shi, and Yani Li. "A 2nd-order sigma-delta mismatch-shaping current-steering DAC for zigbee transmitters." Analog Integrated Circuits and Signal Processing 81, no. 1 (August 8, 2014): 145–52. http://dx.doi.org/10.1007/s10470-014-0375-0.

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Greenwald, Elliot, Christoph Maier, Qihong Wang, Robert Beaulieu, Ralph Etienne-Cummings, Gert Cauwenberghs, and Nitish Thakor. "A CMOS Current Steering Neurostimulation Array With Integrated DAC Calibration and Charge Balancing." IEEE Transactions on Biomedical Circuits and Systems 11, no. 2 (April 2017): 324–35. http://dx.doi.org/10.1109/tbcas.2016.2609854.

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Wu, Kejun, Jing Li, Xiangzhan Wang, Ning Ning, Kaikai Xu, and Qi Yu. "Switching sequence optimization for gradient errors compensation in the current-steering DAC design." Microelectronics Journal 95 (January 2020): 104662. http://dx.doi.org/10.1016/j.mejo.2019.104662.

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Da-Huei Lee, Tai-Haur Kuo, and Kow-Liang Wen. "Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method." IEEE Transactions on Circuits and Systems II: Express Briefs 56, no. 2 (February 2009): 137–41. http://dx.doi.org/10.1109/tcsii.2008.2011606.

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