Relevant bibliographies by topics / Current-Steering Digital-to-Analog Converter

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  2. Dissertations / Theses
  3. Books
  4. Book chapters
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Academic literature on the topic 'Current-Steering Digital-to-Analog Converter'

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Published: 4 June 2021
Last updated: 7 February 2022

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Journal articles on the topic "Current-Steering Digital-to-Analog Converter"

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Henriques, Bernardo G., and Jos� E. Franca. "A CMOS steering-current multiplying digital-to-analog converter." Analog Integrated Circuits and Signal Processing 8, no. 2 (September 1995): 145–55. http://dx.doi.org/10.1007/bf01239107.

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Yi, Shu-Chung. "An 8-bit current-steering digital to analog converter." AEU - International Journal of Electronics and Communications 66, no. 5 (May 2012): 433–37. http://dx.doi.org/10.1016/j.aeue.2011.10.003.

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Yi, Shu-Chung. "A 10-bit current-steering CMOS digital to analog converter." AEU - International Journal of Electronics and Communications 69, no. 1 (January 2015): 14–17. http://dx.doi.org/10.1016/j.aeue.2014.07.010.

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Akita, Ippei, Tetsuro Itakura, and Kei Shiraishi. "Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch." IEEE Transactions on Circuits and Systems II: Express Briefs 58, no. 11 (November 2011): 724–28. http://dx.doi.org/10.1109/tcsii.2011.2168013.

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Sharifi, Leila, Masoud Nazari, Meysam Akbari, and Omid Hashemipour. "An 8-Bit Unified Segmented Current-Steering Digital-to-Analog Converter." Arabian Journal for Science and Engineering 41, no. 3 (October 22, 2015): 785–96. http://dx.doi.org/10.1007/s13369-015-1908-2.

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Li, Xueqing, Hua Fan, Qi Wei, Zhen Xu, Jianan Liu, and Huazhong Yang. "A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter." Journal of Semiconductors 34, no. 8 (August 2013): 085013. http://dx.doi.org/10.1088/1674-4926/34/8/085013.

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Zheng, Dan, Wei Ni, Rui Zhang, and Yong Sheng Yin. "An Improved Data Weighted Averaging for Segmented Current-Steering DACs." Advanced Materials Research 748 (August 2013): 868–73. http://dx.doi.org/10.4028/www.scientific.net/amr.748.868.

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An improved DWA method for 14-bit 5+4+5 segmented current-steering digital-to-analog converters is proposed. Through to SFDR and dynamic performance of compromise consideration, this method uses two barrel shifters to control the starting position of the current element sequence every four clocks. Compared with the conventional DWA method, it features smaller device size and improves SFDR. And based on SIMULINK platform, through the establishment of high level of current steering D/A converter model with matching errors and output impedance. The simulation results show that SFDR is improved about 25dB.
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Nagpara, Bharat H. "A 45 nm 6 Bit Low Power Current Steering Digital to Analog Converter Using GDI Logic." TELKOMNIKA Indonesian Journal of Electrical Engineering 16, no. 1 (October 1, 2015): 46. http://dx.doi.org/10.11591/tijee.v16i1.1586.

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<p><strong><em> </em></strong>In this paper, The Design and Implementation low power Current Steering Digital to Analog Converter in 45 nm technology using GDI Logic using TANNER TOOL, V15 is presented. This architecture gives the most optimized results in terms of speed, resolution and power. The designed 6-bit DAC operates with two supply voltages, 1 V and 3.3 V. The simulation result shows the transient analysis waveforms of current Steering DAC. The average power dissipation is 364.06 μW. The tool used for simulation is Tanner S-Edit and T-Spice. Comparisons show that using GDI logic, it consists low power as compare to the CMOS logic.</p>
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Wang, Guo, Zhou, Wu, Luan, Liu, Ding, Wu, and Liu. "A 3GS/s 12-bit Current-Steering Digital-to-Analog Converter (DAC) in 55 nm CMOS Technology." Electronics 8, no. 4 (April 25, 2019): 464. http://dx.doi.org/10.3390/electronics8040464.

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A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.
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Patel, Jayeshkumar J., and Amisha P. Naik. "Design and implementation of 4 bit binary weighted current steering DAC." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 6 (December 1, 2020): 5642. http://dx.doi.org/10.11591/ijece.v10i6.pp5642-5649.

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A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.
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Dissertations / Theses on the topic "Current-Steering Digital-to-Analog Converter"

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Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
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Moody, Tyler J. "Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.

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Majid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.

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Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by

generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.

At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.

Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.

Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.

HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.

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Bittle, Charles C. "Linearity and monotonicity of a 10-bit, 125 MHz, segmented current steering digital to analog converter." Thesis, University of North Texas, 2000. https://digital.library.unt.edu/ark:/67531/metadc2541/.

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The purpose of this research is to determine the linearity and monotonicity of the THS5651IDW digital to analog converter (DAC), a prototype of the future Texas Instruments TLV5651, 10-bit, 125 MHz communication DAC. Testing was conducted at the Texas Instruments facility on Forest Lane, Dallas, Texas. Texas Instruments provided test equipment, software and laboratory space to obtain test data. Analysis of the data found the DAC to be monotonic since the magnitude of the differential nonlinearity (DNL) was less than ± 1 least significant bit (LSB) and the integral nonlinearity (INL) was less than ± 0.5 LSB. The study also showed that the DAC has primarily negative DNL although the DNL is well within the desired specification.
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Rajendran, Dinesh Babu. "Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579.

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Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.
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Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.

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A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.
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Andersson, K. Ola. "Modeling and implementation of current-steering digital-to-analog converters /." Linköping : Dept. of Electrical Enginering, Univ, 2005. http://www.ep.liu.se/diss/science_technology/09/44/index.html.

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Sadda, AlajaKumari, and Niraja Madavaneri. "A Study of Output Impedance Effects in Current-Steering Digital-to-Analog Converters." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87399.

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In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. The benefits of this architecture is that it occupies less area, consumes less power and the number of control signals required are very less. The requirements for high speed and high performance DAC are discussed in detail. The circuit is implemented in a state-of-the-art 65 nm process, with a supply voltage of 1.2 V and at a sampling speed of 2 GHz. The resolution of the DAC is 8-bits. The design of 8-bit current-steering DAC converts 8 most significant bits (MSBs) into their binary weighted equivalent, which controls 256 unit current sources. The performance of the DAC is measured using the static and dynamic  parameters. In communication applications the static performance measures such as INL and DNL are not of utmost importance. In this work, we have mainly concentrated on the dynamic performance characteristics like SNR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range). For measuring the dynamic parameters, frequency domain analysis is a better choice. Also, we have discussed how the pole-zero analysis can be used to arrive at the dynamic performance metrics of a unit element of the DAC at higher frequencies. Different methods were discussed here to show the effects of poles and zeroes on the output impedance of a unit element at higher frequencies, for example, by hand calculation, using Mathematica and by using cadence. After extensive literature studies, we have implemented a technique in cadence, to increase the output impedance at higher frequencies. This technique is called as “complimentary current solution technique”. This technique will improve the output impedance and SFDR compared to the normal unit element design. Our technique contains mostly analog building blocks, like, current mirrors, biasing scheme and switching scheme and few digital blocks like D-ff (D-flip flop). The whole system is simulated and verified in MATLAB. Dynamic performances of the DAC such as SNR and SFDR are found with the help of MATLAB.
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Balasubramanian, Sidharth. "STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.

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Warecki, Sylwester. "Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique." Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.

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Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.
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Books on the topic "Current-Steering Digital-to-Analog Converter"

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Andersson, K. Ola. Modeling and implementation of current-steering digital-to-analog converters. Linköping: Dept. of Electrical Enginering, Univ., 2005.

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Book chapters on the topic "Current-Steering Digital-to-Analog Converter"

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Mercer, Douglas A. "Current Steering Digital-to-Analog Converters." In Circuits at the Nanoscale, 187–212. CRC Press, 2018. http://dx.doi.org/10.1201/9781315218762-12.

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Mercer, Douglas. "Current Steering Digital-to-Analog Converters." In Circuits at the Nanoscale, 187–212. CRC Press, 2008. http://dx.doi.org/10.1201/9781420070637.pt3.

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Conference papers on the topic "Current-Steering Digital-to-Analog Converter"

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Dey, Aritra, and David R. Allee. "Amorphous silicon current steering digital to analog converter." In 2011 IEEE Custom Integrated Circuits Conference - CICC 2011. IEEE, 2011. http://dx.doi.org/10.1109/cicc.2011.6055407.

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Mathurkar, Piyush, and Madan Mali. "Segmented 8-bit current-steering Digital to Analog Converter." In 2015 International Conference on Pervasive Computing (ICPC). IEEE, 2015. http://dx.doi.org/10.1109/pervasive.2015.7087130.

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Lilic, Nenad, Peter Speer, and Horst Zimmermann. "A Cascaded Thermometer-Coded Current-Steering Digital-to-Analog Converter." In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018. http://dx.doi.org/10.1109/mwscas.2018.8624088.

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Huang, Qiang, and Jun Feng. "A 10-bit nanoampere level current-steering Digital to Analog Converter." In 2013 13th International Symposium on Communications and Information Technologies (ISCIT). IEEE, 2013. http://dx.doi.org/10.1109/iscit.2013.6645861.

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Naik, B. Rajendra, Rameshwar Rao, and P. Chandrasekhar. "Design of 12-bit, 1.8V current steering digital-to-analog converter." In 2008 International Conference on Electronic Design (ICED 2008). IEEE, 2008. http://dx.doi.org/10.1109/iced.2008.4786676.

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Patel, Sneha, and Usha Mehta. "A 1.8V 5-bit Segmented Current Steering Digital-to-Analog Converter." In 2021 Devices for Integrated Circuit (DevIC). IEEE, 2021. http://dx.doi.org/10.1109/devic50843.2021.9455910.

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Hirai, Manato, Hiroshi Tanimoto, Yuji Gendai, Shuhei Yamamoto, Anna Kuwana, and Haruo Kobayashi. "Nonlinearity Analysis of Resistive Ladder-Based Current-Steering Digital-to-Analog Converter." In 2020 International SoC Design Conference (ISOCC). IEEE, 2020. http://dx.doi.org/10.1109/isocc50952.2020.9332949.

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Valet, Patrick, Dario Giotta, Stefan Trampitsch, and Andrea Tonello. "Switched State-Space Model for High Speed Current-Steering Digital-to-Analog Converter." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702247.

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Chun-Chieh Chen and Nan-Ku Lu. "Nonlinearity analysis of R-2R ladder-based current-steering digital to analog converter." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571976.

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Kraus, S., I. Kallfass, R. E. Makon, J. Rosenzweig, R. Driad, M. Moyal, and D. Ritter. "High linearity 2-bit current steering InP/GaInAs DHBT digital-to-analog converter." In 2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM). IEEE, 2010. http://dx.doi.org/10.1109/iciprm.2010.5516140.

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