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Dissertations / Theses on the topic 'Current-Steering Digital-to-Analog Converter'

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Published: 4 June 2021
Last updated: 7 February 2022

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1

Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture conside
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Moody, Tyler J. "Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.

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Majid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.

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<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sourc
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4

Bittle, Charles C. "Linearity and monotonicity of a 10-bit, 125 MHz, segmented current steering digital to analog converter." Thesis, University of North Texas, 2000. https://digital.library.unt.edu/ark:/67531/metadc2541/.

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The purpose of this research is to determine the linearity and monotonicity of the THS5651IDW digital to analog converter (DAC), a prototype of the future Texas Instruments TLV5651, 10-bit, 125 MHz communication DAC. Testing was conducted at the Texas Instruments facility on Forest Lane, Dallas, Texas. Texas Instruments provided test equipment, software and laboratory space to obtain test data. Analysis of the data found the DAC to be monotonic since the magnitude of the differential nonlinearity (DNL) was less than ± 1 least significant bit (LSB) and the integral nonlinearity (INL) was less t
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Rajendran, Dinesh Babu. "Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579.

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Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) techn
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Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.

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A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400
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Andersson, K. Ola. "Modeling and implementation of current-steering digital-to-analog converters /." Linköping : Dept. of Electrical Enginering, Univ, 2005. http://www.ep.liu.se/diss/science_technology/09/44/index.html.

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8

Sadda, AlajaKumari, and Niraja Madavaneri. "A Study of Output Impedance Effects in Current-Steering Digital-to-Analog Converters." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87399.

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In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. The benefits of this architecture is that it occupies less area, consumes less power and the number of control signals required are very less. The requirements for high speed and high performance DAC are discussed in detail. The circuit is implemented in a state-of-the-art 65
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9

Balasubramanian, Sidharth. "STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.

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10

Warecki, Sylwester. "Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique." Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.

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Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The
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11

Chen, Chia-Ching, and 陳珈璟. "A 14-bit High Accuracy Current-Steering Digital-to-Analog Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/wj474e.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>104<br>A 14-bit digital-to-analog converter （DAC）is prosed and implemented in this thesis. It adopts current-steering architecture and multi-element precision matching layout for high-speed and high-accuracy applications. The proposed 14-bit high accuracy current-steering DAC utilizing segmented architecture. The eight-bit most significant bits are decoded from binary code to thermometer code by a thermometer decoder which steers the unary weighted current source array. The systematic mismatch of this current source array is canceled by highly matching layout called
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Chiou, Shiuan-Tse, and 邱宣策. "A 14-bit 300 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3azgtb.

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碩士<br>國立臺灣師範大學<br>電機工程學系<br>107<br>In the recent years, because the technology of integrated circuits develop rapidly, it improves the technique of mobility communication. Nowadays, the fourth generation of mobile communication has become popular, and mobile communication devices have become a necessity. The emergence of femtocells has increased the coverage of communication signals to maintain good transmission quality. In order to construct a femtocell base station capable of accurately transmitting packets, the design of a high resolution and high sample frequency digital-to-analog converte
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Chen, Ren-Li, and 陳仁禮. "A 10-bit 1GSample/s Current Steering Digital-to-Analog Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/31687708028135790675.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>In this thesis, a 10-bit 1-GSample/s segmented digital-to-analog converter is proposed. It is implemented in TSMC standard 0.18�慆 1P6M CMOS technology. The segmented architecture of this current steering DAC consists of 6bit MSB that is constructed by thermometer code structure and 4bit LSB that is binary weighted one. To be easier intergraded in the digital system, the power supply in the analog part is designed in1.8V. To achieve high speed, we use pipeline architecture in the thermometer decoder to alleviate their speed requirement. To improve static and
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KUO, CHIH-YAO, and 郭智堯. "A 14-bit High Accuracy Current-Steering Digital-to-Analog Converter." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/46125710852161181366.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>105<br>High accuracy data converters are always the hot spots of the application markets. However, they are really hard to design and engineers need to take a good care of the systematic and random mismatches of critical deices to achieve good enough accuracy. The random mismatch can be reduced by increasing the areas of critical devices. On the other hand, systematic mismatch can only be cancelled through circuit calibration or subtle layout patterns. For digital-to-analog converter (DAC), Q2 (Quad-Quad) Random Walk layout pattern was created in 1999 to achieve 0.3
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Chang, Jeng-Dau, and 張正道. "10-bit 350-MSample/s Current-Steering Digital-to-Analog Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/83980080754431071819.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>92<br>A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter is proposed in this thesis. Segmented current steering architecture that comprises 6MSB’s unary cells and 4LSB’s binary-weighted cells is applied in this design. Proper area of current source transistor is chosen to overcome mismatch error due to process variation. Cascoded switch structure is adopted in the current cell which improves the performance of the segmented DAC, such as INL and SNDR. In addition, a high speed and high crossing point switch driver is designed to minimize glitch error.
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Guan-YuanLi and 李冠沅. "A 10-bit 800M-Sample/s Current-Steering Digital-to-Analog Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/89046419595938106066.

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Lin, Chien-Chou, and 林建周. "A 10-bit 100M Sa/s Current-Steering Digital-to-Analog Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/21579620518337268165.

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碩士<br>樹德科技大學<br>電腦與通訊系碩士班<br>100<br>In this thesis, a 10-bit 100MSa/s current-steering digital-to-analog converter is implemented using TSMC 0.35um 2P4M mixed signal CMOS technology. The DAC adopts the segmented architecture which comprises a segment of 6-bit into 63 equally weighted current sources in the MSB and a segment of 4-bit binary-weighted current source in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture. The DAC is simulated by CIC using Analog Measurement System. The proposed DAC has the following
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18

Lin, Hsing-Hung, and 林星宏. "A 14Bit 100MS/s Current-Steering Digital to Analog Converter for HDTV." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/4ywhvz.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>104<br>In this thesis, a 14-bit 100MHz segment digital-to-analog converter is proposed. It is implemented in UMC standard 0.18μm 1P6M CMOS technology. The segmented architecture current steering DAC are divided into three parts. First part is a 6bit MSB constructed by thermometer code structure. The second part is a 4bit MID constructed by thermometer code. At the last part is a 4bit LSB binary weighted one. For easier integration in the digital system, the power supply in the analog part and digital part is applied 1.8 volts. In designing digital-to-analog converter
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19

Pan, Chun-Ming, and 潘春明. "A 10-bit 100MS/s Current-Steering Digital-to-Analog Converter for WLAN." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/82012487943461206943.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>In this thesis, a 10-bit 100M-Sample/s current steering digital-to-analog for WLAN is proposed. It is implemented in TSMC 0.35um 2P4M mixed signal CMOS technology. Segmented current steering architecture that comprises 6MSB’s thermometer code structure and 4LSB’s binary-weighted one is applied in this design. In the current cell, proper area of current source is evaluated to overcome mismatch error due to process variation. Cascoded current source and cascoded switch are adapted to improve the performance of the DAC, such as INL and SFDR. In addition, a low
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20

HouTsung-Tien and 侯宗典. "Design and Implementation of a 12-bit 100 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/37193550974193948180.

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碩士<br>崑山科技大學<br>電子工程研究所<br>94<br>In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture. The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The propo
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21

Huang, Chien-Chun, and 黃健群. "A Quadratic Error Compensation in High-Speed 8-bit Current-Steering Digital to Analog Converter." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51457244135558858347.

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碩士<br>國立臺灣大學<br>電機工程學研究所<br>97<br>This thesis proposes an 8-bit 1GHz digital-to-analog converter with a segmented current steering architecture that consists of two parts, the upper 5-bit thermometer code and the lower 3-bit binary-weighted code. The design not only keeps the advantages of current steering architecture, but also consumes lower power. The DAC architecture is implemented by the proposed switching sequence. The new switching sequence divides the upper 5-bit current source into eight unary current source to compensate quadratic error and also uses integral non-linear (INL) bounded
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22

Hsu, Chien Tsung, and 許健宗. "Design of A 10-bit Current Steering Digital-to-Analog Converter for Stimulators in Visual Aids." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/37217619653834428020.

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碩士<br>中華科技大學<br>電子工程研究所碩士班<br>100<br>This thesis realizes a 10-bit current steering digital to analog converter applied in the stimulators of visual aids. This converter, using two-segment architecture, separates input signals into the six most significant bits and the four least significant bits. The six-bit segment is decoded by thermometer code and the four-bit segment is decoded binary weights to get better differential nonlinearity error (DNL) and to ensure the monotonic. In the design of the current sources in the converter, we use cascode architecture to enhance its performance, such as
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23

Chu, Shi-Xuan, and 儲世軒. "A 10-bit 800M-Sample/s Current-Steering Digital-to-Analog Converter and Foreground Calibration Techniques." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/25731764370406717248.

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碩士<br>國立中正大學<br>電機工程所<br>96<br>A 10-bit 800M-Sample/s current-steering digital-to-analog converter(DAC) is designed in this thesis. Considering both circuit linearity and chip area, binary-weighted code and thermometer codes are used in encoding. Area analysis is used to overcome process variations for current source transistors. In order to reduce glitch and enhance dynamical performance of the DAC, filp-flops are utilized in signal synchronization. The chip is implemented in TSMC 0.18μm 1P6M CMOS technology. Simulation results show that the SFDR of the current-steering DAC with an input freq
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Chung, Cheng-Feng, and 鍾政峰. "A new switching scheme for parabolic error compensation in 10 bit CMOS current steering digital to analog converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/21328668856152205743.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>94<br>This thesis proposes a 10 bit 250MHz current steering DAC with a doubly segmented current steering architecture that consists of two parts: upper 5 bit MSBs and intermediate 2 bit MSBs. The other 3 bit LSBs are binary weighted current source. This design not only keeps the advantages of current steering architecture, but also consumes lower power. Two types of DACs are implemented. One is implemented by a two-dimension switching scheme, another one is implemented by the proposed switching scheme. The new switching scheme divides the MSB current source into eig
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Li, Chin, and 李秦. "A 6-bit folded R-2R ladder-based current-steering Digital to Analog Converter Design and Characteristic Analysis." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/5t8au9.

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碩士<br>中原大學<br>電子工程研究所<br>105<br>The purpose of this paper is to improve the power consumption and design area of traditional 6-bit R-2R ladder-based current-steering Digital to Analog Converter. Use folding technology to reduce almost half of the R-2R resistors, and the same unit resistance value’s area also reduce to achieve the purpose of reducing the area. Because of using folding technology, the number of current control switches is also reduced from 48 unit current to 28 unit current; it almost reduces nearly 60%, and achieves the purpose of reducing the power consumption. This paper des
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Yang, Hao-Hsiang, and 楊皓翔. "A 6-bit 2 GS/s Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/27q9b9.

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碩士<br>中原大學<br>電子工程研究所<br>102<br>In this paper, a 6-bit 2 GS/s Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter is designed. Design platform is TSMC 0.18 μm 1P6M CMOS process. The power consumption simulation results is 7.25 mW, include output buffer circuit is 19.8mW, at 1.8V power supply. The ENOB of 5.65 bits, the DNL is 0.005LSB, the INL is 0.024LSB, when the input frequency of 180 MHz, SFDR of 43.44 dB。
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Liu, Yuchang, та 劉昱昌. "Design and Implementation of a 10-bit 250-MS/s Current Steering Digital-to-Analog Converter in 0.18μm CMOS Process". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/43087827800354057702.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>100<br>The simulation and layout of the thesis is to achieve a 250MHz 10bits current steering DAC, and is expected to complete tape out by 0.18um 1p6m process provided by Taiwan Semiconductor Manufacturing Company provided . The circuit layout design has two parts - digital and analog. To reduce the glitch and differential nonlinearity (DNL), integral nonlinearity (INL) and to maintain the transfer curve monotonic the circuit is designed to be segmented structure, in which the highest 6bits MSB is the thermometer decoder and the lowest 4bits LSB is weighted binary c
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Chan, Chun-Yu, and 詹竣宇. "A 6-bit Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter design and characteristics Analysis." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/j48482.

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碩士<br>中原大學<br>電子工程研究所<br>105<br>This paper aims to design a 6-bit Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter. The design platform uses TSMC 0.18-μm 1P6M CMOS. The simulation results show that the power consumption is 1.9913mW when the power supply is 1.8V. In addition, when the input frequency is set to 179.6875MHz, the ENOB is 5.79 bits, the DNL is ±0.011LSB, the INL is ±0.012LSB and the SFDR is 48.80dB, respectively. A further analysis to the designed circuit was presented by investigating the MOS device size of differential pair and current-sourse fo
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Lin, Yuming, and 林育民. "Study of Charge Pump Circuits for UHF RFID Tag and 10 bits 250MS/s Current-Steering Digital-to-Analog Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/94670037659013069801.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>99<br>In this thesis achieve circuit is applied to UHF 915MHz RFID Tags , transfering small radio waves into stable DC voltage for the use of next stage circuit. Because RF signal losses quickly in air, much smaller than -15dBm, the issue of using a charge pump to supply sufficient and stable DC voltage is important. And this technology can be further applied in wireless charging technology, not only in wireless sensor system but also in various technology products such as mobile phones, MP3, wireless communications, and camera…In this thesis, I implement the charge
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Tseng, Wei-Hsin, and 曾偉信. "High-Speed Current-Steering Digital-to-Analog Converters." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/49493691388146598208.

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博士<br>國立交通大學<br>電子研究所<br>99<br>In communication systems, most of the information processing is performed in the digital domain, but the signal carrying the information must be transmitted using analog signals. Therefore, the use of digital-to-analog(DA) and analog-to-digital(AD) converters are unavoidable. Data converters are critical for connecting signals to the real world, often limiting the accuracy and speed of the overall system. As a result, wide-band high-dynamic-range converters are in high demand. This thesis focuses on the Digital-to-Analog Converters (DACs). The current-steering
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tien, Kung yuan, and 孔元田. "Current steering Digital to Analog Converters for ultrasonic breath monitoring system." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/3674q8.

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碩士<br>南臺科技大學<br>電子工程系<br>106<br>This thesis, expounds a respiration monitoring device, which is designed for the use in long-term care and can reduce workloads for caregivers and psychological stress for patients. In addition to its application in long-term care, the device can also be used at places like hospitals and homes with infants. In this thesis, the 0.18-um 1P6M process from Taiwan Semiconductor Manufacturing Company (TSMC) was leveraged to realize a 14-bit 100MHz high-speed current-steering digital-to-analog converter (DAC). The DAC was realized based on a segmented hybrid current mo
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Ren-LiChen and 陳仁禮. "Design of Low-Power Current-Steering Digital-to-Analog Converters for Wireless Communication Applications." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/94146635807191250180.

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博士<br>國立成功大學<br>電機工程學系碩博士班<br>101<br>This dissertation proposes several circuit design techniques for current-steering digital-to-analog converters (DACs) on wireless communication applications to lower the power consumption. Moreover, a compound current cell is also proposed to make current-steering DACs in a system-on-a-chip (SoC) have more functionality for reducing the integration challenges and cost. Hence, three proof-of-concept prototypes are presented to demonstrate these techniques. According to the measurement results of the prototypes, the proposed techniques have good power efficie
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Huang, Su-Ling, and 黃素鈴. "The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/76371604221474286432.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>97<br>This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-�慆 1P6M CMOS process. The measured results show that the differential nonlinearity (DNL) is less than 0.35 LSB (Least Significant Bit), and the integral nonlinearity (INL) is less than 0.6 LSB. The spurious free dynamic range (SFDR) is 60.63 dB with a 25-MHz input signal at a 500-MS/s sampling rate. The power consumption is 28 mW, and the core
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