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1
Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.
Full textAbstract:
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.
2
Moody, Tyler J. "Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.
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Majid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.
Full textAbstract:
Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform by
generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.
At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.
Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.
Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.
HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.
4
Bittle, Charles C. "Linearity and monotonicity of a 10-bit, 125 MHz, segmented current steering digital to analog converter." Thesis, University of North Texas, 2000. https://digital.library.unt.edu/ark:/67531/metadc2541/.
Full textAbstract:
The purpose of this research is to determine the linearity and monotonicity of the THS5651IDW digital to analog converter (DAC), a prototype of the future Texas Instruments TLV5651, 10-bit, 125 MHz communication DAC. Testing was conducted at the Texas Instruments facility on Forest Lane, Dallas, Texas. Texas Instruments provided test equipment, software and laboratory space to obtain test data. Analysis of the data found the DAC to be monotonic since the magnitude of the differential nonlinearity (DNL) was less than ± 1 least significant bit (LSB) and the integral nonlinearity (INL) was less than ± 0.5 LSB. The study also showed that the DAC has primarily negative DNL although the DNL is well within the desired specification.
5
Rajendran, Dinesh Babu. "Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579.
Full textAbstract:
Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.
6
Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.
Full textAbstract:
A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.
7
Andersson, K. Ola. "Modeling and implementation of current-steering digital-to-analog converters /." Linköping : Dept. of Electrical Enginering, Univ, 2005. http://www.ep.liu.se/diss/science_technology/09/44/index.html.
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Sadda, AlajaKumari, and Niraja Madavaneri. "A Study of Output Impedance Effects in Current-Steering Digital-to-Analog Converters." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-87399.
Full textAbstract:
In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and their advantages and disadvantages. We have mainly focused on current-steering digital-to-analog design for achieving high speed and high performance. The current-steering DAC is designed using binary weighted architecture. The benefits of this architecture is that it occupies less area, consumes less power and the number of control signals required are very less. The requirements for high speed and high performance DAC are discussed in detail. The circuit is implemented in a state-of-the-art 65 nm process, with a supply voltage of 1.2 V and at a sampling speed of 2 GHz. The resolution of the DAC is 8-bits. The design of 8-bit current-steering DAC converts 8 most significant bits (MSBs) into their binary weighted equivalent, which controls 256 unit current sources. The performance of the DAC is measured using the static and dynamic parameters. In communication applications the static performance measures such as INL and DNL are not of utmost importance. In this work, we have mainly concentrated on the dynamic performance characteristics like SNR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range). For measuring the dynamic parameters, frequency domain analysis is a better choice. Also, we have discussed how the pole-zero analysis can be used to arrive at the dynamic performance metrics of a unit element of the DAC at higher frequencies. Different methods were discussed here to show the effects of poles and zeroes on the output impedance of a unit element at higher frequencies, for example, by hand calculation, using Mathematica and by using cadence. After extensive literature studies, we have implemented a technique in cadence, to increase the output impedance at higher frequencies. This technique is called as “complimentary current solution technique”. This technique will improve the output impedance and SFDR compared to the normal unit element design. Our technique contains mostly analog building blocks, like, current mirrors, biasing scheme and switching scheme and few digital blocks like D-ff (D-flip flop). The whole system is simulated and verified in MATLAB. Dynamic performances of the DAC such as SNR and SFDR are found with the help of MATLAB.
9
Balasubramanian, Sidharth. "STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.
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Warecki, Sylwester. "Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique." Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.
Full textAbstract:
Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The design of Digital-to-Analog Converters (DAC) providing high-speed and high-resolution is extremely difficult. To overcome problems caused by manufacturing process variation numerous techniques such as thermometer coding or calibration are utilized in DAC design. However, in many cases implementation of these techniques becomes a source of new problems such as clock jitter or glitch. To solve them simulation of DAC, depicting numerous effects of physical phenomena, is an absolute necessity. Unfortunately such simulation with utilization of off-the-shelf mixed signal simulators is very demanding. Therefore simulation of all DAC circuit becomes impractical due to long simulation time or lack of good models of still studied phenomena such as glitch. A novel method allowing for simultaneous and accurate representation of numerous phenomena and significantly increasing simulation speed is proposed. The method is called a Perfect Sampling Technique (PST) and it allows for precise calculation of most important in telecommunication dynamic DAC performance metric---the Spurious Free Dynamic Range (SFDR). The technique was primarily built to overcome the deficiencies of popular Discrete Fourier Transform (DFT). This novel approach allows for concurrent simulation of the following phenomena: deterministic and random clock jitter, random and graded current source mismatch, and the glitch and output finite impedance. The implemented in Visual C++ simulator provides means of representation of various DAC structures: segmentation (thermometer and binary coding), 2D layout of current source matrix and analog switch dynamic characteristics. It utilizes behavioral models of DAC building blocks (analog switches) in custom-built extremely fast event driven simulation framework. It also provides means for parametric, statistical, transient and spectral analysis of DAC.
11
Chen, Chia-Ching, and 陳珈璟. "A 14-bit High Accuracy Current-Steering Digital-to-Analog Converter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/wj474e.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
104
A 14-bit digital-to-analog converter （DAC）is prosed and implemented in this thesis. It adopts current-steering architecture and multi-element precision matching layout for high-speed and high-accuracy applications. The proposed 14-bit high accuracy current-steering DAC utilizing segmented architecture. The eight-bit most significant bits are decoded from binary code to thermometer code by a thermometer decoder which steers the unary weighted current source array. The systematic mismatch of this current source array is canceled by highly matching layout called Modified Q2 Random Pattern created by our research team. The six-bit least significant bits are constructed as a binary weighted current source array implemented by current splitters also proposed by our team to enhance its accuracy. The DAC is implemented in a UMC 0.18um Mixed-Signal 1P6M process powered with 1.8V/3.3V dual supplies. The integral nonlinearity and sampling frequency of the post-simulation are and 100 MHz respectively. The chip core area is merely 1.153mm2. Keyword: Current-steering digital-to-analog converter，Systematic mismatch，Modified Q2 Random Pattern，Layout automation.
12
Chiou, Shiuan-Tse, and 邱宣策. "A 14-bit 300 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3azgtb.
Full textAbstract:
碩士國立臺灣師範大學
電機工程學系
107
In the recent years, because the technology of integrated circuits develop rapidly, it improves the technique of mobility communication. Nowadays, the fourth generation of mobile communication has become popular, and mobile communication devices have become a necessity. The emergence of femtocells has increased the coverage of communication signals to maintain good transmission quality. In order to construct a femtocell base station capable of accurately transmitting packets, the design of a high resolution and high sample frequency digital-to-analog converter is very important. In this paper, a 14-bit 300MHz digital-to-analog converter is achieved by current-steering architecture, and this 14-bit circuit consists of three segments. Two of it is a 6-bit thermometer-based converter, and the other is a 2-bit binary-weighted converter. The supply voltage in analog and digital is applied in 1.8 V and 1 V, respectively. From the measurement results, a peak SFDR of 44.72 dB is achieved in TSMC 0.18μm 1P6M mixed-signal CMOS, and the power consumption is 23.52 mW.
13
Chen, Ren-Li, and 陳仁禮. "A 10-bit 1GSample/s Current Steering Digital-to-Analog Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/31687708028135790675.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
93
In this thesis, a 10-bit 1-GSample/s segmented digital-to-analog converter is proposed. It is implemented in TSMC standard 0.18�慆 1P6M CMOS technology. The segmented architecture of this current steering DAC consists of 6bit MSB that is constructed by thermometer code structure and 4bit LSB that is binary weighted one. To be easier intergraded in the digital system, the power supply in the analog part is designed in1.8V. To achieve high speed, we use pipeline architecture in the thermometer decoder to alleviate their speed requirement. To improve static and dynamic specifications, many issues, such as INL yield requirement, switching scheme, layout optimization and power lines decoupling, in designing this DAC are taken care of. For a 500MHz update rate, the SFDR is 62dB at 200MHz signal frequency. When the update rate reaches to 1GHz, the SFDR is 55dB at 100 MHz signal frequency. The DNL is less than 0.1 LSB, and the INL is less than 0.15 LSB. The power consumption is 35mw at a 100MHz input signal with 1GHz update rate. The active area is 0.5mm2 and the total area is 1.21mm2.
14
KUO, CHIH-YAO, and 郭智堯. "A 14-bit High Accuracy Current-Steering Digital-to-Analog Converter." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/46125710852161181366.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
105
High accuracy data converters are always the hot spots of the application markets. However, they are really hard to design and engineers need to take a good care of the systematic and random mismatches of critical deices to achieve good enough accuracy. The random mismatch can be reduced by increasing the areas of critical devices. On the other hand, systematic mismatch can only be cancelled through circuit calibration or subtle layout patterns. For digital-to-analog converter (DAC), Q2 (Quad-Quad) Random Walk layout pattern was created in 1999 to achieve 0.3 LSB integral nonlinearity (INL) with 14-bit resolution. For more than 20 years till now, no designer on earth is capable of breaking this historical record in DAC accuracy. A segmented matrix style current-steering DAC is proposed in this thesis. To enhance the linearity of Random Walk, Random Pattern is created to further randomize the positions among sequential current sources and thus minimize the correlations among their DNLs to prevent INL error accumulation. The mirroring and rotation of Quad-Quad are also modified to distribute the 16 sub-cells of each unary current sources into 8 x coordinates and 8 y coordinates instead of only 4 x coordinates and 8 y coordinates to get better uniformity. Through MATLAB behavior simulations, the INL is reduced by replacing either Q2 with Enhanced Q2 or Random Walk with Random Pattern. On average, the INL of Enhanced Q2 Random Pattern is reduced from Q2 Random Walk by 6.07 times to increase almost 2.5 bits in the effective number of bits (ENOB). It thus proves the effectiveness and excellence of the proposed layout pattern. For implementation, some script and constraints are composed by Prof. Shao-Yun Fang and her Ph.D. student to guide the EDA tool for Automatic Placement and Routing (APR) according to the new matrix style layout pattern. The post simulations show that the proposed Enhanced Q2 Random Pattern is much better than the traditional Q2 Random Walk in accuracy. The idea was submitted to the top CAD journal, IEEE Transactions on Computer-Aided Design, and the paper was accepted already for future publication.
15
Chang, Jeng-Dau, and 張正道. "10-bit 350-MSample/s Current-Steering Digital-to-Analog Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/83980080754431071819.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
92
A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter is proposed in this thesis. Segmented current steering architecture that comprises 6MSB’s unary cells and 4LSB’s binary-weighted cells is applied in this design. Proper area of current source transistor is chosen to overcome mismatch error due to process variation. Cascoded switch structure is adopted in the current cell which improves the performance of the segmented DAC, such as INL and SNDR. In addition, a high speed and high crossing point switch driver is designed to minimize glitch error. The simulation results show that INL is better than ±0.2 LSB and DNL is between ±0.1 LSB. SNDR better than 60 dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5 V supply is 36 mW for a near-Nyquist fundamental signal at a 350 MHz update rate. The SNDR of post-simulation for a 170 MHz signal at a 350 MHz update rate is 55.96 dB and the power of the post-simulation is 43.8 mW. The DAC is fabricated using TSMC standard 0.25μm 1P5M CMOS process. The chip has small active area of 0.09 mm2.
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Guan-YuanLi and 李冠沅. "A 10-bit 800M-Sample/s Current-Steering Digital-to-Analog Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/89046419595938106066.
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Lin, Chien-Chou, and 林建周. "A 10-bit 100M Sa/s Current-Steering Digital-to-Analog Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/21579620518337268165.
Full textAbstract:
碩士樹德科技大學
電腦與通訊系碩士班
100
In this thesis, a 10-bit 100MSa/s current-steering digital-to-analog converter is implemented using TSMC 0.35um 2P4M mixed signal CMOS technology. The DAC adopts the segmented architecture which comprises a segment of 6-bit into 63 equally weighted current sources in the MSB and a segment of 4-bit binary-weighted current source in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture. The DAC is simulated by CIC using Analog Measurement System. The proposed DAC has the following performances: The sampling rate of DAC is 100M S/a, INL is less then 0.3LSB, DNL is less than ±0.5LSB, setting time is 6nS, for 20MSa/s sine wave input the SFDR is 34dB. The power consumption is 99.33mW at the maximum conversion rate and total area is 1.1 mm2.
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Lin, Hsing-Hung, and 林星宏. "A 14Bit 100MS/s Current-Steering Digital to Analog Converter for HDTV." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/4ywhvz.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
104
In this thesis, a 14-bit 100MHz segment digital-to-analog converter is proposed. It is implemented in UMC standard 0.18μm 1P6M CMOS technology. The segmented architecture current steering DAC are divided into three parts. First part is a 6bit MSB constructed by thermometer code structure. The second part is a 4bit MID constructed by thermometer code. At the last part is a 4bit LSB binary weighted one. For easier integration in the digital system, the power supply in the analog part and digital part is applied 1.8 volts. In designing digital-to-analog converter technical skills such as transistor switching timing scheme, layout optimization and power line decoupling are applied to achieve high performance of static and dynamic specifications.
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Pan, Chun-Ming, and 潘春明. "A 10-bit 100MS/s Current-Steering Digital-to-Analog Converter for WLAN." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/82012487943461206943.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
In this thesis, a 10-bit 100M-Sample/s current steering digital-to-analog for WLAN is proposed. It is implemented in TSMC 0.35um 2P4M mixed signal CMOS technology. Segmented current steering architecture that comprises 6MSB’s thermometer code structure and 4LSB’s binary-weighted one is applied in this design. In the current cell, proper area of current source is evaluated to overcome mismatch error due to process variation. Cascoded current source and cascoded switch are adapted to improve the performance of the DAC, such as INL and SFDR. In addition, a low cross point driver which avoids the switches to cut off at the same time is designed to reduce glitch error. Special layout techniques are used to minimize systematic error in current source array. The simulation results show that DNL is less than ±0.2 LSB and INL is less than ±0.25 LSB. For a 100MHz update, the SFDR is 68.2dB at 2MHz signal frequency and the SFDR is 58.3dB at 30MHz signal frequency. The power consumption is 78.4mW at a 30MHz input signal with 100MHz update rate. The total area is 2.1mm2.
20
HouTsung-Tien and 侯宗典. "Design and Implementation of a 12-bit 100 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/37193550974193948180.
Full textAbstract:
碩士崑山科技大學
電子工程研究所
94
In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture. The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.3 LSB, DNL is less than 0.25 LSB, settling time is 9 ns, and glitch is 5.8 pV-s. For 1MHz sine wave input and 100 MHz sampling rate, the SFDR is 80 dB, and for 49MHz sine wave input and 100 MHz sampling rate, the SFDR is 67 dB. The power consumption is 127 mW at the maximum conversion rate. The real world measurement results show that the proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.6 LSB, DNL is less than 0.4 LSB, settling time is 10 ns, and glitch energy is 25 pV-s. For 200 kHz sine wave input and 100 MHz sampling rate, the measured SFDR is 70.3 dB, and for 5 MHz sine wave input and 100 MHz sampling rate, the measured SFDR is 63.51 dB. The measured power consumption is 142 mW at the maximum conversion rate.
21
Huang, Chien-Chun, and 黃健群. "A Quadratic Error Compensation in High-Speed 8-bit Current-Steering Digital to Analog Converter." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51457244135558858347.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
97
This thesis proposes an 8-bit 1GHz digital-to-analog converter with a segmented current steering architecture that consists of two parts, the upper 5-bit thermometer code and the lower 3-bit binary-weighted code. The design not only keeps the advantages of current steering architecture, but also consumes lower power. The DAC architecture is implemented by the proposed switching sequence. The new switching sequence divides the upper 5-bit current source into eight unary current source to compensate quadratic error and also uses integral non-linear (INL) bounded algorithm to optimize the INL characteristic. This DAC has been implemented in a 90nm 1P9M mixed-signal CMOS process provided by UMC, with active area of 0.013mm2 and total area including PADs is 0.415mm2.The INL and differential non-linear (DNL) are 0.19 and 0.26 LSB, respectively. The spurious-free dynamic range (SFDR) is 49.2dB when the update rate is 1GHz and the input frequency is 9.25MHz. The power consumption is 8.2mW with a supply voltage of 1V.
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Hsu, Chien Tsung, and 許健宗. "Design of A 10-bit Current Steering Digital-to-Analog Converter for Stimulators in Visual Aids." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/37217619653834428020.
Full textAbstract:
碩士中華科技大學
電子工程研究所碩士班
100
This thesis realizes a 10-bit current steering digital to analog converter applied in the stimulators of visual aids. This converter, using two-segment architecture, separates input signals into the six most significant bits and the four least significant bits. The six-bit segment is decoded by thermometer code and the four-bit segment is decoded binary weights to get better differential nonlinearity error (DNL) and to ensure the monotonic. In the design of the current sources in the converter, we use cascode architecture to enhance its performance, such as integral nonlinearity error (INL) and spurious-free dynamic range (SFDR). In addition, a high speed, high switching point switch is designed to reduce the error generated by the instantaneous pulse signal when the signal is switching. This converter circuit is realized by TSMC 0.18-micron, 1Poly/6Metal, mixed-signal / RF, 1.8V/3.3V process. Post-layout simulation results show that the DNL is less than 0.05 LSB, the INL is less than 0.05 LSB, and the spurious-free dynamic range of 79.7027 dB, with the sampling frequency of 2MHz, the input signal of 46.875 kHz. The power consumption of 7.6 mW and the entire layout area is 0.357 mm2. This converter circuit can provide a stable current for in the stimulators of visual aids.
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Chu, Shi-Xuan, and 儲世軒. "A 10-bit 800M-Sample/s Current-Steering Digital-to-Analog Converter and Foreground Calibration Techniques." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/25731764370406717248.
Full textAbstract:
碩士國立中正大學
電機工程所
96
A 10-bit 800M-Sample/s current-steering digital-to-analog converter(DAC) is designed in this thesis. Considering both circuit linearity and chip area, binary-weighted code and thermometer codes are used in encoding. Area analysis is used to overcome process variations for current source transistors. In order to reduce glitch and enhance dynamical performance of the DAC, filp-flops are utilized in signal synchronization. The chip is implemented in TSMC 0.18μm 1P6M CMOS technology. Simulation results show that the SFDR of the current-steering DAC with an input frequency of 102MHz under sampling frequency of 800MHz is 61.9dB. The DNL is about +0.454/-0.258LSB and INL is about +0.310/-0.206LSB. The total area is 1.458 x 1.248 mm2. The total power consumption is 20.98mW. With the experience of the area analysis to overcome process variations, then a new foreground calibration technique is proposed. Only 6 bits are for required analyzing current source transistors area and overall 12-bit linearity could be reached after calibration. The key concept of the calibration scheme is to control the body voltages of the current source transistors. The actual threshold voltage varied accordingly and hence the drain current Id is calibrated. The DAC operates with supply voltage of 1.8V, and can achieve 12-bit resolution at sampling frequency of 250MHz. Furthermore, this DAC demonstrates small-area characteristic.
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Chung, Cheng-Feng, and 鍾政峰. "A new switching scheme for parabolic error compensation in 10 bit CMOS current steering digital to analog converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/21328668856152205743.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
This thesis proposes a 10 bit 250MHz current steering DAC with a doubly segmented current steering architecture that consists of two parts: upper 5 bit MSBs and intermediate 2 bit MSBs. The other 3 bit LSBs are binary weighted current source. This design not only keeps the advantages of current steering architecture, but also consumes lower power. Two types of DACs are implemented. One is implemented by a two-dimension switching scheme, another one is implemented by the proposed switching scheme. The new switching scheme divides the MSB current source into eight parts to compensate parabolic error and also use tree structure to optimize. This DAC is to be implemented with a UMC 0.18 µm 1P6M mixed signal CMOS process. The DNL and INL are 0.2 and 0.7 LSB, respectively. The SFDR is 64dB when the update rate is 200MHz and the input frequency is 1MHz. The power consumption is 20 mW, and it operates from 1.8V. The active area is 0.72x0.68mm2.
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Li, Chin, and 李秦. "A 6-bit folded R-2R ladder-based current-steering Digital to Analog Converter Design and Characteristic Analysis." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/5t8au9.
Full textAbstract:
碩士中原大學
電子工程研究所
105
The purpose of this paper is to improve the power consumption and design area of traditional 6-bit R-2R ladder-based current-steering Digital to Analog Converter. Use folding technology to reduce almost half of the R-2R resistors, and the same unit resistance value’s area also reduce to achieve the purpose of reducing the area. Because of using folding technology, the number of current control switches is also reduced from 48 unit current to 28 unit current; it almost reduces nearly 60%, and achieves the purpose of reducing the power consumption. This paper designs DAC specifications by using rigorous formulas, and explores its static and dynamic characteristics. The power consumption simulation results is 7.25 mW(no Buffer). The ENOB of 5.79 bits, when the input frequency of 50MHz, SFDR of48.46dB. Design platform is TSMC 0.18 μm 1P6M CMOS process.
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Yang, Hao-Hsiang, and 楊皓翔. "A 6-bit 2 GS/s Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/27q9b9.
Full textAbstract:
碩士中原大學
電子工程研究所
102
In this paper, a 6-bit 2 GS/s Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter is designed. Design platform is TSMC 0.18 μm 1P6M CMOS process. The power consumption simulation results is 7.25 mW, include output buffer circuit is 19.8mW, at 1.8V power supply. The ENOB of 5.65 bits, the DNL is 0.005LSB, the INL is 0.024LSB, when the input frequency of 180 MHz, SFDR of 43.44 dB。
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Liu, Yuchang, and 劉昱昌. "Design and Implementation of a 10-bit 250-MS/s Current Steering Digital-to-Analog Converter in 0.18μm CMOS Process." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/43087827800354057702.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
100
The simulation and layout of the thesis is to achieve a 250MHz 10bits current steering DAC, and is expected to complete tape out by 0.18um 1p6m process provided by Taiwan Semiconductor Manufacturing Company provided . The circuit layout design has two parts - digital and analog. To reduce the glitch and differential nonlinearity (DNL), integral nonlinearity (INL) and to maintain the transfer curve monotonic the circuit is designed to be segmented structure, in which the highest 6bits MSB is the thermometer decoder and the lowest 4bits LSB is weighted binary code. The circuit is composed of 4 main parts: (1) digital circuit (2) clock drive, buffer (3) Deglitch Latch (4) current units. And current steering DAC output current do not need to output buffer can Directly drive the load resistance, so better than other architecture has speed advantages. Finally, first measurements to similar measurements of this structure TSMC 0.35μm the DAC chip for its measurement method and its results as a measurement of the paper as a reference.
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Chan, Chun-Yu, and 詹竣宇. "A 6-bit Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter design and characteristics Analysis." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/j48482.
Full textAbstract:
碩士中原大學
電子工程研究所
105
This paper aims to design a 6-bit Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter. The design platform uses TSMC 0.18-μm 1P6M CMOS. The simulation results show that the power consumption is 1.9913mW when the power supply is 1.8V. In addition, when the input frequency is set to 179.6875MHz, the ENOB is 5.79 bits, the DNL is ±0.011LSB, the INL is ±0.012LSB and the SFDR is 48.80dB, respectively. A further analysis to the designed circuit was presented by investigating the MOS device size of differential pair and current-sourse for the overall circuit impact.
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Lin, Yuming, and 林育民. "Study of Charge Pump Circuits for UHF RFID Tag and 10 bits 250MS/s Current-Steering Digital-to-Analog Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/94670037659013069801.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
99
In this thesis achieve circuit is applied to UHF 915MHz RFID Tags , transfering small radio waves into stable DC voltage for the use of next stage circuit. Because RF signal losses quickly in air, much smaller than -15dBm, the issue of using a charge pump to supply sufficient and stable DC voltage is important. And this technology can be further applied in wireless charging technology, not only in wireless sensor system but also in various technology products such as mobile phones, MP3, wireless communications, and camera…In this thesis, I implement the charge pump circuits by TSMC 18µm 1P6M process. In order to achieve a stable supply meet the specifications of the DC voltage, the circuit layout includes a matching network, voltage multiplier, voltage limiting circuit, reference voltage circuit, and Regulator. The simulation and layout of the thesis is to achieve a 250MHz 10bits current steering DAC, and is expected to complete tape out by 35um 2p4m process provided by Taiwan Semiconductor Manufacturing Company provided . The circuit layout design has two parts - digital and analog. To reduce the glitch and differential nonlinearity (DNL), integral nonlinearity (INL) and to maintain the transfer curve monotonic the circuit is designed to be segmented structure, in which the highest 6bits MSB is the thermometer decoder and the lowest 4bits LSB is weighted binary code. The circuit is composed of 4 main parts: (1) digital circuit (2) clock drive, buffer (3) Deglitch Latch (4) current units. And current steering DAC output current do not need to output buffer can Directly drive the load resistance, so better than other architecture has speed advantages.
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Tseng, Wei-Hsin, and 曾偉信. "High-Speed Current-Steering Digital-to-Analog Converters." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/49493691388146598208.
Full textAbstract:
博士國立交通大學
電子研究所
99
In communication systems, most of the information processing is performed in the digital domain, but the signal carrying the information must be transmitted using analog signals. Therefore, the use of digital-to-analog(DA) and analog-to-digital(AD) converters are unavoidable. Data converters are critical for connecting signals to the real world, often limiting the accuracy and speed of the overall system. As a result, wide-band high-dynamic-range converters are in high demand. This thesis focuses on the Digital-to-Analog Converters (DACs). The current-steering structure has been widely used in high-speed DACs, since in this structure the main speed limitation comes from the output node, and high sampling speed is thus easily achieved. However, the non-ideal switching limits the bandwidth of spurious-free dynamic range(SFDR). The SFDR decreases rapidly with increasing input frequency. Therefore, Digital Random Return-to-Zero(DRRZ) is proposed for the high sampling rate current-steering DAC to maintain high SFDR at high frequency. To demonstrate the proposed Digital Random Return-to-Zero technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90 nm CMOS technology. The DAC achieves a SFDR better than 60 dB for a sinewave input up to 460 MHz, and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power. In the design of high-accuracy current-steering DACs, current sources with high matching property are required and the penalty is large area. Intrinsic and parasitic capacitor loading also degrade the signal bandwidth. The way to reduce loading is using compact current cells. In this thesis, background calibration is proposed to correct the mismatch current caused by small dimension. To verify the proposed background calibration algorithm, a 12-bit DAC was fabricated in 90nm CMOS technology and using compact current cells. The area of current sources are 1/400 of the required area which is designed for 12-bit resolution. The chip consumes 128mW. Active area is 1100x750um2. At 1.25GS/s sampling rate, the DAC achieves better SFDR than 70dB up to 500MHz input frequency.
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tien, Kung yuan, and 孔元田. "Current steering Digital to Analog Converters for ultrasonic breath monitoring system." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/3674q8.
Full textAbstract:
碩士南臺科技大學
電子工程系
106
This thesis, expounds a respiration monitoring device, which is designed for the use in long-term care and can reduce workloads for caregivers and psychological stress for patients. In addition to its application in long-term care, the device can also be used at places like hospitals and homes with infants. In this thesis, the 0.18-um 1P6M process from Taiwan Semiconductor Manufacturing Company (TSMC) was leveraged to realize a 14-bit 100MHz high-speed current-steering digital-to-analog converter (DAC). The DAC was realized based on a segmented hybrid current mode architecture, which divided the 14 bits into 4 most significant bits (MSBs), 4 upper least significant bits (ULSBs) and 6 least significant bits (LSBs). The MSBs and ULSBs, once converted into the thermometer encoding structure, controlled 15 current sources, respectively. The LSBs used the binary weighted structure for the control over 6 current sources. This architecture was able to improve differential nonlinearity (DNL), glitch and monotonicity. In addition, the problem of parasitic capacitance discharging was solved simply by adding another transistor between the switches of the current sources and stacked transistors.
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Ren-LiChen and 陳仁禮. "Design of Low-Power Current-Steering Digital-to-Analog Converters for Wireless Communication Applications." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/94146635807191250180.
Full textAbstract:
博士國立成功大學
電機工程學系碩博士班
101
This dissertation proposes several circuit design techniques for current-steering digital-to-analog converters (DACs) on wireless communication applications to lower the power consumption. Moreover, a compound current cell is also proposed to make current-steering DACs in a system-on-a-chip (SoC) have more functionality for reducing the integration challenges and cost. Hence, three proof-of-concept prototypes are presented to demonstrate these techniques. According to the measurement results of the prototypes, the proposed techniques have good power efficiency and the prototypes can meet wireless communication applications, especially on ultra-wideband (UWB) applications. The prototypes and chip measurement results are depicted as follows: The first one uses a “3 (thermometer) 2 (binary)” segmented structure for reaching a compromise between the circuit complexity and the differential nonlinearity (DNL) error. In addition, we employ bipolar current source cells in this prototype to cut the power consumption while maintaining the same output voltage swing. Moreover, a de-glitch latch is presented to reduce the clock feedthrough from the pass transistors. This prototype was implemented in a standard 0.18-m 1P6M CMOS technology with the active area of 0.19 mm2. The measured integral nonlinearity (INL) and DNL are less than 0.04 and 0.05 least significant bit (LSB), respectively. The measured spurious-free dynamic range (SFDR) is above 30 dB over the complete Nyquist band at the sampling frequency of 1.35 GHz. The power consumption of this DAC is 9.7 mW. The second prototype is a 6-bit 2.7-GS/s DAC. In this prototype, a “2 (thermometer) 4 (binary)” segmented architecture is chosen to make a compromise between the current source cell’s area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DAC’s dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in analog and digital parts, respectively. Moreover, the compact de-glitch latch simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13-m 1P8M CMOS technology with the active area of 0.0585 mm2. The measured DNL and INL are less than 0.09 and 0.11 LSB, respectively. The measured SFDR is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW for a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step. In the third one, a compound current cell, with the properties of N-type, P-type, and bipolar ones, is proposed and utilized in a current-steering DAC to satisfy the application of rail-to-rail voltage sources. Additionally, a DAC with the cells also has a high speed fashion. Therefore, the presented DAC with the cells meets both communication and rail-to-rail voltage-source applications. Moreover, the effective output voltage step size is improved by appropriately switching these cells and connecting one of gain control resisters, resulting in a about 6.4-mV step size in a 1.2-V supply. Furthermore, this DAC was implemented in a standard low-power 90-nm 1P9M CMOS technology with the active area of 0.045 mm2. The measured SFDR is more than 36 dB over the Nyquist frequency at 3 GS/s, and the DAC consumes 8.32 mW for a near-Nyquist sinusoidal output at the sampling rate of 3 GS/s.
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Huang, Su-Ling, and 黃素鈴. "The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/76371604221474286432.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
97
This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-�慆 1P6M CMOS process. The measured results show that the differential nonlinearity (DNL) is less than 0.35 LSB (Least Significant Bit), and the integral nonlinearity (INL) is less than 0.6 LSB. The spurious free dynamic range (SFDR) is 60.63 dB with a 25-MHz input signal at a 500-MS/s sampling rate. The power consumption is 28 mW, and the core area is 0.4536 mm2. Moreover, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters. This scheme includes the current subtraction circuit to increase the sampling current accuracy and the selected-code method to reduce the testing time. As a result, the proposed method can greatly shorten the test time and relax the demands on high precision test equipments, and consequently reduce test cost significantly.