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Relevant bibliographies by topics / Cyclic Redundancy Check

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Academic literature on the topic 'Cyclic Redundancy Check'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 June 2025

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Journal articles on the topic "Cyclic Redundancy Check"

1

Baicheva, Tsonka, Stefan Dodunekov, and Peter Kazakov. "On the cyclic redundancy-check codes with 8-bit redundancy." Computer Communications 21, no. 11 (1998): 1030–33. http://dx.doi.org/10.1016/s0140-3664(98)00165-0.

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LIANG, Haihua, and Lina PAN. "Method of fast cyclic redundancy check reverse decoding." Journal of Computer Applications 33, no. 7 (2013): 1833–35. http://dx.doi.org/10.3724/sp.j.1087.2013.01833.

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3

Li, S. Henry, and Charles A. Zukowski. "Self-timed cyclic redundancy check (CRC) in VLSI." Computer Standards & Interfaces 20, no. 6-7 (1999): 440. http://dx.doi.org/10.1016/s0920-5489(99)90902-9.

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Mahajan, Rita, Komal Devi, and Deepak Bagai. "Area efficient parallel lfsr for cyclic redundancy check." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1755. http://dx.doi.org/10.11591/ijece.v10i2.pp1755-1763.

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Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.

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Davis, J. A., M. Mowbray, and S. Crouch. "Finding cyclic redundancy check polynomials for multilevel systems." IEEE Transactions on Communications 46, no. 10 (1998): 1250–53. http://dx.doi.org/10.1109/26.725299.

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Gao, Wei, and Zhong Tang. "Realization of CRC (Cyclic Redundancy Check) Based on LabView." Applied Mechanics and Materials 530-531 (February 2014): 686–89. http://dx.doi.org/10.4028/www.scientific.net/amm.530-531.686.

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Algorithm and characteristics of CRC were investigated, and a pipeline algorithm steps to achieve it was introduced. The Modbus protocol RTU mode with CRC-16 was developed based on LabView using two methods, embedded c statements and graphical language based on LabView2012. The programs developed were verified in a serial communication system consist of infrared temperature robe and IPC. The successful embodies the reliability and the high efficiency of CRC, provides examples of a specific CRC-16 check.

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Baicheva, T., S. Dodunekov, and P. Kazakov. "Undetected error probability performance of cyclic redundancy-check codes of 16-bit redundancy." IEE Proceedings - Communications 147, no. 5 (2000): 253. http://dx.doi.org/10.1049/ip-com:20000649.

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SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i

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Mathew, Neepa P., and Anith Mohan. "Matrix Code Based Error Correction for LUT Based Cyclic Redundancy Check." Procedia Technology 25 (2016): 590–97. http://dx.doi.org/10.1016/j.protcy.2016.08.149.

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Sam Daliri, Mahya, Reza Faghih Mirzaee, Keivan Navi, and Nader Bagherzadeh. "Ternary cyclic redundancy check by a new hardware-friendly ternary operator." Microelectronics Journal 54 (August 2016): 126–37. http://dx.doi.org/10.1016/j.mejo.2016.04.018.

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Dissertations / Theses on the topic "Cyclic Redundancy Check"

1

Chin, Miao. "Complementary metal oxide silicon cyclic redundancy check generators." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28050.

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Yoon, Hee Byung. "The error performance analysis over cyclic redundancy check codes." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28171.

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The burst error is generated in digital communication networks by various unpredictable conditions, which occur at high error rates, for short durations, and can impact services. To completely describe a burst error one has to know the bit pattern. This is impossible in practice on working systems. Therefore, under the memoryless binary symmetric channel (MBSC) assumptions, the performance evaluation or estimation schemes for digital signal 1 (DS1) transmission systems carrying live traffic is an interesting and important problem. This study will present some analytical methods, leading to efficient detecting algorithms of burst error using cyclic redundancy check (CRC) code. The definition of burst error is introduced using three different models. Among the three burst error models, the mathematical model is used in this study. The probability density function, function(b) of burst error of length b is proposed. The performance of CRC-n codes is evaluated and analyzed using function(b) through the use of a computer simulation model within CRC block burst error. The simulation result shows that the mean block burst error tends to approach the pattern of the burst error which random bit errors generate

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Cheng, Yuelong, and Xiaoying Ma. "Cyclic Redundancy Check for Zigbee-Based Meeting Attendance Registration System." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-12629.

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The research accomplished in this dissertation is focused on the design of effective solutions to the problem that error codes occur in the ZigBee-based meeting attendance registration system. In this work, several different check algorithms are compared, and the powerful error-detecting Cyclic Redundancy Check (CRC) algorithm is studied. In view of the features of the meeting attendance registration system, we implement the check module of CRC-8. This work also considers the data reliability. We assume use retransmission mechanism to ensure the validity and completeness of transmission data. Finally, the potential technical improvement and future work are presented.

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Vasudevan, Siddarth. "Design and Development of a CubeSat Hardware Architecture with COTS MPSoC using Radiation Mitigation Techniques." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-285577.

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CubeSat missions needs components that are tolerant against the radiation in space. The hardware components must be reliable, and it must not compromise the functionality on-board during the mission. At the same time, the cost of hardware and its development should not be high. Hence, this thesis discusses the design and development of a CubeSat architecture using a Commercial Off-The- Shelf (COTS) Multi-Processor System on Chip (MPSoC). The architecture employs an affordable Rad-Hard Micro-Controller Unit as a Supervisor for the MPSoC. Also, it uses several radiation mitigation techniques such as the Latch-up protection circuit to protect it against Single-Event Latch-ups (SELs), Readback scrubbing for Non- Volatile Memories (NVMs) such as NOR Flash and Configuration scrubbing for the FPGA present in the MPSoC to protect it against Single-Event Upset (SEU)s, reliable communication using Cyclic Redundancy Check (CRC) and Space packet protocol. Apart from such functionalities, the Supervisor executes tasks such as Watchdog that monitors the liveliness of the applications running in the MPSoC, data logging, performing Over-The-Air Software/Firmware update. The thesis work implements functionalities such as Communication, Readback memory scrubbing, Configuration scrubbing using SEM-IP, Watchdog, and Software/Firmware update. The execution times of the functionalities are presented for the application done in the Supervisor. As for the Configuration scrubbing that was implemented in Programmable Logic (PL)/FPGA, results of area and latency are reported.<br>CubeSat-uppdrag behöver komponenter som är toleranta mot strålningen i rymden. Maskinvarukomponenterna måste vara pålitliga och funktionaliteten ombord får inte äventyras under uppdraget. Samtidigt bör kostnaden för hårdvara och dess utveckling inte vara hög. Därför diskuterar denna avhandling design och utveckling av en CubeSatarkitektur med hjälp av COTS (eng. Custom-off-The-Shelf) MPSoC (eng. Multi Processor System-on-Chip). Arkitekturen använder en prisvärd strålningshärdad (eng. Rad-Hard) Micro-Controller Unit(MCU) som Övervakare för MPSoC:en och använder också flera tekniker för att begränsa strålningens effekter såsom kretser för att skydda kretsen från s.k. Single Event Latch-Ups (SELs), återläsningsskrubbning för icke-volatila minnen (eng. Non-Volatile Memories) NVMs som NOR Flash och skrubbning av konfigurationsminnet skrubbning för FPGA:er i MPSoC:en för att skydda dem mot Single-Event Upsets (SEUs), och tillhandahålla pålitlig kommunikation mha CRC och Space Packet Protocol. Bortsett från sådana funktioner utför Övervakaren uppgifter som Watchdog för att övervaka att applikationerna som körs i MPSoC:en fortfarande är vid liv, dataloggning, och Over- the-Air-uppdateringar av programvaran/Firmware. Examensarbetet implementerar funktioner såsom kommunikation, återläsningsskrubbning av minnet, konfigurationsminnesskrubbning mha SEM- IP, Watchdog och uppdatering av programvara/firmware. Exekveringstiderna för utförandet av funktionerna presenteras för den applikationen som körs i Övervakaren. När det gäller konfigurationsminnesskrubbningen som implementerats i den programmerbara logiken i FPGA:n, rapporteras area och latens.

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Chang, Li-Yuan, and 張力元. "High-Speed Parallel Cyclic Redundancy Check Circuit." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/97590893794310197308.

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碩士<br>大葉大學<br>電信工程學系碩士班<br>94<br>Error Control Coding is widely used in data communications and storage devices as a powerful method for dealing with data errors. It also applide to many other fields such as the testing of integrated circuits and the detection of lofical faults. In this thesis, we develop the advance parallel Burst Error Correcting Code circuits. We use combinational circuit to compute syndrome and error patterns, and using FPGA board to implement our Fire Code Decoder.

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Alves, José Domingos Resende Gomes Lopes. "Interface Ethernet para um testador de sistemas electrónicos do Tilecal." Master's thesis, 2012. http://hdl.handle.net/10451/9156.

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Tese de mestrado em Engenharia Física, apresentada à Universidade de Lisboa, através da Faculdade de Ciências, 2012<br>Este trabalho foi realizado no âmbito da actualização de um testador de sistemas electrónicos do calorímetro hadrônico Tilecal da experiência ATLAS/CERN. Este testador, o MobiDICK 4, é implementado de forma a comunicar com um computador através de uma interface Ethernet implementada numa FPGA, tendo sido necessário efectuar testes às interfaces Ethernet disponíveis para este tipo de implementação. Uma das funcionalidades do referido testador é a verificação da integridade de dados enviados pelo sistema electrónico de frontaria instalado no TileCal. Foi também implementado, no âmbito deste trabalho, um algoritmo de verificação de integridade de dados chamado de Cyclic Redundancy Check (CRC). O teste das interfaces foi realizado através da implementação de um sistema de comunicação no laboratório de electrónica da FCUL (Faculdade de Ciências da Universidade de Lisboa), operando em modo full-duplex, no qual se testou a comunicação Ethernet entre uma placa ML605 equipada com uma FPGA Virtex-6 da Xilinx, e um computador, com recurso ao protocolo TCP/IP. Foram implementadas e testadas duas interfaces Ethernet disponibilizadas pela Xilinx: as interfaces Tri-mode Ethernet Media Access Control (TMAC) e Ethernet Lite Media Access Control (ELM), num sistema embebido controlado pelo microprocessador soft-core embebido MicroBlaze. A implementação e os testes dessas interfaces Ethernet foram efectuados no ambiente Integrated Software Environment (ISE) da Xilinx com recurso às ferramentas existentes na plataforma Embedded Development Kit (EDK). A ferramenta EDK permite a implementação rápida de um sistema embebido completo e funcional, incluindo um microprocessador embebido, para ser configurado numa FPGA da Xilinx. O algoritmo de verificação de dados recebidos pelo testador (enviados pela electrónica de frontaria) foi implementado no CERN, numa placa ML507 equipada com uma FPGA Virtex-5 da Xilinx. Esta placa é a placa de controlo do referido testador MobiDICK 4. Após a implementação foram realizadas testes de validação, numa situação real de aquisição de dados da electrónica de frontaria.<br>The present work was developed in the scope of an update of a tester of the electronics systems of the hadronic calorimeter TileCal of the ATLAS experiment at CERN. This tester, MobiDICK 4, communicates with a user’s computer via an Ethernet interface implemented in FPGA. Tests of Ethernet interfaces were required to determine the one more suitable for the tester. Another functionality of this tester is to check the integrity of data sent by the front-end electronics system of the TileCal, so an algorithm to do this task was implemented in the scope of this work. The Ethernet interfaces’ tests were performed by implementing a communication system in full-duplex mode in our electronics laboratory, where the Ethernet communications between a Xilinx ML605 board equipped with a Virtex-6 FPGA, and a computer, using the TCP/IP protocol was tested. Two Ethernet interfaces available in the Xilinx’s tools were implemented and tested: the Tri-mode Ethernet Media Access Control (TMAC) interface and the Ethernet Lite Media Access Control (ELM) interface, incorporated in an embedded system controlled by the embedded soft-core microprocessor MicroBlaze. The implementation and tests were performed using the Integrated Software Environment (ISE) from Xilinx, and the resources available in the Embedded Development Kit (EDK). EDK allows a simple way to implement a complete and functional embedded system with a microprocessor for deploying in a Xilinx’s FPGA. The data integrity check algorithm was implemented and tested in the control board of the tester, the ML507 board equipped with a Virtex-5 FPGA. This algorithm will be able to check the data integrity in data sent by TileCal during tests. After the implementation, validation tests were performed in a real situation of data acquisition from the front-end electronics system of the TileCal.

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Lee, Min Han, and 李旻翰. "Successive Cancellation List Decoding of Polar Codes with Multiple Nested Cyclic Redundancy Checks." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/20146117222228424432.

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碩士<br>國立清華大學<br>電機工程學系<br>104<br>In this thesis, we use multiple nested CRCs in the successive cancellation list decoding (SCLD) of polar codes instead of one single CRC in the literature. The method is to divide the source bits in one block into multiple parts, where each part adds one nested CRC. And all those bits, including source bits and check bits, become the information bits of polar codes to be encoded into a codeword. After the transmitter transmits the codeword, the receiver will use successive cancellation list decoding with multiple nested CRCs to decode the word. Simulation results show that multiple nested CRCs generally outperform a single CRC in the successive cancellation list decoding of polar codes.

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Books on the topic "Cyclic Redundancy Check"

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Koh, H. K. Erasure correction using cyclic redundancy check codes. UMIST, 1993.

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Chin, Miao. Complementary metal oxide silicon cyclic redundancy check generators. Naval Postgraduate School, 1991.

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Yoon, Hee Byung. The error performance analysis over cyclic redundancy check codes. Naval Postgraduate School, 1991.

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Book chapters on the topic "Cyclic Redundancy Check"

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Fujimoto, Kazuhisa. "Checksum and Cyclic Redundancy Check Mechanism." In Encyclopedia of Database Systems. Springer New York, 2018. http://dx.doi.org/10.1007/978-1-4614-8265-9_1474.

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Wada, Kenichi. "Checksum and Cyclic Redundancy Check Mechanism." In Encyclopedia of Database Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-39940-9_1474.

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Fujimoto, Kazuhisa. "Checksum and Cyclic Redundancy Check Mechanism." In Encyclopedia of Database Systems. Springer New York, 2016. http://dx.doi.org/10.1007/978-1-4899-7993-3_1474-2.

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Gupta, Megha. "Cyclic Redundancy Check Based Data Authentication in Opportunistic Networks." In Lecture Notes on Data Engineering and Communications Technologies. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11437-4_2.

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Pavan Kumar, C., and R. Selvakumar. "Authentication Protocol Using Error Correcting Codes and Cyclic Redundancy Check." In Wireless Algorithms, Systems, and Applications. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-94268-1_80.

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Lin, Chu-Hsing, Jung-Chun Liu, Wei-Cheng Hsu, Hsing-Weng Wang, Wei-Chih Lin, and Jian-Wei Li. "Image Tampering Detection and Recovery Using Dual Watermarks and Cyclic Redundancy Checks." In Advanced Communication and Networking. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13405-0_14.

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"Cyclic Redundancy Check (CRC)." In Encyclopedia of Database Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-39940-9_2334.

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"Cyclic redundancy check (CRC) program listing." In Practical Data Communications for Instrumentation and Control. Elsevier, 2003. http://dx.doi.org/10.1016/b978-075065797-6/50015-0.

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"Design and implementation of cyclic redundancy check algorithm." In Computing, Control, Information and Education Engineering. CRC Press, 2015. http://dx.doi.org/10.1201/b18828-91.

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Sang, Shengju. "Design and implementation of Cyclic Redundancy Check in power dispatching automation." In Advances in Energy Equipment Science and Engineering. CRC Press, 2015. http://dx.doi.org/10.1201/b19126-344.

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Conference papers on the topic "Cyclic Redundancy Check"

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Walma, Mathys. "Pipelined Cyclic Redundancy Check (CRC) Calculation." In 2007 16th International Conference on Computer Communications and Networks. IEEE, 2007. http://dx.doi.org/10.1109/icccn.2007.4317846.

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Zhang, Xinmiao, and Yok Jye Tang. "Low-Complexity Parallel Cyclic Redundancy Check." In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021. http://dx.doi.org/10.1109/iscas51556.2021.9401679.

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Xu, Zhanqi, Aijun Wen, and Zengji Liu. "Some transforms in cyclic redundancy check (CRC) computation." In 2011 International Conference on Electrical and Control Engineering (ICECE). IEEE, 2011. http://dx.doi.org/10.1109/iceceng.2011.6057364.

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Sheng-Ju, Sang. "Implementation of Cyclic Redundancy Check in Data Communication." In 2015 International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2015. http://dx.doi.org/10.1109/cicn.2015.108.

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Yan-Fei Li, Hong-Jun Wang, and Hua Li. "A RFID algorithm based on Cyclic Redundancy Check." In 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication (2009 ASID). IEEE, 2009. http://dx.doi.org/10.1109/icasid.2009.5276899.

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Sridevi, Nandivada, K. Jamal, and Kiran Mannem. "Implementation of Cyclic Redundancy Check in Data Recovery." In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2021. http://dx.doi.org/10.1109/icesc51422.2021.9532802.

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Singh, Anil Kumar. "Comprehensive study of error detection by cyclic redundancy check." In 2017 2nd International Conference for Convergence in Technology (I2CT). IEEE, 2017. http://dx.doi.org/10.1109/i2ct.2017.8226191.

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Abdulnabi, Mohamed S., and Hisham Ahmed. "Design of Efficient Cyclic Redundancy Check-32 using FPGA." In 2018 International Conference on Computer, Control, Electrical, and Electronics Engineering (ICCCEEE). IEEE, 2018. http://dx.doi.org/10.1109/iccceee.2018.8515877.

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Peng, Jianfen, Yajian Zhou, and Yixian Yang. "Cyclic redundancy code check algorithm based on small lookup table." In 2009 IEEE International Conference on Communications Technology and Applications (ICCTA). IEEE, 2009. http://dx.doi.org/10.1109/iccomta.2009.5349133.

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Yu, Zong-zuo, and Guo Ying. "The design of cyclic redundancy check module based on FPGA." In 2011 2nd International Conference on Control, Instrumentation, and Automation (ICCIA). IEEE, 2011. http://dx.doi.org/10.1109/icciautom.2011.6183970.

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Reports on the topic "Cyclic Redundancy Check"

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Sheinwald, D., J. Satran, P. Thaler, and V. Cavanna. Internet Protocol Small Computer System Interface (iSCSI) Cyclic Redundancy Check (CRC)/Checksum Considerations. RFC Editor, 2002. http://dx.doi.org/10.17487/rfc3385.

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