Relevant bibliographies by topics / Cyclic redundancy check code

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  2. Dissertations / Theses
  3. Books
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Academic literature on the topic 'Cyclic redundancy check code'

Author: Grafiati
Published: 5 June 2025
Last updated: 24 June 2025

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Journal articles on the topic "Cyclic redundancy check code"

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Tran, Thang Viet, Giao N. Pham, Anh N. Bui, et al. "Hardware Designs of Cyclic Redundancy Check Code with Calculation Time Trade-Off Strategy." International Journal of Emerging Technology and Advanced Engineering 12, no. 6 (2022): 170–76. http://dx.doi.org/10.46338/ijetae0622_06.

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This paper will discuss the design of cyclic redundancy check code (CRC), a most popular error detecting scheme in intelligent communication. At first, the concepts of CRC are given in detail with mathematical model and software simulation in python scripts. And mainly, with calculation time trade-off strategy, we provide the CRC hardware design with three architecture models serial, parallel, hybrid serial and parallel. Keywords: Error Detection Scheme; Cyclic Redundancy Check; Python; Verilog HDL; Digital System Design
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Deng, Jinxiang. "Evaluating the EVENODD Code: Principles, Applications, and Future Prospects in Data Storage Systems." ITM Web of Conferences 73 (2025): 03019. https://doi.org/10.1051/itmconf/20257303019.

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In modern data storage and transmission, ensuring data integrity and reliability is critical due to potential losses or corruption caused by channel instability and system errors. Check codes have been developed to address these issues, allowing recovery of the original data even when errors occur. This paper provides a comprehensive analysis of the EVENODD code, a widely used parity code in error detection and correction applications. The fundamental principle of the EVENODD code relies on adding a binary check bit to ensure that the count of ones in the data string is either even or odd, depending on the desired configuration. Its implementation in Redundant Array of Independent Disks level 6 architecture highlights the code’s ability to improve data reliability by incorporating dual parity, enhancing fault tolerance in distributed systems. The advantages and limitations of EVENODD, such as its efficiency in single-bit error detection but inability to correct multi-bit errors, are examined. Additionally, comparisons are made with similar codes, including Longitudinal Redundancy Check and Cyclic Redundancy Check, to showcase their respective strengths and use cases. The paper discusses the EVENODD code’s industrial applications, particularly in satellite remote sensing and library databases, where data integrity is paramount. Future directions include optimizing the code's performance and cost-effectiveness for large- scale data storage and transmission environments, promoting secure and reliable information systems.
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Jaekyun Moon, Jihoon Park, and Jun Lee. "Cyclic redundancy check code based high-rate error-detection code for perpendicular recording." IEEE Transactions on Magnetics 42, no. 5 (2006): 1626–28. http://dx.doi.org/10.1109/tmag.2006.870444.

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SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
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Mahajan, Rita, Komal Devi, and Deepak Bagai. "Area efficient parallel lfsr for cyclic redundancy check." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1755. http://dx.doi.org/10.11591/ijece.v10i2.pp1755-1763.

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Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
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Rita, Mahajan, Devi Komal, and Bagai Deepak. "Area efficient parallel LFSR for cyclic redundancy check." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1755–63. https://doi.org/10.11591/ijece.v10i2.pp1755-1763.

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Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
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Zhang, Yimeng, Zhen Zuo, Sida Li, and Wenhao Jin. "Fast Classification of Error Correcting Codes based on Syndrome a Posteriori Probability Spectrum for Intelligent Communication." Journal of Physics: Conference Series 2829, no. 1 (2024): 012014. http://dx.doi.org/10.1088/1742-6596/2829/1/012014.

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Abstract Classification of channel codes has drawn widespread concern for a long time. In this letter, we propose a posteriori probability based approach to classify cyclic redundancy check codes and convolutional codes. We defined the posteriori probability spectrum to clarify the parity-check relationship between the intercepted codewords and the candidate parity-check vector generated by traversing. We theoretically explained that the posteriori probability spectrum of cyclic redundancy check codes and convolutional codes show clear distinctions. We further specify the feature parameter generated from the posteriori probability spectrum to do classification. Simulation results show that the posteriori probability spectrum for cyclic redundancy check codes and convolutional codes are significantly different. The proposed approach outperforms traditional Gauss-Jordan elimination through pivoting approach in classification accuracy.
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Ahmed, Md Firoz, Md Sofiqul Islam, and Abu Zafor Md Touhidul Islam. "Comparative Performance Assessment of V-Blast Encoded 8×8 MIMO MC-CDMA Wireless System." International Journal on AdHoc Networking Systems 11, no. 2 (2021): 1–7. http://dx.doi.org/10.5121/ijans.2021.11201.

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The bit error rate performance of a V-Blast encoded 8x8 MIMO MC-CDMA wireless communication system for different signal detection (MMSE and ZF) and digital modulation (BPSK, QPSK, DPSK, and 4QAM) schemes for grayscale image transmission has been investigated in this paper. The proposed wireless system employ ½-rated Convolution and cyclic redundancy check (CRC) channel encoding over the AWGN channel and Walsh Hadamard code as an orthogonal spread code. The present Matlab based simulation study demonstrates that the V-Blast encoded 8×8 MIMO MC-CDMA wireless system with the employment of 1⁄2- rated convolution and cyclic redundancy check (CRC) channel encoding strategies shows good performance utilizing BPSK digital modulation and ZF signal detection scheme in grayscale image transmission.
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Baicheva, Tsonka, Stefan Dodunekov, and Peter Kazakov. "On the cyclic redundancy-check codes with 8-bit redundancy." Computer Communications 21, no. 11 (1998): 1030–33. http://dx.doi.org/10.1016/s0140-3664(98)00165-0.

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Mathew, Neepa P., and Anith Mohan. "Matrix Code Based Error Correction for LUT Based Cyclic Redundancy Check." Procedia Technology 25 (2016): 590–97. http://dx.doi.org/10.1016/j.protcy.2016.08.149.

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Dissertations / Theses on the topic "Cyclic redundancy check code"

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Yoon, Hee Byung. "The error performance analysis over cyclic redundancy check codes." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28171.

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The burst error is generated in digital communication networks by various unpredictable conditions, which occur at high error rates, for short durations, and can impact services. To completely describe a burst error one has to know the bit pattern. This is impossible in practice on working systems. Therefore, under the memoryless binary symmetric channel (MBSC) assumptions, the performance evaluation or estimation schemes for digital signal 1 (DS1) transmission systems carrying live traffic is an interesting and important problem. This study will present some analytical methods, leading to efficient detecting algorithms of burst error using cyclic redundancy check (CRC) code. The definition of burst error is introduced using three different models. Among the three burst error models, the mathematical model is used in this study. The probability density function, function(b) of burst error of length b is proposed. The performance of CRC-n codes is evaluated and analyzed using function(b) through the use of a computer simulation model within CRC block burst error. The simulation result shows that the mean block burst error tends to approach the pattern of the burst error which random bit errors generate
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Chin, Miao. "Complementary metal oxide silicon cyclic redundancy check generators." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28050.

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Cheng, Yuelong, and Xiaoying Ma. "Cyclic Redundancy Check for Zigbee-Based Meeting Attendance Registration System." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-12629.

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The research accomplished in this dissertation is focused on the design of effective solutions to the problem that error codes occur in the ZigBee-based meeting attendance registration system. In this work, several different check algorithms are compared, and the powerful error-detecting Cyclic Redundancy Check (CRC) algorithm is studied. In view of the features of the meeting attendance registration system, we implement the check module of CRC-8. This work also considers the data reliability. We assume use retransmission mechanism to ensure the validity and completeness of transmission data. Finally, the potential technical improvement and future work are presented.
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Von, Leipzig Mirko. "Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/96835.

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Thesis (MEng)--Stellenbosch University, 2015.<br>ENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investigates binary quasi-cyclic LDPC codes and designs a generic, flexible VHDL decoder. The decoder is further enhanced to automatically select the most likely decoder based on the initial a posterior probability of the parity-check equation syndromes. A software system is developed that generates hardware code for such a decoder based on a small user specification. The system is extended to provide performance simulations for this generated decoder.<br>AFRIKAANSE OPSOMMING: Iteratiewe foutkorreksiekodes soos LDPC-kodes word wyd gebruik in moderne voorwaartse foutkorreksiestelsels. ’n Subklas van LDPC-kodes, bekend as kwasisikliese LDPC-kodes, word in verskeie hoëspoed-kommunikasie- en video-uitsaaistelselstandaarde gebruik. Hierdie standaarde inkorporeer verskeie kodes van wisselende lengtes en kodetempos, en vereis hoë deurset. Buigsame apparatuur, wat die vermoë het om ’n verskeidenheid kwasisikliese LDPC-kodes te dekodeer, is gevolglik van belang. Hierdie tesis ondersoek binêre kwasisikliese LDPC-kodes, en ontwerp ’n generiese, buigsame VHDL-dekodeerder. Die dekodeerder word verder verbeter om outomaties die mees waarskynlike dekodeerder te selekteer, gebaseer op die aanvanklike a posteriori-waarskynlikheid van die pariteitstoetsvergelykings se sindrome. ’n Programmatuurstelsel word ontwikkel wat die fermware-kode vir so ’n dekodeerder genereer, gebaseer op ’n beknopte gebruikerspesifikasie. Die stelsel word uitgebrei om werksverrigting te simuleer vir die gegenereerde dekodeerder.
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Grymel, Martin-Thomas. "Error control with binary cyclic codes." Thesis, University of Manchester, 2013. https://www.research.manchester.ac.uk/portal/en/theses/error-control-with-binary-cyclic-codes(a5750b4a-e4d6-49a8-915b-3e015387ad36).html.

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Error-control codes provide a mechanism to increase the reliability of digital data being processed, transmitted, or stored under noisy conditions. Cyclic codes constitute an important class of error-control code, offering powerful error detection and correction capabilities. They can easily be generated and verified in hardware, which makes them particularly well suited to the practical use as error detecting codes.A cyclic code is based on a generator polynomial which determines its properties including the specific error detection strength. The optimal choice of polynomial depends on many factors that may be influenced by the underlying application. It is therefore advantageous to employ programmable cyclic code hardware that allows a flexible choice of polynomial to be applied to different requirements. A novel method is presented in this thesis to realise programmable cyclic code circuits that are fast, energy-efficient and minimise implementation resources.It can be shown that the correction of a single-bit error on the basis of a cyclic code is equivalent to the solution of an instance of the discrete logarithm problem. A new approach is proposed for computing discrete logarithms; this leads to a generic deterministic algorithm for analysed group orders that equal Mersenne numbers with an exponent of a power of two. The algorithm exhibits a worst-case runtime in the order of the square root of the group order and constant space requirements.This thesis establishes new relationships for finite fields that are represented as the polynomial ring over the binary field modulo a primitive polynomial. With a subset of these properties, a novel approach is developed for the solution of the discrete logarithm in the multiplicative groups of these fields. This leads to a deterministic algorithm for small group orders that has linear space and linearithmic time requirements in the degree of defining polynomial, enabling an efficient correction of single-bit errors based on the corresponding cyclic codes.
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Price, Aiden K. "Improved constructions of low-density parity-check codes." Thesis, Queensland University of Technology, 2019. https://eprints.qut.edu.au/128373/1/Aiden_Price_Thesis.pdf.

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There is an ongoing need to improve the efficiency and error-correcting performance of error correcting codes, which are widely used to enhance accuracy when retrieving or communicating information. This research investigates several potential improvements to a high-performing class of error correcting codes known as low-density parity-check (LDPC) codes. The results presented here further the known literature surrounding a specific class of functions (Alltop functions). Additionally, this work demonstrates ways of manipulating existing LDPC code constructions using relaxed difference sets to provide constructions with far more flexible code parameters. These constructions have competitive performance when compared to relevant modern codes.
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Grobler, Trienko Lups. "Fountain codes and their typical application in wireless standards like edge." Diss., University of Pretoria, 2008. http://hdl.handle.net/2263/25381.

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One of the most important technologies used in modern communication systems is channel coding. Channel coding dates back to a paper published by Shannon in 1948 [1] entitled “A Mathematical Theory of Communication”. The basic idea behind channel coding is to send redundant information (parity) together with a message to make the transmission more error resistant. There are different types of codes that can be used to generate the parity required, including block, convolutional and concatenated codes. A special subclass of codes consisting of the codes mentioned in the previous paragraph, is sparse graph codes. The structure of sparse graph codes can be depicted via a graphical representation: the factor graph which has sparse connections between its elements. Codes belonging to this subclass include Low-Density-Parity-Check (LDPC) codes, Repeat Accumulate (RA), Turbo and fountain codes. These codes can be decoded by using the belief propagation algorithm, an iterative algorithm where probabilistic information is passed to the nodes of the graph. This dissertation focuses on noisy decoding of fountain codes using belief propagation decoding. Fountain codes were originally developed for erasure channels, but since any factor graph can be decoded using belief propagation, noisy decoding of fountain codes can easily be accomplished. Three fountain codes namely Tornado, Luby Transform (LT) and Raptor codes were investigated during this dissertation. The following results were obtained: <ol> <li>The Tornado graph structure is unsuitable for noisy decoding since the code structure protects the first layer of parity instead of the original message bits (a Tornado graph consists of more than one layer).</li> <li> The successful decoding of systematic LT codes were verified.</li> <li>A systematic Raptor code was introduced and successfully decoded. The simulation results show that the Raptor graph structure can improve on its constituent codes (a Raptor code consists of more than one code).</li></ol> Lastly an LT code was used to replace the convolutional incremental redundancy scheme used by the 2G mobile standard Enhanced Data Rates for GSM Evolution (EDGE). The results show that a fountain incremental redundancy scheme outperforms a convolutional approach if the frame lengths are long enough. For the EDGE platform the results also showed that the fountain incremental redundancy scheme outperforms the convolutional approach after the second transmission is received. Although EDGE is an older technology, it still remains a good platform for testing different incremental redundancy schemes, since it was one of the first platforms to use incremental redundancy.<br>Dissertation (MEng)--University of Pretoria, 2008.<br>Electrical, Electronic and Computer Engineering<br>MEng<br>unrestricted
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Vasudevan, Siddarth. "Design and Development of a CubeSat Hardware Architecture with COTS MPSoC using Radiation Mitigation Techniques." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-285577.

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CubeSat missions needs components that are tolerant against the radiation in space. The hardware components must be reliable, and it must not compromise the functionality on-board during the mission. At the same time, the cost of hardware and its development should not be high. Hence, this thesis discusses the design and development of a CubeSat architecture using a Commercial Off-The- Shelf (COTS) Multi-Processor System on Chip (MPSoC). The architecture employs an affordable Rad-Hard Micro-Controller Unit as a Supervisor for the MPSoC. Also, it uses several radiation mitigation techniques such as the Latch-up protection circuit to protect it against Single-Event Latch-ups (SELs), Readback scrubbing for Non- Volatile Memories (NVMs) such as NOR Flash and Configuration scrubbing for the FPGA present in the MPSoC to protect it against Single-Event Upset (SEU)s, reliable communication using Cyclic Redundancy Check (CRC) and Space packet protocol. Apart from such functionalities, the Supervisor executes tasks such as Watchdog that monitors the liveliness of the applications running in the MPSoC, data logging, performing Over-The-Air Software/Firmware update. The thesis work implements functionalities such as Communication, Readback memory scrubbing, Configuration scrubbing using SEM-IP, Watchdog, and Software/Firmware update. The execution times of the functionalities are presented for the application done in the Supervisor. As for the Configuration scrubbing that was implemented in Programmable Logic (PL)/FPGA, results of area and latency are reported.<br>CubeSat-uppdrag behöver komponenter som är toleranta mot strålningen i rymden. Maskinvarukomponenterna måste vara pålitliga och funktionaliteten ombord får inte äventyras under uppdraget. Samtidigt bör kostnaden för hårdvara och dess utveckling inte vara hög. Därför diskuterar denna avhandling design och utveckling av en CubeSatarkitektur med hjälp av COTS (eng. Custom-off-The-Shelf) MPSoC (eng. Multi Processor System-on-Chip). Arkitekturen använder en prisvärd strålningshärdad (eng. Rad-Hard) Micro-Controller Unit(MCU) som Övervakare för MPSoC:en och använder också flera tekniker för att begränsa strålningens effekter såsom kretser för att skydda kretsen från s.k. Single Event Latch-Ups (SELs), återläsningsskrubbning för icke-volatila minnen (eng. Non-Volatile Memories) NVMs som NOR Flash och skrubbning av konfigurationsminnet skrubbning för FPGA:er i MPSoC:en för att skydda dem mot Single-Event Upsets (SEUs), och tillhandahålla pålitlig kommunikation mha CRC och Space Packet Protocol. Bortsett från sådana funktioner utför Övervakaren uppgifter som Watchdog för att övervaka att applikationerna som körs i MPSoC:en fortfarande är vid liv, dataloggning, och Over- the-Air-uppdateringar av programvaran/Firmware. Examensarbetet implementerar funktioner såsom kommunikation, återläsningsskrubbning av minnet, konfigurationsminnesskrubbning mha SEM- IP, Watchdog och uppdatering av programvara/firmware. Exekveringstiderna för utförandet av funktionerna presenteras för den applikationen som körs i Övervakaren. När det gäller konfigurationsminnesskrubbningen som implementerats i den programmerbara logiken i FPGA:n, rapporteras area och latens.
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Chang, Li-Yuan, and 張力元. "High-Speed Parallel Cyclic Redundancy Check Circuit." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/97590893794310197308.

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碩士<br>大葉大學<br>電信工程學系碩士班<br>94<br>Error Control Coding is widely used in data communications and storage devices as a powerful method for dealing with data errors. It also applide to many other fields such as the testing of integrated circuits and the detection of lofical faults. In this thesis, we develop the advance parallel Burst Error Correcting Code circuits. We use combinational circuit to compute syndrome and error patterns, and using FPGA board to implement our Fire Code Decoder.
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Lee, Min Han, and 李旻翰. "Successive Cancellation List Decoding of Polar Codes with Multiple Nested Cyclic Redundancy Checks." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/20146117222228424432.

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碩士<br>國立清華大學<br>電機工程學系<br>104<br>In this thesis, we use multiple nested CRCs in the successive cancellation list decoding (SCLD) of polar codes instead of one single CRC in the literature. The method is to divide the source bits in one block into multiple parts, where each part adds one nested CRC. And all those bits, including source bits and check bits, become the information bits of polar codes to be encoded into a codeword. After the transmitter transmits the codeword, the receiver will use successive cancellation list decoding with multiple nested CRCs to decode the word. Simulation results show that multiple nested CRCs generally outperform a single CRC in the successive cancellation list decoding of polar codes.
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Books on the topic "Cyclic redundancy check code"

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Koh, H. K. Erasure correction using cyclic redundancy check codes. UMIST, 1993.

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Yoon, Hee Byung. The error performance analysis over cyclic redundancy check codes. Naval Postgraduate School, 1991.

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Chin, Miao. Complementary metal oxide silicon cyclic redundancy check generators. Naval Postgraduate School, 1991.

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Castagnoli, Guy E. On the minimum distance of long cyclic codes and cyclic redundancy-check codes. 1989.

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Merchant, Kamal. Cyclic Redundancy Check Für Die Industrielle Kommunikation - Probleme, Nutzen und Risiken: Abschätzung der Restfehlerwahrscheinlichkeit Von CRC-Codes. de Gruyter GmbH, Walter, 2013.

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Merchant, Kamal. Cyclic Redundancy Check Für Die Industrielle Kommunikation - Probleme, Nutzen und Risiken: Abschätzung der Restfehlerwahrscheinlichkeit Von CRC-Codes. de Gruyter GmbH, Walter, 2013.

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Boles, Melanie. DsPIC33/PIC24 FRM, 32-Bit Programmable Cyclic Redundancy Check (CRC). Microchip Technology Incorporated, 2018.

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Yang, Ada. PIC32 FRM - Section 60. 32-Bit Programmable Cyclic Redundancy Check (CRC). Microchip Technology Incorporated, 2017.

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Boles, Melanie. PIC32 FRM - Section 60. 32-Bit Programmable Cyclic Redundancy Check (CRC). Microchip Technology Incorporated, 2016.

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Boles, Melanie. PIC32 FRM - Section 60. 32-Bit Programmable Cyclic Redundancy Check (CRC). Microchip Technology Incorporated, 2016.

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Book chapters on the topic "Cyclic redundancy check code"

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Pavan Kumar, C., and R. Selvakumar. "Authentication Protocol Using Error Correcting Codes and Cyclic Redundancy Check." In Wireless Algorithms, Systems, and Applications. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-94268-1_80.

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Fujimoto, Kazuhisa. "Checksum and Cyclic Redundancy Check Mechanism." In Encyclopedia of Database Systems. Springer New York, 2016. http://dx.doi.org/10.1007/978-1-4899-7993-3_1474-2.

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Wada, Kenichi. "Checksum and Cyclic Redundancy Check Mechanism." In Encyclopedia of Database Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-39940-9_1474.

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Fujimoto, Kazuhisa. "Checksum and Cyclic Redundancy Check Mechanism." In Encyclopedia of Database Systems. Springer New York, 2018. http://dx.doi.org/10.1007/978-1-4614-8265-9_1474.

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Gupta, Megha. "Cyclic Redundancy Check Based Data Authentication in Opportunistic Networks." In Lecture Notes on Data Engineering and Communications Technologies. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11437-4_2.

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Patel, Dharmesh Jayantibhai, Pinalkumar Engineer, and Ninad Sunilkumar Bhatt. "Image Communication Using Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) Code." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6229-7_17.

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Ilievska, Natasha. "Optimizing the Error-Detecting Capability of the Quasigroup Redundancy Check Code When Quasigroups of Order 4 are Used for Coding." In Communications in Computer and Information Science. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-83432-5_18.

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"3 Wichtige lineare Block-Codes." In Cyclic Redundancy Check für die industrielle Kommunikation - Probleme, Nutzen und Risiken. Oldenbourg Wissenschaftsverlag, 2013. http://dx.doi.org/10.1524/9783486741933.25.

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"Cyclic Redundancy Check (CRC)." In Encyclopedia of Database Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-39940-9_2334.

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"Cyclic redundancy check (CRC) program listing." In Practical Data Communications for Instrumentation and Control. Elsevier, 2003. http://dx.doi.org/10.1016/b978-075065797-6/50015-0.

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Conference papers on the topic "Cyclic redundancy check code"

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Chen, Xiaomin, Xu Wang, and Sitong Chen. "Design and optimization of feedback retransmission protocol based on cyclic redundancy check." In International Conference on Mechatronics and Intelligent Control (ICMIC 2024), edited by Kun Zhang and Pascal Lorenz. SPIE, 2025. https://doi.org/10.1117/12.3052197.

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Im, Hyungchul, Naeun Park, and Seongsoo Lee. "A Novel Intrusion Detection System Using Cyclic Redundancy Check Field for In-Vehicle Networks." In 2024 IEEE 100th Vehicular Technology Conference (VTC2024-Fall). IEEE, 2024. https://doi.org/10.1109/vtc2024-fall63153.2024.10757603.

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Peng, Jianfen, Yajian Zhou, and Yixian Yang. "Cyclic redundancy code check algorithm based on small lookup table." In 2009 IEEE International Conference on Communications Technology and Applications (ICCTA). IEEE, 2009. http://dx.doi.org/10.1109/iccomta.2009.5349133.

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Xiaoqing, Ge, Liu Guangzu, Zou Jun, and Sun Linlin. "Compiled Code Study of Joint Parity and Cyclic Redundancy Check." In 2022 IEEE 5th International Conference on Electronic Information and Communication Technology (ICEICT). IEEE, 2022. http://dx.doi.org/10.1109/iceict55736.2022.9909046.

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Liang, Weisong, and Haiyang Liu. "Low-Complexity Error Correction Algorithm for Cyclic Redundancy Check Codes." In 2021 7th International Conference on Computer and Communications (ICCC). IEEE, 2021. http://dx.doi.org/10.1109/iccc54389.2021.9674684.

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Yanbin Zhang and Qi Yuan. "A multiple bits error correction method based on cyclic redundancy check codes." In 2008 9th International Conference on Signal Processing (ICSP 2008). IEEE, 2008. http://dx.doi.org/10.1109/icosp.2008.4697490.

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Yang, Zhimin, Shiju Li, Hao Feng, Thomas Honold, and Guanding Yu. "Cross-Layer Iterative Decoding of Irregular LDPC Codes using Cyclic Redundancy Check Codes." In 2009 IEEE Wireless Communications and Networking Conference. IEEE, 2009. http://dx.doi.org/10.1109/wcnc.2009.4917653.

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Khan, Mohammad Ishtiaque, and Muhammad Mostafa Amir Faisal. "Design of Cyclic Redundancy Check (CRC) Code Generator Circuit in Quantum Dot Cellular Automata (QCA) for Communication." In 2023 26th International Conference on Computer and Information Technology (ICCIT). IEEE, 2023. http://dx.doi.org/10.1109/iccit60459.2023.10441331.

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Lv, Yansong, Jianping Li, and Man Hu. "Repeated-Part Adaptive Successive Cancellation List Decoder for Polar Codes with Cyclic Redundancy Check." In 2018 14th IEEE International Conference on Signal Processing (ICSP). IEEE, 2018. http://dx.doi.org/10.1109/icsp.2018.8652469.

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Zhang, Xinmiao, and Yok Jye Tang. "Low-Complexity Parallel Cyclic Redundancy Check." In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021. http://dx.doi.org/10.1109/iscas51556.2021.9401679.

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Reports on the topic "Cyclic redundancy check code"

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Sheinwald, D., J. Satran, P. Thaler, and V. Cavanna. Internet Protocol Small Computer System Interface (iSCSI) Cyclic Redundancy Check (CRC)/Checksum Considerations. RFC Editor, 2002. http://dx.doi.org/10.17487/rfc3385.

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ANTI-WIND CAPACITY CHECK AND COLLAPSE ANALYSIS OF EXISTING TRANSMISSION TOWER. The Hong Kong Institute of Steel Construction, 2022. http://dx.doi.org/10.18057/icass2020.p.046.

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Abstract:
"With the implementation of the new code for the design of overhead transmission line in China, the design check, maintenance and reinforcement for the existing transmission towers are indispensable. In this paper, based on an existing transmission line project, firstly, the differences of the wind load calculations between different design codes are analyzed contrastively, and the safety stock of the tower primary members is checked. Then, the tower’s ultimate bearing capacity is analyzed, in which the parameters of the fiber hinges are determined by the solid element model simulation. Last, the tower collapse process is simulated, and a similar accident case is investigated briefly. It is revealed that by the new code, the evaluated safety stock of this existing tower decreases obviously; at the 1/3 of the tower height and the position under the lowest crossarms, the primary members perform as the weak parts; and the progressive collapse resistance of the tower is low, which is triggered by the primary member buckling. Therefore, to reinforce the weak parts of the existing towers, increase the redundancy to resist a local failure and avoid the total collapse of the entire structural system is imperative."
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