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Journal articles on the topic 'Cyclic redundancy check code'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

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1

Tran, Thang Viet, Giao N. Pham, Anh N. Bui, et al. "Hardware Designs of Cyclic Redundancy Check Code with Calculation Time Trade-Off Strategy." International Journal of Emerging Technology and Advanced Engineering 12, no. 6 (2022): 170–76. http://dx.doi.org/10.46338/ijetae0622_06.

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This paper will discuss the design of cyclic redundancy check code (CRC), a most popular error detecting scheme in intelligent communication. At first, the concepts of CRC are given in detail with mathematical model and software simulation in python scripts. And mainly, with calculation time trade-off strategy, we provide the CRC hardware design with three architecture models serial, parallel, hybrid serial and parallel. Keywords: Error Detection Scheme; Cyclic Redundancy Check; Python; Verilog HDL; Digital System Design

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2

Deng, Jinxiang. "Evaluating the EVENODD Code: Principles, Applications, and Future Prospects in Data Storage Systems." ITM Web of Conferences 73 (2025): 03019. https://doi.org/10.1051/itmconf/20257303019.

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In modern data storage and transmission, ensuring data integrity and reliability is critical due to potential losses or corruption caused by channel instability and system errors. Check codes have been developed to address these issues, allowing recovery of the original data even when errors occur. This paper provides a comprehensive analysis of the EVENODD code, a widely used parity code in error detection and correction applications. The fundamental principle of the EVENODD code relies on adding a binary check bit to ensure that the count of ones in the data string is either even or odd, dep

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3

Jaekyun Moon, Jihoon Park, and Jun Lee. "Cyclic redundancy check code based high-rate error-detection code for perpendicular recording." IEEE Transactions on Magnetics 42, no. 5 (2006): 1626–28. http://dx.doi.org/10.1109/tmag.2006.870444.

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SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Networ

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Mahajan, Rita, Komal Devi, and Deepak Bagai. "Area efficient parallel lfsr for cyclic redundancy check." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1755. http://dx.doi.org/10.11591/ijece.v10i2.pp1755-1763.

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Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a tech

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Rita, Mahajan, Devi Komal, and Bagai Deepak. "Area efficient parallel LFSR for cyclic redundancy check." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1755–63. https://doi.org/10.11591/ijece.v10i2.pp1755-1763.

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Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a tech

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7

Zhang, Yimeng, Zhen Zuo, Sida Li, and Wenhao Jin. "Fast Classification of Error Correcting Codes based on Syndrome a Posteriori Probability Spectrum for Intelligent Communication." Journal of Physics: Conference Series 2829, no. 1 (2024): 012014. http://dx.doi.org/10.1088/1742-6596/2829/1/012014.

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Abstract Classification of channel codes has drawn widespread concern for a long time. In this letter, we propose a posteriori probability based approach to classify cyclic redundancy check codes and convolutional codes. We defined the posteriori probability spectrum to clarify the parity-check relationship between the intercepted codewords and the candidate parity-check vector generated by traversing. We theoretically explained that the posteriori probability spectrum of cyclic redundancy check codes and convolutional codes show clear distinctions. We further specify the feature parameter gen

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8

Ahmed, Md Firoz, Md Sofiqul Islam, and Abu Zafor Md Touhidul Islam. "Comparative Performance Assessment of V-Blast Encoded 8×8 MIMO MC-CDMA Wireless System." International Journal on AdHoc Networking Systems 11, no. 2 (2021): 1–7. http://dx.doi.org/10.5121/ijans.2021.11201.

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The bit error rate performance of a V-Blast encoded 8x8 MIMO MC-CDMA wireless communication system for different signal detection (MMSE and ZF) and digital modulation (BPSK, QPSK, DPSK, and 4QAM) schemes for grayscale image transmission has been investigated in this paper. The proposed wireless system employ ½-rated Convolution and cyclic redundancy check (CRC) channel encoding over the AWGN channel and Walsh Hadamard code as an orthogonal spread code. The present Matlab based simulation study demonstrates that the V-Blast encoded 8×8 MIMO MC-CDMA wireless system with the employment of 1⁄2- ra

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9

Baicheva, Tsonka, Stefan Dodunekov, and Peter Kazakov. "On the cyclic redundancy-check codes with 8-bit redundancy." Computer Communications 21, no. 11 (1998): 1030–33. http://dx.doi.org/10.1016/s0140-3664(98)00165-0.

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10

Mathew, Neepa P., and Anith Mohan. "Matrix Code Based Error Correction for LUT Based Cyclic Redundancy Check." Procedia Technology 25 (2016): 590–97. http://dx.doi.org/10.1016/j.protcy.2016.08.149.

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11

Blyudov, Anton, Dmitry Pivovarov, and Georgiy Pronin. "Power Distribution of Codes with the Lowest Alphabet Redundancy Depending on the Number of Bits and Code Distance." Proceedings of Petersburg Transport University 20, no. 2 (2023): 365–75. http://dx.doi.org/10.20295/1815-588x-2023-2-365-375.

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Purpose: To investigate the dependence of the maximum power of codes on the number of digits and the minimum code distance; to find an approach to determine the optimal rules for constructing the check vector of a separable code from the point of view of ensuring minimal redundancy with a given reliability of message transmission. Methods: Computer simulation has been used to conduct experimental studies. For theoretical studies, the method of analytical review, graph theory, and coding theory have been applied. Results: Theoretical and experimental studies have obtained certain specific cases

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12

Hamizan, Suhaimi, Mohamad Roslina, Mohd Ali Darmawaty, and Abdullah Ezmin. "Cyclic redundancy check-aidedsuccessive cancellation-based polar decoders." Cyclic redundancy check-aidedsuccessive cancellation-based polar decoders 32, no. 2 (2023): 811–18. https://doi.org/10.11591/ijeecs.v32.i2.pp811-818.

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Research on channel coding for network transmission using polar codes has produced excellent results. By removing error redundancy from the decoding process, cyclic redundancy check (CRC) is frequently used by researchers to increase a system’s performance. In prior research, the application of decoder algorithms for polar codes was examined but not thoroughly compared. For the general capabilities of the previously proposed algorithms to be ascertained, it is crucial to analyze the employment of polar decoders especially successive cancellation (SC)-based polar decoders and the use of C

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Ma, Ji Ming, Kai Sui Cai, and Xiao Jiao Li. "A Graphic Expression CRC Algorithm Based on Bytes Operation." Advanced Materials Research 756-759 (September 2013): 1870–74. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.1870.

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In computer network communication, adopted the error-check control methods to reduce the error code frequency of data transmission commonly. The CRC (Cyclic Redundancy Check) method is the best one of them. This paper analyzed the principle and the check rules of CRC algorithm. For the CRC algorithm of bytes operation, proposed a new table-driven algorithm which is visual, compact and easy to be understood. A strict mathematic proof of the CRC algorithm is given. By diagrammatizing, deduct the calculated process of CRC-ITU and CRC-32 code in detail. At the same time, we designed a concise CRC-

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Suhaimi, Hamizan, Roslina Mohamad, Darmawaty Mohd Ali, and Ezmin Abdullah. "Cyclic redundancy check-aided successive cancellation-based polar decoders." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 2 (2023): 811. http://dx.doi.org/10.11591/ijeecs.v32.i2.pp811-818.

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<span>Research on channel coding for network transmission using polar codes has produced excellent results. By removing error redundancy from the decoding process, cyclic redundancy check (CRC) is frequently used by researchers to increase a system’s performance. In prior research, the application of decoder algorithms for polar codes was examined but not thoroughly compared. For the general capabilities of the previously proposed algorithms to be ascertained, it is crucial to analyze the employment of polar decoders especially successive cancellation (SC)-based polar decoders and the us

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Baicheva, T., S. Dodunekov, and P. Kazakov. "Undetected error probability performance of cyclic redundancy-check codes of 16-bit redundancy." IEE Proceedings - Communications 147, no. 5 (2000): 253. http://dx.doi.org/10.1049/ip-com:20000649.

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16

TOLENTINO, Lean Karlo, Maria Victoria PADILLA, and Ronnie SERFA JUAN. "FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code." International Journal of Engineering & Technology 7, no. 3 (2018): 1008. http://dx.doi.org/10.14419/ijet.v7i3.12681.

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To ensure an error-free transmission in packet switching, additional check bits (either header or a payload) are typically appended to the input data of a message for error detection especially in a string of binary code. Normally, it comes from the input message and as a result of a deterministic algorithm after these data have been processed. The receiver system implements the said algorithm, while the transmitter used it to match the reliability of the sent information and detects whether an error bit has occurred or not. The corrupted bits will be corrected, recovered, and matched with the

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Chaturvedi, Swati, Sukrut Pasumarthi, and Nan Wang. "Implementation and Performance Analysis of Two Error Detection and Correction Techniques." International Journal of Interdisciplinary Telecommunications and Networking 10, no. 1 (2018): 36–48. http://dx.doi.org/10.4018/ijitn.2018010103.

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In computer communication and telecommunication applications, error detection and correction techniques must be employed to ensure a reliable data transmission from the source to the destination. Two of the most prevailing techniques, Cyclic Redundancy Check (CRC) detection and Hamming code correction, are implemented and analyzed. The CRC method picks up prominence because it joins three focal points: extraordinary blunder identification capacities, minimal overhead, and simplicity of usage. Moreover, both the CRC and Hamming code are binary linear codes. However, one significant difference i

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18

Park, Daejin. "Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method." Journal of Circuits, Systems and Computers 25, no. 07 (2016): 1650068. http://dx.doi.org/10.1142/s0218126616500687.

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The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binar

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19

Saleh, Adham Hadi, Hayder Khaleel AL-Qaysi, Khalid Awaad Humood, and Tahreer Mahmood. "Design of CRC circuit for 5G system using VHDL." Bulletin of Electrical Engineering and Informatics 12, no. 4 (2023): 2125–35. http://dx.doi.org/10.11591/beei.v12i4.4598.

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low d

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Saleh, Adham Hadi, Hayder Khaleel AL-Qaysi, Khalid Awaad Humood, and Tahreer Mahmood. "Design of CRC circuit for 5G system using VHDL." Bulletin of Electrical Engineering and Informatics 12, no. 4 (2023): 2125–35. http://dx.doi.org/10.11591/eei.v12i4.4598.

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low d

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21

Murata, Takumi, and Hideki Ochiai. "Performance Analysis of CRC Codes for Systematic and Nonsystematic Polar Codes with List Decoding." Wireless Communications and Mobile Computing 2018 (2018): 1–8. http://dx.doi.org/10.1155/2018/7286909.

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Successive cancellation list (SCL) decoding of polar codes is an effective approach that can significantly outperform the original successive cancellation (SC) decoding, provided that proper cyclic redundancy-check (CRC) codes are employed at the stage of candidate selection. Previous studies on CRC-assisted polar codes mostly focus on improvement of the decoding algorithms as well as their implementation, and little attention has been paid to the CRC code structure itself. For the CRC-concatenated polar codes with CRC code as their outer code, the use of longer CRC code leads to reduction of

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Zhang, Wen Wen, Wei Ping Jing, and Bin Jiang. "Optimization Design of the CRC Check for RFID Communication System." Advanced Materials Research 926-930 (May 2014): 1979–83. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.1979.

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The method of cyclic redundancy check (CRC) was been used in the process of RFID communication adopts to ensure that the data was transfer correctly. The principle of CRC was been introduced. The design method about 16-bit CRC code was been gotten through the hardware circuit and hardware description language. And it was compatible with the serial and parallel two kinds of data streams. At the same time it was been verified correctly in RFID communication system. And the results are verified in the specified clock frequency in xc2vp4-6fg256 device in FPGA Xilinx kit using VI-IDL in RTL level.

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23

Glaser, Allan. "The Use of Cyclic Redundancy Check (CRC-32) and Adler-32 Checksums for Source Code Verification." Drug Information Journal 37, no. 2 (2003): 147–54. http://dx.doi.org/10.1177/009286150303700203.

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24

Tran, Dat, Shahid Aslam, Nicolas Gorius, and George Nehmetallah. "Parallel Computation of CRC-Code on an FPGA Platform for High Data Throughput." Electronics 10, no. 7 (2021): 866. http://dx.doi.org/10.3390/electronics10070866.

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With the rapid advancement of radiation hard imaging technology, space-based remote sensing instruments are becoming not only more sophisticated but are also generating substantially more amounts of data for rapid processing. For applications that rely on data transmitted from a planetary probe to a relay spacecraft to Earth, alteration or discontinuity in data over a long transmission distance is likely to happen. Cyclic Redundancy Check (CRC) is one of the most well-known package error check techniques in sensor networks for critical applications. However, serial CRC computation could be a b

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Castagnoli, G., S. Brauer, and M. Herrmann. "Optimization of cyclic redundancy-check codes with 24 and 32 parity bits." IEEE Transactions on Communications 41, no. 6 (1993): 883–92. http://dx.doi.org/10.1109/26.231911.

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26

Rekkal, Kahina, Sara Rekkal, and Abdesselam Bassou. "Advanced hybrid algorithms for precise multipath channel estimation in next-generation wireless networks." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 2 (2024): 1654. http://dx.doi.org/10.11591/ijece.v14i2.pp1654-1664.

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Multipath channels continue to present challenges in wireless communication for both 5G and 6G networks. A multipath channel is a phenomenon in wireless communications where signals traverse from the sender to the receiver along various paths. This end occurs due to the reflection, diffraction, and refraction of signals of various objects and structures in the environment. Such pathways can cause symbol interference in the transmitted signal, leading to communication issues. To this end, our paper proposes the integration of three algorithms: teaching-learning-based optimization (TLBO), partic

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Rekkal, Kahina, Sara Rekkal, and Abdesselam Bassou. "Advanced hybrid algorithms for precise multipath channel estimation in next-generation wireless networks." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 2 (2024): 1654–64. https://doi.org/10.11591/ijece.v14i2.pp1654-1664.

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Multipath channels continue to present challenges in wireless communication for both 5G and 6G networks. A multipath channel is a phenomenon in wireless communications where signals traverse from the sender to the receiver along various paths. This end occurs due to the reflection, diffraction, and refraction of signals of various objects and structures in the environment. Such pathways can cause symbol interference in the transmitted signal, leading to communication issues. To this end, our paper proposes the integration of three algorithms: teaching-learning-based optimization (TLBO), partic

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28

Dilli, Ravilla. "CHANNEL CODE RATE MATCHING DESIGN IN CYCLIC REDUNDANCY CHECK-AIDED POLAR CODING FOR 5G NR UPLINK COMMUNICATION." Telecommunications and Radio Engineering 80, no. 4 (2021): 31–47. http://dx.doi.org/10.1615/telecomradeng.2021037038.

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Dilli, Ravilla. "CHANNEL CODE RATE MATCHING DESIGN IN CYCLIC REDUNDANCY CHECK-AIDED POLAR CODING FOR 5G NR UPLINK COMMUNICATION." Telecommunications and Radio Engineering 80, no. 4 (2021): 31–47. http://dx.doi.org/10.1615/telecomradeng.2021037038.

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30

Sais, Manar, Najat Rafalia, and Jaafar Abouchabaka. "DNA technology for big data storage and error detection solutions: Hamming code vs Cyclic Redundancy Check (CRC)." E3S Web of Conferences 412 (2023): 01090. http://dx.doi.org/10.1051/e3sconf/202341201090.

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There is an increasing need for high-capacity, highdensity storage media that can retain data for a long time, due to the exponential development in the capacity of information generated. The durability and high information density of synthetic deoxyribonucleic acid (DNA) make it an attractive and promising medium for data storage. DNA data storage technology is expected to revolutionize data storage in the coming years, replacing various Big Data storage technologies. As a medium that addresses the need for high-latency, immutable information storage, DNA has several potential advantages. One

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Zhang, Xianwen, Ming Jiang, Mingyang Zhu, Kailin Liu, and Chunming Zhao. "CRC-Aided Adaptive BP Decoding of PAC Codes." Entropy 24, no. 8 (2022): 1170. http://dx.doi.org/10.3390/e24081170.

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Although long polar codes with successive cancellation decoding can asymptotically achieve channel capacity, the performance of short blocklength polar codes is far from optimal. Recently, Arıkan proposed employing a convolutional pre-transformation before the polarization network, called polarization-adjusted convolutional (PAC) codes. In this paper, we focus on improving the performance of short PAC codes concatenated with a cyclic redundancy check (CRC) outer code, CRC-PAC codes, since error detection capability is essential in practical applications, such as the polar coding scheme for the

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32

Li, Bin, Hui Shen, and David Tse. "An Adaptive Successive Cancellation List Decoder for Polar Codes with Cyclic Redundancy Check." IEEE Communications Letters 16, no. 12 (2012): 2044–47. http://dx.doi.org/10.1109/lcomm.2012.111612.121898.

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Muhammad, Shamsuddeen Hassan, and Abdulrasheed Mustapha. "A Form of List Viterbi Algorithm for Decoding Convolutional Codes." U.Porto Journal of Engineering 4, no. 2 (2018): 42–48. http://dx.doi.org/10.24840/2183-6493_004.002_0004.

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Viterbi algorithm is a maximum likelihood decoding algorithm. It is used to decode convolutional code in several wireless communication systems, including Wi-Fi. The standard Viterbi algorithm gives just one decoded output, which may be correct or incorrect. Incorrect packets are normally discarded thereby necessitating retransmission and hence resulting in considerable energy loss and delay. Some real-time applications such as Voice over Internet Protocol (VoIP) telephony do not tolerate excessive delay. This makes the conventional Viterbi decoding strategy sub-optimal. In this regard, a modi

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Nitin Uniyal, Pradeep Semwal, Sanjay Sharma,. "A Two-Phase Data Integrity Verification using Cyclic Redundancy Check and SHA-256 Algorithm for Security of Cloud Data." Power System Technology 48, no. 1 (2024): 389–402. https://doi.org/10.52783/pst.287.

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With the rising dependence on distributed computing, assuring the security of information put away in the cloud has become vital. Conventional strategies for information may not be adequate to handle the advancing digital dangers. This proposed paper proposes an enhanced efficient way to deal with upgrade cloud data security through a two-layered message trustworthiness check system that incorporates cyclic Redundancy Check (CRC) and hash capability strategies. By joining these two techniques, the proposed framework plans to give a strong cryptographic module for ensuring message integrity of

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WANG, Yuhuan, Hang YIN, Zhanxin YANG, Yansong LV, Lu SI, and Xinle YU. "An Adaptive Fusion Successive Cancellation List Decoder for Polar Codes with Cyclic Redundancy Check." IEICE Transactions on Communications E103.B, no. 1 (2020): 43–51. http://dx.doi.org/10.1587/transcom.2019ebp3031.

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An, Fanglin, Jun Ye, and Zewen Yang. "Data Transmission Error Detection and Correction with Cyclic Redundancy Check and Polar Code Integration with Successive Cancellation Decoding Algorithm." Applied Sciences 15, no. 3 (2025): 1124. https://doi.org/10.3390/app15031124.

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In the context of Internet of Things and 5G communication, ensuring the accuracy and reliability of data transmission is critical, especially as the future 6G communication system places a greater emphasis on highly reliable transmission. However, the existing error correction schemes for 5G are found to be insufficient in their error correction capability for the 6G environment. To address this issue, this paper proposes an enhanced error correction scheme, which is an improvement over existing methods. This scheme is based on a combination of cyclic redundancy check (CRC) codes and Polar Cod

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Zhang, Yongxing, Wenping Ge, Pengju Zhang, Mengyao Gao, and Gecheng Zhang. "A Joint Detection and Decoding Scheme for PC-SCMA System Based on Pruning Iteration." Symmetry 12, no. 10 (2020): 1624. http://dx.doi.org/10.3390/sym12101624.

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Polar coding and sparse code multiple access (SCMA) are key technologies for 5G mobile communication, the joint design of them has a great significance to improve the overall performance of the transmitter-receiver symmetric wireless communication system. In this paper, we firstly propose a pruning iterative joint detection and decoding algorithm (PI-JDD) based on the confidence stability of resource nodes. Branches to be updated are dynamically pruned to avoid redundant iterative, which is able to reduce 24~50% complexity while achieving the approximate error performance of traditional serial

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F. Aliwee, Hala, and Abdulkareem A. Kadhim. "BER PERFORMANCE OF JOINT POLAR CODED SIGNAL AND MIMO USING MILLIMETER WAVE." Iraqi Journal of Information & Communications Technology 4, no. 1 (2021): 10–18. http://dx.doi.org/10.31987/ijict.4.1.124.

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There have been active researches worldwide for evolving the next-generation networks such as 5G. The 5G network is predicted to ensure considerable mobile data traffic having large number of wireless connections. This is combined with high energy-efficiency and Quality of Service (QoS). For these reasons, 5G should be exploited the prospect of new developments, including multiple-input multiple-output (MIMO) technology and using higher frequencies such as the millimeter-wave (mmWave) frequency band. Error correction techniques are commonly utilized to reduce transmission error and enhance QoS

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Zhang, Yi, Xiangyang Luo, Xiaodong Zhu, Zhenyu Li, and Adrian G. Bors. "Enhancing reliability and efficiency for real-time robust adaptive steganography using cyclic redundancy check codes." Journal of Real-Time Image Processing 17, no. 1 (2019): 115–23. http://dx.doi.org/10.1007/s11554-019-00905-7.

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kumar, B. Pradeep, and K. Tejaswi. "A Novel Method for Cyclic Redundancy Check Using Aided Hybrid Decoding Algorithm for Turbo Codes." International Journal of Engineering Trends and Technology 25, no. 2 (2015): 106–10. http://dx.doi.org/10.14445/22315381/ijett-v25p219.

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Aurangzib, Md Abdur Rahman, Firoz Ahmed Md., and Nurnaby Hasan Md. "Performance Assessment of STBC Encoded MIMO MC-CDMA System over AWGN Channel." International Journal of Innovative Science and Research Technology 7, no. 9 (2022): 1074–78. https://doi.org/10.5281/zenodo.7162474.

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This article presents the performance of a MIMO MC-CDMA system using Alamouti Space Time Block Code (STBC) scheme to transmit voice signals over an AWGN channel with QAM and QPSK digital modulation scheme in terms of bit error rate (BER). According to the results of this study, QPSK modulation outperforms QAM modulation in the MIMO MC-CDMA STBC-based wireless communication system. In comparison to QPSK digital modulation, QAM digital modulation performs the worst in voice signal transmission. The present MATLAB simulation study shows that the STBC encoded 4×4 MIMO MC-CDMA wireless commun

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Murugesan, Vigneshwari. "Leveraging CRC Error Detection for Enhanced Error Correction in Digital Communication Systems." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 04 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem30604.

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In this study, CRC error detection techniques will be used to not only identify but fix single-bit errors in digital communication systems. In the past, CRC codes have been employed mainly for their ability to detect errors efficiently. However, this paper suggests a new way that will make it possible to modify CRC functions and thus correct the identified errors. It is intended that by using an optimized look-up table in Verilog hardware description language with an advanced Xilinx 14.7 toolchain, this research can increase the dependability and effectiveness of error correction mechanisms fo

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Sumukh G, Nazim Khan, Priyadarshini S, Dr. Vrunda Kusanur, and Dr. Keerti Kulkarni. "Multiple Error Detection and Correction in SRAM Emulated TCAMs Using RS Code." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 11, no. 2 (2025): 2968–77. https://doi.org/10.32628/cseit25112762.

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Ternary Content Addressable Memories (TCAMs) are specialized types of memory primarily used in networking hardware, such as switches and routers, to perform high-speed operations. They are mainly utilized in hardware components designed for fast searching and matching operations. For example, TCAMs are used in intrusion detection and prevention systems (IDS/IPS) and network and packet processing in software defined system SDNs. TCAMs are used in application specific integrated circuits which are integrated into intellectual property blocks or as a standalone device. The FPGAs do not include an

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Hyla, Jakub, and Wojciech Sułek. "Energy-Efficient Raptor-like LDPC Coding Scheme Design and Implementation for IoT Communication Systems." Energies 16, no. 12 (2023): 4697. http://dx.doi.org/10.3390/en16124697.

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The large number of inexpensive and energy-efficient terminals in IoT systems is one of the emerging elements of the recent landscape of information and communication technologies. IoT nodes are usually embedded systems with limited processing power devices and strict requirements on energy consumption. In this paper, we consider the design and implementation of a part of the IoT communication uplink stack, namely the error correction coding scheme, for energy-efficient operation. We examine how an efficient rate-adaptive coding scheme, namely the Raptor-like (RL) quasi-cyclic (QC) subclass of

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Li, Shibao, Yunqiang Deng, Xun Gao, He Li, Lin Guo, and Zhenwei Dong. "Generalized Segmented Bit-Flipping Scheme for Successive Cancellation Decoding of Polar Codes With Cyclic Redundancy Check." IEEE Access 7 (2019): 83424–36. http://dx.doi.org/10.1109/access.2019.2922664.

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Saiz-Adalid, Luis-J., Joaquín Gracia-Morán, Daniel Gil-Tomás, J. Carlos Baraza-Calvo, and Pedro-J. Gil-Vicente. "Reducing the Overhead of BCH Codes: New Double Error Correction Codes." Electronics 9, no. 11 (2020): 1897. http://dx.doi.org/10.3390/electronics9111897.

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The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and redu

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Ahmed, Abdulkadhim Hamad, Al-Mumen Haider, and Taih Gatte Mohammed. "FPGA-based experimental board for error control codes." Bulletin of Electrical Engineering and Informatics 11, no. 3 (2022): 1460~1470. https://doi.org/10.11591/eei.v11i3.3778.

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This paper proposed an experimental device that emulates and facilitates teaching the theoretical concepts of error-control coding (ECC) techniques. Two prototypes laboratory boards were designed and implemented. The first board simulates the transmitter side of a typical digital communication system. It mainly contains a data source, (7,4) Hamming encoder, cyclic redundancy check encoder (CRC), and Gaussian noise generator. The second board has two types of Hamming decoders, a syndrome decoder, and a maximum likelihood (ML) decoder that accepts the received soft signals at the channel output.

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Cheng, Yulun, and Longxiang Yang. "A Novel Error Detection due to Joint CRC Aided Denoise-and-Forward Network Coding for Two-Way Relay Channels." Scientific World Journal 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/470324.

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In wireless two-way (TW) relay channels, denoise-and-forward (DNF) network coding (NC) is a promising technique to achieve spectral efficiency. However, unsuccessful detection at relay severely deteriorates the diversity gain, as well as end-to-end pairwise error probability (PEP). To handle this issue, a novel joint cyclic redundancy code (CRC) check method (JCRC) is proposed in this paper by exploiting the property of two NC combined CRC codewords. Firstly, the detection probability bounds of the proposed method are derived to prove its efficiency in evaluating the reliability of NC signals.

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Wang, Yong Liang, Chao Sheng Mai, Zhi Liang Chen, Qi Song, Zi Han Chen, and Xing Li Wu. "Research of Intelligent Control System for Fish-Farming." Applied Mechanics and Materials 303-306 (February 2013): 1200–1203. http://dx.doi.org/10.4028/www.scientific.net/amm.303-306.1200.

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Used Atmega 8 microcontroller as the control center, with the temperature sensor DS18B20, feeding control system, combined with radio frequency technology, intelligent control system for fish-farming was designed. The system has the whole process of intelligent automatic control and testing for feeding, supplemental oxygen, and PID temperature regulation; PC and the host processor connect each other through the RS-485 to greatly improve the transmission distance, using CRC cyclic redundancy check code ensure the accuracy of data. The machine is mainly responsible for collecting the spot parame

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Rullyanto, Rullyanto, and Mohamad Fathoni. "Analisa Unjuk Kerja Sistem Downlink Dedicated Channel (DCH) Pada Wideband CDMA." Jurnal Ilmiah Giga 16, no. 1 (2019): 17. http://dx.doi.org/10.47313/jig.v16i1.586.

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Sistem seluler Wideband Code Division Multiple Acces (WCDMA) saat ini berkembang sangat pesat pada tugas akhir ini dilakukan Analisa Unjuk Kerja Sistim Downlink Dedicated Channel (DCH) pada Wideband CDMA. Untuk menganalisa performa atau unjuk kerja dari sistem Downlink DCH pada Wideband CDMA dicari nilai kesalahan bit pada saat pengiriman yang biasa dikenal dengan nama Bit Error Rate pada Cyclic Redundancy Check (CRC) dan channel coding dengan input Dedicated Traffik Channel (DTCH) dan Dedicated Control Channel (DCCH) dicari nilai Bit Error Rate (BER) pada sistem Downlink Dedicated Channel (DC

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