Relevant bibliographies by topics / D latch

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'D latch'

Author: Grafiati
Published: 4 June 2021
Last updated: 10 February 2022

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Journal articles on the topic "D latch"

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Hatefinasab, Seyedehsomayeh, Noel Rodriguez, Antonio García, and Encarnacion Castillo. "Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit." Electronics 10, no. 11 (May 25, 2021): 1256. http://dx.doi.org/10.3390/electronics10111256.

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.
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Gupta, Kirti, Neeta Pandey, and Maneesha Gupta. "MCML D-Latch Using Triple-Tail Cells: Analysis and Design." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/217674.

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A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.
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Talebipoor, Neda, Peiman Keshavarzian, and Behzad Irannejad. "Low Power and High Speed D-Latch Circuit Designs Based on Carbon Nanotube FET." International Journal of Engineering & Technology 2, no. 1 (November 16, 2012): 12. http://dx.doi.org/10.14419/ijet.v2i1.483.

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In this paper we propose low power and high speed D-latche circuits base on carbon nanotube field effect transistor. D-latches are the important state-holding elements and systems performance enhancement will be achieved by improving the flip-flop latches structure. The circuit designs are simulated by Hspice .In this paper the consumption result of the circuit parameters such as delay, power and PDP for our three different D-latch circuit design in various voltages and different temperatures.
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Liu Po Ching and Ong Geok Ling. "Low-power and low-voltage D-latch." Electronics Letters 34, no. 7 (1998): 641. http://dx.doi.org/10.1049/el:19980447.

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Vanak, Amin, and Reza Sabbaghi-Nadooshan. "Improvement of Power and Performance in NAND and D-Latch Gates Using CNFET Technology." Journal of Nano Research 33 (June 2015): 126–36. http://dx.doi.org/10.4028/www.scientific.net/jnanor.33.126.

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In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice. Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.
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Ong, Geok Ling, and Po-Ching Liu. "Technique for lower power dissipation in D-latch." Electronics Letters 34, no. 18 (1998): 1733. http://dx.doi.org/10.1049/el:19981207.

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Banerjee, Anirban, Vikash Prasad, and Debaprasad Das. "Design and Analysis of Ternary D-Latch Using CNTFETs." Journal of Nano- and Electronic Physics 11, no. 4 (2019): 04011–1. http://dx.doi.org/10.21272/jnep.11(4).04011.

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K.G.Sharma, Abhilasha. "Optimum Design of D-Latch for Low power Applications." IOSR Journal of Engineering 02, no. 04 (April 2012): 604–8. http://dx.doi.org/10.9790/3021-0204604608.

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Pandey, Neeta, Kirti Gupta, and Maneesha Gupta. "An efficient triple-tail cell based PFSCL D latch." Microelectronics Journal 45, no. 8 (August 2014): 1001–7. http://dx.doi.org/10.1016/j.mejo.2014.05.002.

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Singar, Sumitra, and P. K. Ghosh. "Fault-Free D-Latch Configurations for Low Power Applications." Journal of Nanoelectronics and Optoelectronics 13, no. 5 (May 1, 2018): 701–7. http://dx.doi.org/10.1166/jno.2018.2264.

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Dissertations / Theses on the topic "D latch"

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Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.
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Lach, Roland [Verfasser]. "Magnetische Geräuschemission umrichtergespeister Käfigläufer-Asynchronmaschinen / Roland Lach." Dortmund : Universitätsbibliothek Technische Universität Dortmund, 2005. http://d-nb.info/1011533820/34.

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Wagner, Stefanie [Verfasser]. "History of the European larch (Larix decidua Mill.) / Stefanie Wagner." Bonn : Universitäts- und Landesbibliothek Bonn, 2013. http://d-nb.info/1060787334/34.

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Lach, Björn [Verfasser]. "Automatische Reifendruckregelung in der Gesamtsimulation Fahrzeug-Gelände / Björn Lach." Aachen : Shaker, 2006. http://d-nb.info/1170528791/34.

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Sirries, Steffen [Verfasser], and Mario [Akademischer Betreuer] Larch. "Essays on International Trade and Migration / Steffen Sirries. Betreuer: Mario Larch." Bayreuth : Universität Bayreuth, 2016. http://d-nb.info/1113107332/34.

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Löwy, Sarah [Verfasser], and Eric Jan [Akademischer Betreuer] Mittemeijer. "Formation of lath martensite / Sarah Löwy. Betreuer: Eric Jan Mittemeijer." Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2016. http://d-nb.info/1093404299/34.

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Lach, Nadine [Verfasser]. "Therapieadhärenz und Arzneimittelwechselwirkungen bei Patienten mit hypertensiver Krise / Nadine Lach." Göttingen : Niedersächsische Staats- und Universitätsbibliothek Göttingen, 2021. http://d-nb.info/1234847051/34.

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Priester-Lasch, Maximilian [Verfasser], and Gabriele [Akademischer Betreuer] Alex. "Eine Reise nach Indien. Übersetzungen eines Modells / Maximilian Priester-Lasch ; Betreuer: Gabriele Alex." Tübingen : Universitätsbibliothek Tübingen, 2017. http://d-nb.info/1196702179/34.

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Lach, Johannes [Verfasser], and Jutta [Gutachter] Eichler. "Struktur-Aktivitätsbeziehung eines CXCR4-mimetischen Peptides / Johannes Lach ; Gutachter: Jutta Eichler." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2017. http://d-nb.info/1149368683/34.

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Swidsinski, Anja [Verfasser], Alexander [Gutachter] Lasch, Alexander [Akademischer Betreuer] Lasch, Dorothee [Gutachter] Wieser, and Gudrun [Gutachter] Loster-Schneider. "Multiperspektivität und interpretatorische Relevanz : Eine relevanztheoretisch- literaturwissenschaftliche Untersuchung von Peter Wawerzineks „Rabenliebe“ und Wolfgang Herrndorfs „Arbeit und Struktur“ / Anja Swidsinski ; Gutachter: Alexander Lasch, Dorothee Wieser, Gudrun Loster-Schneider ; Betreuer: Alexander Lasch." Dresden : Technische Universität Dresden, 2021. http://d-nb.info/123241042X/34.

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Book chapters on the topic "D latch"

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Juan-Chico, J., M. J. Bellido, A. J. Acosta, M. Valencia, and J. L. Huertas. "Analysis of Metastable Operation in a CMOS Dynamic D-Latch." In Analog Design Issues in Digital VLSI Circuits and Systems, 143–57. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6101-9_12.

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Alioto, M., and G. Palumbo. "Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates." In Lecture Notes in Computer Science, 429–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x_43.

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Sakshi Bhatnagar, Harsh Gupta, and Swapnil Jain. "Modified D-Latch Enabled BEC1 Carry-Select Adder with Low Power-Delay Product and Area Efficiency." In Proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing, 441–49. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2638-3_51.

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Miller-Klejsa, Anna. "Złodzieje rowerów na trasie W-Z uwagi o recepcji dzieła De Siki w polskim piśmiennictwie filmowym do 1956 roku." In Sperimentare ed esprimere l’italianità. Aspetti letterari e culturali. Doświadczanie i wyrażanie włoskości. Aspekty literackie i kulturowe. Wydawnictwo Uniwersytetu Łódzkiego, 2021. http://dx.doi.org/10.18778/8220-478-0.13.

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Po zakończeniu II wojny światowej kultura filmowa w Polsce Ludowej uległa istotnej transformacji. Jednym z jej aspektów był nowy model importu filmów: większość międzynarodowych źródeł została zastąpiona filmami z komunistycznego bloku, głównie z ZSRR. Filmy włoskie stanowiły w tych realiach istotny wyjątek: publiczność polska była zaznajomiona nie tylko z filmami, ale także – dzięki przekładom publikowanym w prasie branżowej – z teoretycznymi tezami nurtu C. Zavattiniego i U. Barbaro (ten ostatni w latach 1948–1949 wykładał nawet w łódzkiej Szkole Filmowej). Niektóre filmy uznawane za neorealistyczne nie zostały jednak dopuszczone na polskie ekrany przez cenzurę (zakazano m.in. wyświetlania kilku filmów Rosselliniego), lub pojawiły się w kinach ze znaczącym opóźnieniem (los taki spotkał m.in. film Umberto D.). W artykule koncentruję się na zbadaniu recepcji filmu Złodzieje rowerów (Ladri di biciclette, reż. V. De Sica, 1948) w polskim czasopiśmiennictwie filmowym lat 1946–1956. Analiza wykazała, że o ile w latach 1946–1949 przeważają raczej pozytywne głosy, o tyle od początku lat 50., w okresie stalinizacji, dominują głosy krytyczne; odkąd ideałem stało się kino radzieckie i poetyka socrealizmu, włoski neorealizm (i film De Siki) oskarżany był o pesymizm oraz gubienie „wielkich perspektyw rewolucyjnych”. To podejście uległo zmianie w czasie odwilży, kiedy neorealizm stał się swoistym wzorem do naśladowania – przykładem nowatorskiej estetyki filmowej.
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Conference papers on the topic "D latch"

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Danielak, W., W. Machado, M. Jaffer, S. Waldstein, A. Jordan, M. Sachdev, and D. Li. "Latch-Up Root Cause Analysis for New ASIC Design." In ISTFA 2007. ASM International, 2007. http://dx.doi.org/10.31399/asm.cp.istfa2007p0337.

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Abstract The analyzed new Application Specific Integrated Circuit (ASIC) design failed latch-up test on two input pins during current stress. In order to determine the root cause, the Failure Analysis (FA) with use of backside Emission Microscopy (EMMI) was performed. The EMMI results were followed by detailed layout and circuit analysis. It was found that the root cause of the latch-up is an abutment of two specific cells (called “cell C” and “cell D”), where the N-well was grounded creating a parasitic NPN transistor sustaining the latch-up. A detailed calculation of parasitic interconnection resistances from the layout revealed some differences between latching and non-latching pins. The analytical model to explain the latch-up behavior based on parasitic resistances was applied successfully to root cause analysis. Summarizing, the latch–up behavior can be explained by the abutment of cells C and D, parasitic interconnect resistances and cell location with respect to the substrate bumps. In conclusions the following recommendations were made: 1. Remove the n-well in cell D; 2. Connect specific cells (B and D) to higher supply voltage; 3. Implement p+ guard rings for cells C and D; 4. Optimize placement of ground bumps; 5. Eliminate abutment of cell C and D.
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Marthi, Poorna, Nazir Hossain, Jean-Francois Millithaler, and Martin Margala. "A new level sensitive D Latch using Ballistic nanodevices." In 2016 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2016. http://dx.doi.org/10.1109/iscas.2016.7538939.

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Ho, Patrick W. C., Haider Abbas F. Almurib, and T. Nandha Kumar. "Non-volatile D-latch for sequential logic circuits using memristors." In TENCON 2015 - 2015 IEEE Region 10 Conference. IEEE, 2015. http://dx.doi.org/10.1109/tencon.2015.7372849.

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Radhika, Neeta Pandey, Kirti Gupta, and Maneesha Gupta. "Low power D-latch design using MCML tri-state buffers." In 2014 International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2014. http://dx.doi.org/10.1109/spin.2014.6777011.

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Kulkarni, Anant, Brajesh Kumar Kaushik, and Zeljko Zilic. "Implementation and Analysis of Spin-Torque-Based Reversible D-Latch." In 2018 IEEE 31st Canadian Conference on Electrical & Computer Engineering (CCECE). IEEE, 2018. http://dx.doi.org/10.1109/ccece.2018.8447583.

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Kumar, Robin, and Arvind Kumar. "Design and simulation of D-latch and multiplexer using vMOS." In 2010 27th International Conference on Microelectronics Proceedings. IEEE, 2010. http://dx.doi.org/10.1109/miel.2010.5490469.

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Singar, Sumitra, and P. K. Ghosh. "Unique robust fault resistant D-latch for low power applications." In 2017 International Conference on Computer, Communications and Electronics (Comptelix). IEEE, 2017. http://dx.doi.org/10.1109/comptelix.2017.8003930.

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Vallabhuni, Rajeev Ratna, G. Yamini, T. Vinitha, and S. Sanath Reddy. "Performance analysis: D-Latch modules designed using 18nm FinFET Technology." In 2020 International Conference on Smart Electronics and Communication (ICOSEC). IEEE, 2020. http://dx.doi.org/10.1109/icosec49089.2020.9215341.

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Alfredsson, Jon, and Snorre Aunet. "D-latch for subthreshold floating-gate circuits exploiting threshold elements." In 2007 Norchip Conference. IEEE, 2007. http://dx.doi.org/10.1109/norchp.2007.4481059.

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Singh, Akanksha, Ayushi Marwah, and Shyam Akashe. "Novel Gating Technique in D-Latch for Low Power Application." In the Second International Conference. New York, New York, USA: ACM Press, 2016. http://dx.doi.org/10.1145/2905055.2905303.

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Journal articles Dissertations / Theses
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