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Academic literature on the topic 'D to Q Delay and Average power Consumption'
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Journal articles on the topic "D to Q Delay and Average power Consumption"
1
Shaik, Haneef, and Arunmetha S. "Design of Low Power C-Element Based Dual Data Rate Flip-Flip." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 5 (2020): 672–75. https://doi.org/10.35940/ijeat.E9245.069520.
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Fulfillment of dual edge flip-flops gets freshly develops into the goal of countless exploration to sustain expressive accomplishment of digital schemes while compressing power expenditure. Powerful low-power flip-flops acquire absolute basic district elements Gross sudden width of histrionic organizes successive circumferences / circuits. Conclude individually and remarkable testing as long as their vulnerability, Q-Delay, Rise Time Path, Fall Time Path and Average Power Consumption. While Power reveals smart effective count regarding the latest electrifying circuit transistors, uncertainly we survive balancing, including scheming comic numbers such as transistors that suspense each number of flip-flops. Analysis / inquiry on static / stable circuits is performed by Dual Data Rate (DDR) using PTM CMOS-16 nm technology alongside 5MHZ frequencies, including their victory procedure. Sensational Dual Data Rate (DDR) Flip-Flop uses 30% less capacity / power, including 14% lower C-Q delay. This paper's proposed architecture is to analyze logic size, area, and power consumption using tanner tool.
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Mathiazhagan, V., N. P. Ananthamoorthy, and C. Venkatesh. "Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (2022): 1261–73. http://dx.doi.org/10.1166/jno.2022.3291.
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Power consumption in integrated circuits is one of the prominent aspects of the design methodologies that affect cost and efficiency. It holds a prominent role in the design and fabrication of Integrated Circuits (ICs). Power consumption in ICs increases largely due to clock diffusion techniques and Flip-Flops (FFs) since they consume a huge amount of power to carry out internal transitions. Various researchers have proposed different flip-flop circuit designs for reducing power consumption in clocking systems. When integrated circuits are operating at high frequency, the clock functions are usually managed using clocked transistors. The increased number of clocked transistors increases power consumption which is a major challenge. This research aims to minimize the power consumption in flip-flops by lowering the number of clock transistors. This paper presents the design of an enhanced Dual Edge Triggered Flip-Flop (2EdTFF) based on ultra-low-power robust pass-transistor logic (PTL) for power consumption reduction. The proposed PTL-based 2EdTFF is implemented and simulated. The results of the simulation analysis show that the transistor count and layout area are reduced for minimizing power consumption. The average power utilization of the proposed approach is 3.69 μW for a power activity of 50%, 25%, and 12.5%. The power utilization of the proposed approach is reduced by 12.6% compared to TGFF, 5.5%, and 6.6% compared to S-TCRFF and TCRFF. Comparative analysis shows that the proposed approach achieves better power reduction with better D-to-Q delay and Power-Delay-Product (PDP) performance.
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Zhao, Xianghong, Jieyu Zhao, and WeiMing Cai. "A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (2020): 136–41. http://dx.doi.org/10.1166/jno.2020.2702.
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Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.
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John, Kuruvilla, Vinod Kumar R S, and Kumar S S. "Design of low power and high speed implicit pulse flip-flop and its application." International Journal of Engineering & Technology 7, no. 3 (2018): 1893. http://dx.doi.org/10.14419/ijet.v7i3.12845.
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In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.
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Emir, Recep, Dilek Surekci Yamacli, Serhan Yamacli, and Sezai Alper Tekin. "Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology." Electronics 13, no. 15 (2024): 2993. http://dx.doi.org/10.3390/electronics13152993.
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The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R2) values in the range of 0.86 and 0.99.
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Zhou, Yong-Qiang, Lei Dai, and Suo-Ping Li. "Performance Analysis of Multiple Relays Cooperative Truncated Automatic Repeat Request in Wireless Sensor Networks." Sensor Letters 17, no. 9 (2019): 733–38. http://dx.doi.org/10.1166/sl.2019.4138.
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In this paper, we research the performance of direct and non-direct multiple relays cooperative truncated automatic repeat request (D/ND-MRCT-ARQ) protocols in wireless sensor networks (WSNs). We propose a method that named discrete time Markov chain (DTMC) with N + 2 states, which could obtain the throughput formulas of D/ND-MRCT-ARQ protocols. Furthermore, we solve the mathematical expressions of the average transmission delay of both protocols by truncating the number of packet retransmission. In addition, we derive energy efficiency formulas of both protocols under considering the different power consumption of each node. Simulation results demonstrate that the proposed D-MRCT-ARQ protocol achieve higher throughput and energy efficiency while fewer average packet transmission delay, as compared with the ND-MRCT-ARQ protocol.
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Li, Xuezhu. "5G Converged Network Resource Allocation Strategy Based on Reinforcement Learning in Edge Cloud Computing Environment." Computational Intelligence and Neuroscience 2022 (May 14, 2022): 1–8. http://dx.doi.org/10.1155/2022/6174708.
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Aiming at the problem that computing power and resources of Mobile Edge Computing (MEC) servers are difficult to process long-period intensive task data, this study proposes a 5G converged network resource allocation strategy based on reinforcement learning in edge cloud computing environment. n order to solve the problem of insufficient local computing power, the proposed strategy offloads some tasks to the edge of network. Firstly, we build a multi-MEC server and multi-user mobile edge system, and design optimization objectives to minimize the average response time of system tasks and total energy consumption. Then, task offloading and resource allocation process is modeled as Markov decision process. Furthermore, the deep Q-network is used to find the optimal resource allocation scheme. Finally, the proposed strategy is analyzed experimentally based on TensorFlow learning framework. Experimental results show that when the number of users is 110, final energy consumption is about 2500 J, which effectively reduces task delay and improves the utilization of resources.
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Lin, Jin-Fa, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, and Shao-Wei Yu. "Novel Low-Complexity and Low-Power Flip-Flop Design." Electronics 9, no. 5 (2020): 783. http://dx.doi.org/10.3390/electronics9050783.
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In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.
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Faraji, S. Rasoul, Pierre Abillama, and Kia Bazargan. "Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (2022): 1–25. http://dx.doi.org/10.1145/3494570.
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Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.
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Ram, Mahendra, Sushil Kumar, Vinod Kumar, Ajay Sikandar, and Rupak Kharel. "Enabling Green Wireless Sensor Networks: Energy Efficient T-MAC Using Markov Chain Based Optimization." Electronics 8, no. 5 (2019): 534. http://dx.doi.org/10.3390/electronics8050534.
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Due to the rapidly growing sensor-enabled connected world around us, with the continuously decreasing size of sensors from smaller to tiny, energy efficiency in wireless sensor networks has drawn ample consideration in both academia as well as in industries’ R&D. The literature of energy efficiency in wireless sensor networks (WSNs) is focused on the three layers of wireless communication, namely the physical, Medium Access Control (MAC) and network layers. Physical layer-centric energy efficiency techniques have limited capabilities due to hardware designs and size considerations. Network layer-centric energy efficiency approaches have been constrained, in view of network dynamics and available network infrastructures. However, energy efficiency at the MAC layer requires a traffic cooperative transmission control. In this context, this paper presents a one-dimensional discrete-time Markov chain analytical model of the Timeout Medium Access Control (T-MAC) protocol. Specifically, an analytical model is derived for T-MAC focusing on an analysis of service delay, throughput, energy consumption and power efficiency under unsaturated traffic conditions. The service delay model calculates the average service delay using the adaptive sleep wakeup schedules. The component models include a queuing theory-based throughput analysis model, a cycle probability-based analytical model for computing the probabilities of a successful transmission, collision, and the idle state of a sensor, as well as an energy consumption model for the sensor’s life cycle. A fair performance assessment of the proposed T-MAC analytical model attests to the energy efficiency of the model when compared to that of state-of-the-art techniques, in terms of better power saving, a higher throughput and a lower energy consumption under various traffic loads.