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Journal articles on the topic 'DAC circuit'

Author: Grafiati

Published: 5 June 2025

Last updated: 1 August 2025

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1

Matthew Khoo Kah Wen, Nabihah Ahmad, Yuzman Yusoff, and Hasmayadi Abdul Majid. "A Hybrid CMOS Digital-to-Analogue Converters Design for High Resolution SAR ADC." Journal of Advanced Research in Applied Sciences and Engineering Technology 32, no. 3 (2023): 121–38. http://dx.doi.org/10.37934/araset.32.3.121138.

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The paper describes the design and implementation of a 14-bit differential Digital-to-Analogue Converter (DAC) based on the Silterra 0.18µm Complementary Metal-Oxide-Semiconductor (CMOS) process to be established in a Successive Approximation Register (SAR) Analogue-to-Digital Converter (ADC) for the purpose of high-resolution, high accuracy and low power applications. The proposed differential DAC aims to eliminate the issue of stringent matching requirements imposed on high-resolution DACs while leveraging both linearity performance and power consumption parameters at a balanced point. The o

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2

Journal, IJSREM. "Design and Analysis of Op-Amp based 3-Bit R – 2R,4-Bit R–2R & 8-Bit R–2R ladder Digital to Analog Converter using NI-Multisim 14.3." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 02 (2024): 1–13. http://dx.doi.org/10.55041/ijsrem28594.

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Using repetitive arrangements of precision resistor networks in a ladder-like shape, an R-2R Ladder is a quick and low-cost approach to do digital-to-analog conversion. Different resistor levels, an operational amplifier (LM741), and single pole double throw switches were the major building blocks for both circuits. MULTISIM software was used to build both circuits so that the circuit could be tested for its ideal use. The inclusion of both circuits in a real circuit helps with identifying and contrasting each's strengths and drawbacks. Using repetitive arrangements of precision resistor netwo

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3

Shen, Xiao Feng, Rong Bin Hu, and Xi Chen. "A Novel R-2R Current-Mode DAC Used for Digital-Calibrated ADC." Advanced Materials Research 753-755 (August 2013): 2479–82. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2479.

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In this paper, a kind of novel DAC architecture is proposed. Compared to the traditional DAC architecture, the proposed is a multistage one. In order to improve precision, we use a kind of feedback bias circuit, which can minimize the effect of the base currents. A 16-bit DAC transistor-level circuit is implemented in 0.18um SiGe process. The simulation results show that the DAC using the proposed architecture has higher resolution, and better static and dynamic performances than the traditional one.

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Lakshmi Bhavani, G., Patan Muzafar, T. Usha Rani та ін. "A 1.2v ΔΣ ADC Modulator Using 4-bit SAR Quantizer for Biomedical Applications by using 65nm CMOS Technology". MATEC Web of Conferences 392 (2024): 01060. http://dx.doi.org/10.1051/matecconf/202439201060.

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This research focuses on enhancing Sigma-Delta ADC modulators for biomedical applications by leveraging the working principle of Successive Approximation ADC circuits. The proposed modulator includes a comparator, DAC, successive approximation register, and control circuit. The operational process begins with the sample and holds circuit-initiating conversions by sampling the input signal, and then compared with the DAC output. Using a 4-bit example, the successive approximation register refines the DAC output through iterative bit adjustments until the closest digital code approximation to th

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Wu, Zhang Yu, Xian Wang, Ye Hui Wu, and Long Cheng Que. "An N-Bit DAC with Adjustable Precision and Range." Advanced Materials Research 846-847 (November 2013): 822–25. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.822.

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Now some special circuits need higher precision in relatively fixed range. While the precision of a common digital-to-analog converter (DAC) is equidistant, which means the higher the precision is, the greater the number of bits. The increase of number of bits will slow down the speed of converter. This architecture we present here aims at finding a way of solving the problem. It uses M bits of the N-bit DAC to adjust precision by changing the current of the voltage division circuit, which alters the range of the DAC to a certain extent.

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Tian, Y., P. Yang, Q. Wang, et al. "Development of an on-chip configurable DAC module for monolithic active pixel sensor." Journal of Instrumentation 17, no. 03 (2022): C03006. http://dx.doi.org/10.1088/1748-0221/17/03/c03006.

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Abstract This paper describes an on-chip configurable Digital to Analog Converter (DAC) module for monolithic active pixel sensor. The DAC module consists of four 10-bit voltage DACs, seven 8-bit current DACs, a bandgap circuit, and a configure interface. The voltage DAC is implemented with an R-2R resistor ladder network, and each LSB corresponds to 3 mV. The current DAC is in the current-steering type with a thermometer code. Each LSB of the current DAC corresponds to 10 nA. The bandgap circuit provides a stable, temperature-independent reference voltage of 1.25 V to the DACs. All the DACs c

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Рембеза, S. Rembeza, Кононов, and V. Kononov. "Sectional digital-to-analog converter for designing CMOS pipelined-CGT-ADC while minimizing switched capacitors." Modeling of systems and processes 6, no. 3 (2014): 32–34. http://dx.doi.org/10.12737/2387.

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The formulated optimal requirements sectional bezkontaktni DAC. Considered are the main technological and frequency limitations sovovych DAC with low power consumption. Suggested 4-bit binary-weighted Zogby differential DAC architecture analogue circuit.

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Hashemifar, Seyed Mohammad. "Design of a Single-Core Digital-to-Analog Converter with Ultra-Wideband and Low Power Consumption for CUWB-IR Applications." Tehnički glasnik 16, no. 3 (2022): 311–14. http://dx.doi.org/10.31803/tg-20220405104325.

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Data converters are intermediate circuits used to connect between two analog and digital ranges. Data converters are not only used for converting audio into a microphone or speaker, but also for converting audio into a camera or display, transferring information to a computer or digital signal processor. At these times, the need for data converters is not invested in every aspect of life. Digital to analog converters is a leading part of these converters, which are widely used in most audio and video circuits. In this thesis, we have proposed a 4-bit 1GS/s DAC for CUWB-IR usage. To enhance the

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9

Widodo, Arif. "Optimasi Linieritas Rangkaian R-2R Ladder DAC Menggunakan Algoritma Genetika." INAJEEE : Indonesian Journal of Electrical and Eletronics Engineering 1, no. 1 (2018): 7. http://dx.doi.org/10.26740/inajeee.v1n1.p7-11.

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Abstrak - rangkaian R-2R ladder digital-to-analog converter (DAC) adalah rangkaian elektronika sederhanayang dapat dibuat dengan dua nilai resistor serta banyak digunakan untuk proses konversi nilai digital keanalog secara langsung. Pemilihan nilai serta penempatan resistor pada rangkaian ini sangat berpengaruhpada linieritas sinyal hasil konversi. Penelitian ini bertujuan untuk memberikan solusi dalam merancangrangkaian R-2R ladder DAC dengan linieritas yang medekati optimal menggunakan komponen resistor yangada di pasaran. Dengan bantuan algoritma genetika, komponen resistor yang ada dapat d

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10

Li, Weng Yuan, and Teng Xiao Jiang. "A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit." Applied Mechanics and Materials 513-517 (February 2014): 4555–58. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4555.

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In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal freq

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11

Li, Shun. "Design and Implementation of DDS Signal Generator Based on FPGA." Academic Journal of Science and Technology 9, no. 1 (2024): 145–49. http://dx.doi.org/10.54097/xdhh4c13.

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With the rapid development of semiconductor technology, the digital circuit of the control chip gradually replaces the analog circuit of the traditional signal generator, which improves the performance of the signal generator and reduces the cost of research, development and production. This paper proposes a design scheme that takes FPGA chip as the control center. The signal generator system mainly includes DAC module, FPGA module and key module. The system uses Verilog language to develop the sine wave digital signal generation and key switching frequency control logic circuit on FPGA. The f

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12

Qiu, Jinpeng, Tong Liu, Xubin Chen, et al. "A New Digital to Analog Converter Based on Low-Offset Bandgap Reference." Journal of Electrical and Computer Engineering 2017 (2017): 1–10. http://dx.doi.org/10.1155/2017/1658695.

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This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an

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Kim, C. K., S. H. Lee, and L. T. Wu. "Circuit emulations." International Journal of Digital & Analog Cabled Systems 1, no. 4 (1988): 245–56. http://dx.doi.org/10.1002/dac.4520010411.

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14

Sun, Jian, Chen Li, Yuexin Cao, Liangde Lai, and Weichen Song. "A 4T1C Pixel Circuit with Threshold Voltage Compensation for Organic Light-Emitting Diode on Silicon Microdisplays." Electronics 14, no. 5 (2025): 824. https://doi.org/10.3390/electronics14050824.

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In this paper, a pixel circuit consists of four MOSFETs and one capacitor is proposed for Organic Light-Emitting Diode on Silicon (OLEDoS) microdisplays. The proposed pixel circuit enhances luminance uniformity by compensating for the threshold voltage variation of the driving transistors by the capacitive coupling effect. Even with a threshold voltage variation of ±20 mV, the HSPICE simulation results reveal that the driving current offset stays between −0.89 and 0.70 LSB, which is more than seven times smaller than that of the conventional 2T1C pixel circuit. Additionally, a two-stage DAC dr

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15

Dedesin, Emre, Mesud Kahriman, and Ozlem Coskun. "Microcontroller Controlled Inverter Application." WSEAS TRANSACTIONS ON COMPUTERS 21 (March 26, 2022): 103–9. http://dx.doi.org/10.37394/23205.2022.21.15.

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The limited use of fossil fuels has increased the interest in renewable energy sources. Renewable energy sources are generally direct current (DC) production. The popularity of inverters converting from DC to AC is increasing due to the generation of the generated DC signal and the current grid being alternating current (AC). In this study, a computer-controlled inverter was designed with the 16F877 microcontroller chosen as the model, and frequency and amplitude controls were realized with the serial communication system of this structure. A digital-analog converter (DAC) circuit is formed by

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16

Bao, Yuxuan. "Research Progress of Bandgap Reference Circuit." Highlights in Science, Engineering and Technology 103 (June 26, 2024): 42–47. http://dx.doi.org/10.54097/9s275912.

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As an important part of integrated circuit design, bandgap reference circuit is widely used in various chips, among which ADC (analog-to-digital converter) and DAC(digital-to-analog converter) are typical examples. This paper introduces the bandgap reference circuit and its working principle in detail, and then systematically combs and introduces a variety of bandgap reference circuits. A conventional bandgap reference circuit consists of an op-amp, two bipolar transistors and multiple resistors; The CMOS bandgap reference circuit uses the common-source common-gate current mirror to provide th

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17

Widiatmoko, Eko, Muhammad Miftahul Munir, and Khairurrijal. "Development of Digital Variable Frequency Triangle Signal Generator Using Cygnal C8051F005 SoC." Applied Mechanics and Materials 771 (July 2015): 46–49. http://dx.doi.org/10.4028/www.scientific.net/amm.771.46.

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A circuit for generating triangle waveform with variable, digitally controlled frequency has been developed. The circuit utilizes a Cygnal C8051F005 System-on-a-Chip (SoC) for controlling the output frequency. Two 12-bit Digital to Analog Converters (DACs) included in the SoC feeds a voltage to a frequency converter to generate symmetrical bipolar triangle signal using four op-amps, which is an improved version of commonly found voltage controlled oscillator circuit. With one DAC, the frequency can be swept from 7 Hz to 3000 Hz while the amplitude remains constant. The second DAC is used to fi

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18

Wang, Youren, Zhiqiang Zhang, and Jiang Cui. "The Architecture and Circuital Implementation Scheme of a New Cell Neural Network for Analog Signal Processing." JUCS - Journal of Universal Computer Science 13, no. (9) (2007): 1344–53. https://doi.org/10.3217/jucs-013-09-1344.

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It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network SCCNN for analog signal processing circuits, designed the neural cell circuit, and developed the evolutionary design method of the SCCNN based on selfadapting genetic algorithm. In the architecture of new cellular neural network SCCNN, each neural cell connects with four neighborhood neural cells, the neural cell circuit and signal transfer line between neural cells are controlled by programmable switches. The validity

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Liu, Cai Hong, Jin Shui Ji, and Ai Qin Qi. "Design of Control Module for Serial DAC Based on FPGA." Advanced Materials Research 765-767 (September 2013): 2456–59. http://dx.doi.org/10.4028/www.scientific.net/amr.765-767.2456.

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In order to increase the flexibility of control for serial DAC, a new control method for DAC based on FPGA is proposed in this paper. A state transition diagram can be drawn according to the timing diagram of DAC, Which can be realized in FPGA using Very High-speed Integrated Circuit Hardware Description Language. The simulate results show that logic in FPGA is consistent with the requirements. The module based on FPGA can be modified just by modifying software, not the hardware.

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Ishiguchi, Yoritaka, Daishi Isogai, Takuma Osawa, and Shigetoshi Nakatake. "Analog perceptron circuit with DAC-based multiplier." Integration 63 (September 2018): 240–47. http://dx.doi.org/10.1016/j.vlsi.2018.05.010.

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21

Karmakar, Supriya, John A. Chandy, and Faquir C. Jain. "Implementation of Membership Function using Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 23, no. 01n02 (2014): 1450007. http://dx.doi.org/10.1142/s0129156414500074.

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Spatial wave-function switched field effect transistor (SWSFET) switches the current flow between different channels inside the FET based on the applied voltage in its gate terminal. SWSFET can be used to implement multi-valued logic circuit with less number of circuit elements. Recently we presented unipolar inverter circuit using SWSFET. In this paper we develop a circuit model of SWSFET based on BSIM 3.2.0 and BSIM 3.2.4 and implement membership function using that circuit model of SWSFET. The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quan

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22

Wang, Weihe, and Hongqi Yu. "Pipelined Memristive neural network analog-to-digital converter." Journal of Physics: Conference Series 2632, no. 1 (2023): 012004. http://dx.doi.org/10.1088/1742-6596/2632/1/012004.

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Abstract This paper designs a pipelined memristive neural network ADCs. Cascade the sub stages of memristive neural network ADC with pipeline structure to improve the conversion accuracy of memristive neural network ADC. First, the signal flow of the pipeline architecture is optimized, and the compatibility between the 4 bit memristive neural network ADC and the pipeline architecture is solved. Secondly, the application of random disturbance circuits in pipeline architecture was analyzed. Combining the calibration circuit with the pipeline DAC to reduce the power consumption of the calibration

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Md., Mashrur Islam, Mushfiq ur Rahman Md., and Hosen Rubayet. "A Successive Method of Flashing for ADC Networks." Asian Journal of Contemporary Science and Technology 1, no. 1 (2019): 17–20. https://doi.org/10.5281/zenodo.3241796.

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In spite of being fastest Flash ADC isn’t much popular due to its huge siege and large power consumption. To overcome these problems half flash ADC is introduced in which A/D conversion is done in two steps. Say for an 8-bit system, first the higher 4 bits and then lower 4 bits. So total comparators required is 32. Besides two separate encoder circuit consisting of logic gates and diodes, a 4-bit DAC, a differential amplifier, track and hold circuit etc. is required. So, this system isn’t small enough for implementing inside any microcontroller or small digital devices. This paper

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more

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Nahar, Ali Kerem, Ansam Subhi Jaddar, Hussain K. Khleaf, and Mohmmed Jawad Mortada Mobarek. "Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance." International Journal of Advances in Applied Sciences 10, no. 1 (2021): 79. http://dx.doi.org/10.11591/ijaas.v10.i1.pp79-87.

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<p>In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response

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Ali, Kerem Nahar, Subhi Jaddar Ansam, K. Khleaf Hussain, and Jawad Mortada Mobarek Mohmmed. "Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance." International Journal of Advances in Applied Sciences (IJAAS) 10, no. 1 (2021): 79–87. https://doi.org/10.11591/ijaas.v10.i1.pp79-87.

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In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounti

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27

Myderrizi, Indrit, та Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology". Journal of Circuits, Systems and Computers 26, № 11 (2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.

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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with

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28

Lee, Jae-Hun, Dasom Park, Woojin Cho, Huu Phan, Cong Nguyen та Jong-Wook Lee. "A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques". Sensors 18, № 10 (2018): 3486. http://dx.doi.org/10.3390/s18103486.

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Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is effici

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Wang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (2022): 1704. http://dx.doi.org/10.3390/app12031704.

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In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips an

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Hu, Yunfeng, Bin Tang, Lexing Hu, et al. "A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications." Micromachines 13, no. 12 (2022): 2110. http://dx.doi.org/10.3390/mi13122110.

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This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CVref2, achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of Vcm and complexity of DAC control logic and DAC driver circuit. Mo

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Prasanna, P. Durga. "Implementation of 8-Bit Asynchronous SAR ADC." International Journal for Research in Applied Science and Engineering Technology 13, no. 2 (2025): 979–83. https://doi.org/10.22214/ijraset.2025.67010.

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This study analyses the design of SAR ADC that is suitable for implementing in low power applications. The designed SAR ADC minimizes the complexities associated with its design using higher frequencies by avoiding the usage of oversampled clock. A Bootstrap circuit is designed for a sampling and holding which improves increased linearity. Another aspect of the low power is designing a comparator such that it does not require a pre-amplifier. Successive Approximation register (SAR) ADC is implemented using a charge redistribution DAC. The SAR logic block generates the digital code thus reducin

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Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementa

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Bhupatprasad, Chourasia Ashish, and Kelkar Deepali Shrikant. "A circuit design of a cyclic voltage generator." Chemistry & Chemical Technology 2, no. 3 (2008): 235–38. http://dx.doi.org/10.23939/chcht02.03.235.

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The present paper describes a simple circuit for construction of a cyclic voltage generator, which can be used in electrochemical synthesis of conducting polymer films like polyaniline(PANI), polythiophene, polypyrrol etc. The circuit consists of a clock generator; its frequency is converted into digital voltage which is further converted to analog form using digital to analog converter (DAC). This analog voltage, after boosting, is used as a source of voltage in the synthesis of conducting polymer. Since the oxidation potential for a polymer is unknown, the circuit developed has a facility to

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Reed, Lynn, John Hoenig, and Vema Reddy. "The Design and Characterization of an 8-bit ADC for 250°C Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (2015): 000027–32. http://dx.doi.org/10.4071/hiten-session1-paper1_5.

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Many high temperature applications require the measurement of analog voltages. This usually requires the integration of an ADC into the design. While the temperature degradation in performance of digital circuits is well known, the effects of temperature on analog circuitry are much harder to predict. Analog design is often an iterative process in which the characterization knowledge of a fabricated design is used to improve the next iteration of the design. This paper presents the results of the most recent iteration. This paper describes how the design of an existing 8-bit ADC was optimized

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35

Razavi, Behzad. "The Current-Steering DAC [A Circuit for All Seasons]." IEEE Solid-State Circuits Magazine 10, no. 1 (2018): 11–15. http://dx.doi.org/10.1109/mssc.2017.2771102.

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36

Ye, Yidie, and Yinshui Xia. "A current-mode DAC unit circuit with smooth transition." Journal of Semiconductors 36, no. 7 (2015): 075006. http://dx.doi.org/10.1088/1674-4926/36/7/075006.

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37

Zhou, Dengrong. "Design and Implementation of DAC Circuit in Waveform Generator." Journal of Physics: Conference Series 1601 (July 2020): 022006. http://dx.doi.org/10.1088/1742-6596/1601/2/022006.

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Lin, Shengmin, Cheng Lin, and Qunchao Chen. "A Low-power Level-Crossing ADC for Biosignal Acquisition." Journal of Physics: Conference Series 2524, no. 1 (2023): 012022. http://dx.doi.org/10.1088/1742-6596/2524/1/012022.

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Abstract A large number of redundant signals will be generated when the traditional Nyquist sampling method is used to acquire a biological signal, leading to a system’s energy loss. A new level-crossing analog-to-digital converter (LC-ADC) with non-uniform sampling and fixed window structure is presented, with fewer data and low power consumption features. The circuit uses a 6-bit capacitive DAC to quantize the input signal, avoiding the error accumulation of the 1-bit capacitive DAC structure, and a nanoamp CMOS current bias circuit to provide a very low quiescent current for the comparator,

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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.

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<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with le

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Agayev, Ferid, Javid Karimov, Almaz Mehdiyeva, and Sevinj Quliyeva. "Design principles of digital-to-analog conversion in information transformation." Technology audit and production reserves 5, no. 1(67) (2022): 18–21. http://dx.doi.org/10.15587/2706-5448.2022.267770.

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The object of study is digital-to-analog converter (DAC). The meaning of DAC, their design and control of various types of switches, as well as some logic elements that can act as a switch, as well as the principles of DAC operation based on various series, microcircuits were considered. The resistance of a 4-bit DAC circuit was calculated and, accordingly, the change in the output voltage when applying the corresponding combined input voltage was studied, and a timing diagram was accordingly developed. Using 1-state and toggle physical switches, schematics are established and side effects are

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Tafir Mustaffa, Mohd, Yong Cheng Lim, and Choon Yan Teh. "Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN)." Indonesian Journal of Electrical Engineering and Computer Science 5, no. 3 (2017): 643. http://dx.doi.org/10.11591/ijeecs.v5.i3.pp643-649.

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DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique

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Yuan, Meng, Mingchao Jian, Jiwei Zheng, and Chunbing Guo. "Behavioral Modeling and Circuit Design of High Precision Low Power Dynamic Zoom ADC." Journal of Physics: Conference Series 2477, no. 1 (2023): 012074. http://dx.doi.org/10.1088/1742-6596/2477/1/012074.

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Abstract In this paper, a high-precision, energy-saving dynamic zoom ADC consisting of a 6-bit SAR ADC and a second-level Σ − ∆ modulator (SDM) is proposed. Non-ideal factors, including slew rate (SR), limited bandwidth and DC gain of the op-amp, and kT/C noise, mismatch of DAC capacitors, are analyzed with a behavioral model in Simulink to guide actual circuit design more accurately. The ADC parameters are adjusted and optimized by model simulation. Because the DAC capacitors mismatch produces harmonic distortion, the DWA technique is used. A new digital combined circuit is proposed to minimi

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Li, Yan-Ming, Xiao-Li Xi, Hao Zhang, et al. "A Digital–Controlled Soft-Start Circuit for Negative Output DC–DC Converter." Journal of Circuits, Systems and Computers 28, no. 04 (2019): 1950067. http://dx.doi.org/10.1142/s0218126619500671.

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To suppress the inrush current and overshoot voltage generated at the start-up stage of Buck–Boost converter, a digital–controlled soft-start circuit based on digital-to-analog converter (DAC) control technology is proposed in this paper. The power consumption of the circuit is zero and the circuit is also keeps the characteristics of simple structure and high reliability. The circuit has been integrated into a Buck–Boost converter with negative voltage output by using the 0.18[Formula: see text][Formula: see text]m CDMOS high voltage process. The experimental results show that this circuit ca

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Zhang, Chao Zhu, Yue Zhu, and Ji Nan Han. "The Dual Sine Signal Generator Design Based on the Principle of Difference Frequency Filtering." Advanced Materials Research 981 (July 2014): 74–77. http://dx.doi.org/10.4028/www.scientific.net/amr.981.74.

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The paper attempts to realize the processing scheme of low cost dual sine wave generator. It used single-chip microcomputer and CPLD(Complex Programable Logic Device) as the control core. It maked use of CPLD and discrete component simulations to implement DDS principle. It utilized the filter circuit, integrated op-amp circuit and multiplier circuit instead of DAC chip. The range of frequency, amplitude and phase difference are 1Hz~1000Hz, 1V~3V and 0o~359o, respectively. The results show that a 2-channel sine signal generator can be designed with adjustable frequency, amplitude and phase dif

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Lafata, Pavel. "Investigation of phantom circuit benefits for next generation xDSL systems." International Journal of Communication Systems 29, no. 1 (2014): 5–15. http://dx.doi.org/10.1002/dac.2786.

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Kakarla, Deepti. "An optimized design approach for 8-bit pipelined ADC using high gain amplifier." i-manager’s Journal on Electronics Engineering 12, no. 2 (2022): 23. http://dx.doi.org/10.26634/jele.12.2.18529.

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Demand of high-performance converters with integrated circuits with combined features and specifications of power consumption, resolution and speed have become very dominant in many emerging applications. Pipelined ADC mixed signal system consists of Sample and Hold, Flash ADC, DAC and Gain amplifier in all the stages. In the present work, a pipeline ADC architecture has 3-stages, with each stage of 3-bits with 3-bit flash ADC followed by a 3-bit binary weighted DAC at each stage. A novel approach to design a 8-bit ADC is implemented, and this design offers less number of comparators compared

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Ameur, Noura Ben, Nouri Masmoudi та Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit". Journal of Circuits, Systems and Computers 24, № 03 (2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio D

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Ahmadi, Hamid, Wolfgang E. Denzel, Charles A. Murphy, and Erich Port. "A high-performance switch fabric for integrated circuit and packet switching." International Journal of Digital & Analog Cabled Systems 2, no. 4 (1989): 277–87. http://dx.doi.org/10.1002/dac.4520020411.

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Papadakis, Andreas E., Emmanuel S. Chaniotakis, Prokopis E. Giannakakis, Nikolaos D. Tselikas, and Iakovos S. Venieris. "Parlay-based service provision in circuit- and packet-switched telecommunications networks." International Journal of Communication Systems 17, no. 1 (2004): 63–83. http://dx.doi.org/10.1002/dac.631.

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Li, Tie Hu, Rui Tao Zhang, Wei Dong Yang, and Guang Bing Chen. "An Analog-Digital Clock DLL Control Circuit Used for High-Speed High-Resolution Digital-to-Analog Converter." Applied Mechanics and Materials 716-717 (December 2014): 1293–97. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1293.

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An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) ca

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