Relevant bibliographies by topics / Dadda's multiplier

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Dadda's multiplier'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Dadda's multiplier"

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Rajasekar, B., and K. Ashokkumar. "Low Power 4×4 Bit Multiplier Design Using DADDA, WALLACE Algorithm and Gate Diffusion Input Technology Kotha Vinil Kumar Reddy, Kondamuri Venkata Bala Manikanta Abhinav,." Journal of Computational and Theoretical Nanoscience 16, no. 8 (August 1, 2019): 3359–66. http://dx.doi.org/10.1166/jctn.2019.8220.

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We designed two different multipliers in order to reduce the power consumption, propagation delay and also area occupied by the multiplier. Previously there is a multiplier using DADDA algorithm that consumes high power and propagation delay also more in order to overcome that problems we designed multiplier using WALLACE algorithm. This multiplier can overcome those drawbacks. For more efficient multiplier we used GDI (Gate Diffusion Input) technology used along with the WALLACE algorithm. This model has been designed using Tanner EDA tool.
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Ramkumar, B., and Harish M. Kittur. "Faster and Energy-Efficient Signed Multipliers." VLSI Design 2013 (June 2, 2013): 1–12. http://dx.doi.org/10.1155/2013/495354.

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We demonstrate faster and energy-efficient column compression multiplication with very small area overheads by using a combination of two techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using new hybrid adder structures proposed here. Based on the proposed techniques, 8-b, 16-b, 32-b, and 64-b Wallace (W), Dadda (D), and HPM (H) reduction tree based Baugh-Wooley multipliers are developed and compared with the regular W, D, H based Baugh-Wooley multipliers. The performances of the proposed multipliers are analyzed by evaluating the delay, area, and power, with 65 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multipliers are as much as 29%, 27%, and 21% faster than the regular W, D, H based Baugh-Wooley multipliers, respectively, with a maximum of only 2.4% power overhead. Also, the power-delay products (energy consumption) of the proposed 16-b, 32-b, and 64-b multipliers are significantly lower than those of the regular Baugh-Wooley multiplier. Applicability of the proposed techniques to the Booth-Encoded multipliers is also discussed.
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Vijaya Lakshmi, K. N. V. S., and D. R. Sandeep. "LowPower32-Bit DADDA Multipleir." International Journal of Computer Trends and Technology 17, no. 5 (November 25, 2014): 237–44. http://dx.doi.org/10.14445/22312803/ijctt-v17p144.

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Ravi, S., Govind Shaji Nair, Rajeev Narayan, and Harish M. Kittur. "Low Power and Efficient Dadda Multiplier." Research Journal of Applied Sciences, Engineering and Technology 9, no. 1 (January 5, 2015): 53–57. http://dx.doi.org/10.19026/rjaset.9.1376.

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Alukuru, Girija, Janardhana Raju M, and Anilkumar Somasi. "Multi Operation Floating Point Architecture using DADDA Multiplier." International Journal of Engineering Trends and Technology 13, no. 8 (July 25, 2014): 391–93. http://dx.doi.org/10.14445/22315381/ijett-v13p278.

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Crawley, D. G., and G. A. J. Amaratunga. "8 × 8 bit pipelined dadda multiplier in CMOS." IEE Proceedings G (Electronic Circuits and Systems) 135, no. 6 (1988): 231. http://dx.doi.org/10.1049/ip-g-1.1988.0033.

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Ponnusamy, Anitha, and Palaniappan Ramanathan. "Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop." Applied Mechanics and Materials 573 (June 2014): 187–93. http://dx.doi.org/10.4028/www.scientific.net/amm.573.187.

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The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.
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G., Suresh. "Approximate Compressors based Inexact Vedic Dadda Multipliers." HELIX 8, no. 1 (January 1, 2018): 2683–90. http://dx.doi.org/10.29042/2018-2683-2690.

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Nandam, Krishna Sravani, K. Jamal, Anil Kumar Budati, Kiran Mannem, and Manchalla O. V. P. Kumar. "Design and analysis of Dadda multiplier with Common Boolean Logic." Materials Today: Proceedings 33 (2020): 4833–36. http://dx.doi.org/10.1016/j.matpr.2020.08.392.

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Beaulah, A. Vincy. "FPGA Implementation of Low Power DADDA Multipliers and its Application." International Journal of MC Square Scientific Research 7, no. 1 (July 17, 2015): 16–22. http://dx.doi.org/10.20894/ijmsr.117.007.001.003.

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Dissertations / Theses on the topic "Dadda's multiplier"

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Nezhad, Mohammad Reza Reshadi, and Kaivan Navi. "High-speed Multiplier Design Using Multi-Operand Multipliers." IJCSN, 2012. http://hdl.handle.net/10150/219513.

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Multipliers are used in most arithmetic computing systems such as 3D graphics, signal processing, and etc. It is inherently a slow operation as a large number of partial products are added to produce the result. There has been much work done on designing multipliers [1]-[6]. In first stage, Multiplication is implemented by accumulation of partial products, each of which is conceptually produced via multiplying the whole multi-digit multiplicand by a weighted digit of multiplier. To compute partial products, most of the approaches employ the Modified Booth Encoding (MBE) approach [3]-[5], [7], for the first step because of its ability to cut the number of partial products rows in half. In next step the partial products are reduced to a row of sums and a row of caries which is called reduction stage.
Multiplication is one of the major bottlenecks in most digital computing and signal processing systems, which depends on the word size to be executed. This paper presents three deferent designs for three-operand 4-bit multiplier for positive integer multiplication, and compares them in regard to timing, dynamic power, and area with classical method of multiplication performed on today architects. The three-operand 4-bit multipliers structure introduced, serves as a building block for three-operand multipliers in general
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Oskuii, Saeeid Tahmasbi. "Design of Low-Power Reduction-Trees in Parallel Multipliers." Doctoral thesis, Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-1958.

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Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well.

In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources.

In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations.

The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs.

Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.

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Chu, Wesley Donald. "Wallace and Dadda Multipliers implemented using carry lookahead adders." Thesis, 2013. http://hdl.handle.net/2152/24007.

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In a previous paper it was shown that the use of carry lookahead adders can reduce the delay it takes to compute the product with Wallace and Dadda multipliers. In this report, a more detailed analysis is provided on the use of carry lookahead adders to implement Dadda multipliers and Wallace multipliers. These two styles present different ways to use the arithmetic components and offer different benefits. Implementations of each style of multiplier are presented in this report. The performance delay and complexity of the implementations is compared and analyzed.
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Waters, Ronald S. "Total delay optimization for column reduction multipliers considering non-uniform arrival times to the final adder." Thesis, 2014. http://hdl.handle.net/2152/24858.

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Column Reduction Multiplier techniques provide the fastest multiplier designs and involve three steps. First, a partial product array of terms is formed by logically ANDing each bit of the multiplier with each bit of the multiplicand. Second, adders or counters are used to reduce the number of terms in each bit column to a final two. This activity is commonly described as column reduction and occurs in multiple stages. Finally, some form of carry propagate adder (CPA) is applied to the final two terms in order to sum them to produce the final product of the multiplication. Since forming the partial products, in the first step, is simply forming an array of the logical AND's of two bits, there is little opportunity for delay improvement for the first step. There has been much work done in optimizing the reduction stages for column multipliers in the second reduction step. All of the reduction approaches of the second step result in non-uniform arrival times to the input of the final carry propagate adder in the final step. The designs for carry propagate adders have been done assuming that the input bits all have the same arrival time. It is not evident that the non-uniform arrival times from the columns impacts the performance of the multiplier. A thorough analysis of the several column reduction methods and the impact of carry propagate adder designs, along with the column reduction design step, to provide the fastest possible final results, for an array of multiplier widths has not been undertaken. This dissertation investigates the design impact of three carry propagate adders, with different performance attributes, on the final delay results for four column reduction multipliers and suggests general ways to optimize the total delay for the multipliers.
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Book chapters on the topic "Dadda's multiplier"

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Gidd, Avinash, Shivani Ghasti, Snehal Jadhav, and K. Sivasankaran. "Performance Analysis of 32-Bit DADDA Multiplier Using 15–4 Compressor." In Communications in Computer and Information Science, 19–30. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_2.

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Gupta, Priya, Anu Gupta, and Abhijit Asati. "Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime." In Advances in Computational Intelligence and Robotics, 78–123. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-9474-3.ch004.

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In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.
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Conference papers on the topic "Dadda's multiplier"

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Guckert, Lauren, and Earl E. Swartzlander. "Dadda Multiplier designs using memristors." In 2017 IEEE International Conference on IC Design and Technology (ICICDT). IEEE, 2017. http://dx.doi.org/10.1109/icicdt.2017.7993521.

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Lanier, Travis, Jacob Wilcox, and Earl E. Swartzlander, Jr. "Automated synthesis of Dadda multipliers." In Optical Science and Technology, the SPIE 49th Annual Meeting, edited by Franklin T. Luk. SPIE, 2004. http://dx.doi.org/10.1117/12.559866.

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Pathak, Ketki C., Jignesh N. Sarvaiya, Anand D. Darji, Shreya Diwan, Anjali Gangadwala, Zinal Bhatt, and Azba Patel. "An Efficient Dadda Multiplier using Approximate Adder." In TENCON 2020 - 2020 IEEE REGION 10 CONFERENCE (TENCON). IEEE, 2020. http://dx.doi.org/10.1109/tencon50793.2020.9293737.

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Chanda, Saurav, Koushik Guha, Santu Patra, Anupam Karmakar, Loukrakpam Merin Singh, and Krishna Lal Baishnab. "A 32-bit Energy Efficient Exact Dadda Multiplier." In 2019 IEEE 5th International Conference for Convergence in Technology (I2CT). IEEE, 2019. http://dx.doi.org/10.1109/i2ct45611.2019.9033535.

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Bharathi, M., and Yasha Jyothi M. Shirur. "Optimized Synthesis of Dadda Multiplier Using ParallelPrefix Adders." In 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT). IEEE, 2019. http://dx.doi.org/10.1109/icssit46314.2019.8987897.

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Nandam, Madhav Venkata Srinivas, and Sudhakar Alluri. "High Performance 32 bit Dadda Multiplier Using EDA." In 2020 7th International Conference on Smart Structures and Systems (ICSSS). IEEE, 2020. http://dx.doi.org/10.1109/icsss49621.2020.9201958.

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Chanda, Saurav, Koushik Guha, Santu Patra, Loukrakpam Merin Singh, Krishna Lal Baishnab, and Prashanta Kumar Paul. "An Energy Efficient 32 Bit Approximate Dadda Multiplier." In 2020 IEEE Calcutta Conference (CALCON). IEEE, 2020. http://dx.doi.org/10.1109/calcon49167.2020.9106548.

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Townsend, Whitney J., Earl E. Swartzlander, Jr., and Jacob A. Abraham. "A comparison of Dadda and Wallace multiplier delays." In Optical Science and Technology, SPIE's 48th Annual Meeting, edited by Franklin T. Luk. SPIE, 2003. http://dx.doi.org/10.1117/12.507012.

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Ramachandran, G., CHANDRA KUMAR DIXIT, K. Kishore, and A. Arunraja. "Performance Analysis Of Mantissa Multiplier And Dadda Tree Multiplier And Implementing With Dsp Architecture." In 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS). IEEE, 2021. http://dx.doi.org/10.1109/icais50930.2021.9395883.

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Jeevan, B., S. Narender, C. V. K. Reddy, and K. Sivani. "A high speed binary floating point multiplier using Dadda algorithm." In 2013 International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s). IEEE, 2013. http://dx.doi.org/10.1109/imac4s.2013.6526454.

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