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Journal articles on the topic 'Dadda's multiplier'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

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1

Rajasekar, B., and K. Ashokkumar. "Low Power 4×4 Bit Multiplier Design Using DADDA, WALLACE Algorithm and Gate Diffusion Input Technology Kotha Vinil Kumar Reddy, Kondamuri Venkata Bala Manikanta Abhinav,." Journal of Computational and Theoretical Nanoscience 16, no. 8 (August 1, 2019): 3359–66. http://dx.doi.org/10.1166/jctn.2019.8220.

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We designed two different multipliers in order to reduce the power consumption, propagation delay and also area occupied by the multiplier. Previously there is a multiplier using DADDA algorithm that consumes high power and propagation delay also more in order to overcome that problems we designed multiplier using WALLACE algorithm. This multiplier can overcome those drawbacks. For more efficient multiplier we used GDI (Gate Diffusion Input) technology used along with the WALLACE algorithm. This model has been designed using Tanner EDA tool.

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2

Ramkumar, B., and Harish M. Kittur. "Faster and Energy-Efficient Signed Multipliers." VLSI Design 2013 (June 2, 2013): 1–12. http://dx.doi.org/10.1155/2013/495354.

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We demonstrate faster and energy-efficient column compression multiplication with very small area overheads by using a combination of two techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using new hybrid adder structures proposed here. Based on the proposed techniques, 8-b, 16-b, 32-b, and 64-b Wallace (W), Dadda (D), and HPM (H) reduction tree based Baugh-Wooley multipliers are developed and compared with the regular W, D, H based Baugh-Wooley multipliers. The performances of the proposed multipliers are analyzed by evaluating the delay, area, and power, with 65 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multipliers are as much as 29%, 27%, and 21% faster than the regular W, D, H based Baugh-Wooley multipliers, respectively, with a maximum of only 2.4% power overhead. Also, the power-delay products (energy consumption) of the proposed 16-b, 32-b, and 64-b multipliers are significantly lower than those of the regular Baugh-Wooley multiplier. Applicability of the proposed techniques to the Booth-Encoded multipliers is also discussed.

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3

Vijaya Lakshmi, K. N. V. S., and D. R. Sandeep. "LowPower32-Bit DADDA Multipleir." International Journal of Computer Trends and Technology 17, no. 5 (November 25, 2014): 237–44. http://dx.doi.org/10.14445/22312803/ijctt-v17p144.

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4

Ravi, S., Govind Shaji Nair, Rajeev Narayan, and Harish M. Kittur. "Low Power and Efficient Dadda Multiplier." Research Journal of Applied Sciences, Engineering and Technology 9, no. 1 (January 5, 2015): 53–57. http://dx.doi.org/10.19026/rjaset.9.1376.

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5

Alukuru, Girija, Janardhana Raju M, and Anilkumar Somasi. "Multi Operation Floating Point Architecture using DADDA Multiplier." International Journal of Engineering Trends and Technology 13, no. 8 (July 25, 2014): 391–93. http://dx.doi.org/10.14445/22315381/ijett-v13p278.

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6

Crawley, D. G., and G. A. J. Amaratunga. "8 × 8 bit pipelined dadda multiplier in CMOS." IEE Proceedings G (Electronic Circuits and Systems) 135, no. 6 (1988): 231. http://dx.doi.org/10.1049/ip-g-1.1988.0033.

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7

Ponnusamy, Anitha, and Palaniappan Ramanathan. "Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop." Applied Mechanics and Materials 573 (June 2014): 187–93. http://dx.doi.org/10.4028/www.scientific.net/amm.573.187.

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The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

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8

G., Suresh. "Approximate Compressors based Inexact Vedic Dadda Multipliers." HELIX 8, no. 1 (January 1, 2018): 2683–90. http://dx.doi.org/10.29042/2018-2683-2690.

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9

Nandam, Krishna Sravani, K. Jamal, Anil Kumar Budati, Kiran Mannem, and Manchalla O. V. P. Kumar. "Design and analysis of Dadda multiplier with Common Boolean Logic." Materials Today: Proceedings 33 (2020): 4833–36. http://dx.doi.org/10.1016/j.matpr.2020.08.392.

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10

Beaulah, A. Vincy. "FPGA Implementation of Low Power DADDA Multipliers and its Application." International Journal of MC Square Scientific Research 7, no. 1 (July 17, 2015): 16–22. http://dx.doi.org/10.20894/ijmsr.117.007.001.003.

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11

Venkatesh, K. "Reliable Low-Power DADDA Multiplier Design Using Fixed-Width Replica Redundancy Block." International Journal for Research in Applied Science and Engineering Technology V, no. VIII (August 30, 2017): 1462–69. http://dx.doi.org/10.22214/ijraset.2017.8207.

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12

P. VINAY, MALLIK, and HEMACHANDRA G. "Design of 2D-DCT and Quantization Using Dadda and Vedic Multipliers." i-manager's Journal on Digital Signal Processing 4, no. 3 (2016): 21. http://dx.doi.org/10.26634/jdp.4.3.8144.

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13

Sathanapally, Siddhardha. "Implementation of 4x4 Data bit Multiplier using Dadda Algorithm and Optimized Full Adder." International Journal for Research in Applied Science and Engineering Technology 8, no. 5 (May 31, 2020): 961–64. http://dx.doi.org/10.22214/ijraset.2020.5151.

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14

., R. Naveen. "A SURVEY OF LOW POWER WALLACE AND DADDA MULTIPLIERS USING DIFFERENT LOGIC FULL ADDERS." International Journal of Research in Engineering and Technology 03, no. 11 (November 25, 2014): 320–29. http://dx.doi.org/10.15623/ijret.2014.0311053.

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15

Gupta, Priya, Anu Gupta, and Abhijit Asati. "Ultra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold Regime." American Journal of Engineering and Applied Sciences 8, no. 4 (April 1, 2015): 702–16. http://dx.doi.org/10.3844/ajeassp.2015.702.716.

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16

Afzali-Kusha, Hassan, Marzieh Vaeztourshizi, Mehdi Kamal, and Massoud Pedram. "Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 5 (May 2020): 1207–20. http://dx.doi.org/10.1109/tvlsi.2020.2978874.

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17

Suman, Jami Venkata, D. G. Jignash, and B. I. Neelgar. "Design of Digital FIR Filter Based on MCMAT for 12 bit ALU using DADDA & WALLACE Tree Multiplier." International Journal of Hybrid Information Technology 7, no. 6 (November 30, 2014): 325–36. http://dx.doi.org/10.14257/ijhit.2014.7.6.28.

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18

Shabbir, Zain, Anas Razzaq Ghumman, and Shabbir Majeed Chaudhry. "A Reduced-sp- $$\hbox {D3L}_{\mathrm{sum}}$$ D3L sum Adder-Based High Frequency $$4\times 4$$ 4 × 4 Bit Multiplier Using Dadda Algorithm." Circuits, Systems, and Signal Processing 35, no. 9 (November 24, 2015): 3113–34. http://dx.doi.org/10.1007/s00034-015-0201-7.

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19

"Design of Dadda and Wallace Tree Multiplier Using Compressor Technique." International Journal of Engineering and Advanced Technology 8, no. 6S3 (November 22, 2019): 1551–54. http://dx.doi.org/10.35940/ijeat.f1280.0986s319.

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The work portrays about the design of the Dadda multiplier using 4:2 compressor techniques. The three design techniques, namely conventional design, optimized design using exclusive OR with multiplexer and a further optimized design with less number of critical paths with gates are implemented. All the three designs are implemented in Dadda multiplier and wallace tree multiplier and their performances are compared. The performance metrics measured are area, power consumption, delay and transistor count and these parameters are efficient in dadda multiplier compared to wallace tree multiplier with the above three design techniques. The designs are using behavioral modeling and the results are taken in the 180nm Cadence tool. The result shows that the Dadda multiplier performs better in terms of delay, area and transistor count for all three designs than the Wallace tree multiplier.

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20

"Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (July 10, 2019): 2007–14. http://dx.doi.org/10.35940/ijitee.i8517.078919.

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Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

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21

"VLSI Architecture of High Performance Multiplier for High Speed Applications." International Journal of Innovative Technology and Exploring Engineering 9, no. 3 (January 10, 2020): 442–45. http://dx.doi.org/10.35940/ijitee.b7405.019320.

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In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

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22

"Low Power Multiplier using Approximate Compressor for Error Tolerant Applications." International Journal of Engineering and Advanced Technology 9, no. 1S3 (December 31, 2019): 319–24. http://dx.doi.org/10.35940/ijeat.a1060.1291s319.

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Approximate or inexact computing has gained a significant amount of attention for error tolerant systems such as signal processing and image processing applications. In this paper, a comprehensive analysis and evaluation of multipliers realized using the existing approximate 4-2 compressors towards achieving low power has been presented. 8-bit Dadda multiplier has been chosen and the power consumption comparison has been performed. The exact multiplier has also been realized to enable the calculation of power savings for the approximate multipliers. An image compression algorithm using approximate multipliers has been implemented to analyze the operability of the approximate multipliers. Accuracy of the approximate multipliers has also been computed by means of Normalized Error Distance (NED) and PSNR. All the circuits are designed using 45nm CMOS process technology and simulations are carried out using Cadence® Virtuoso design tools.

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23

"Design and Implementation of Dual Mode Compressor Based 32 Bitdadda Multiplier using Modified Carry Select Adder." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (December 10, 2020): 1763–67. http://dx.doi.org/10.35940/ijitee.b7893.129219.

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In this paper, we tend to advocate 4:2 compressors, that have the flexibleness of trade between the particular andinexact operational modes.Multiplicationis based totally on multiply and adder unit,filtering,convolution which are extensively used in applications of signal processing. As, multiplication takes more execution time in DSP structures, there is need to develop high pace multipliers.In the approximate mode, those dual compressors offer quickness and decrease current consumptions on the fee of lower accuracy.Every single compressors has its personal diploma of efficiency interior the approximate mode moreover to one-of-a-kind delays and strength dissipations internal the approximate and true modesexploitation these compressors inside the buildings of parallel multipliers affords configurable multipliers whose accuracies (as properly as their powers and speeds) can even change dynamically at some stage within the runtime. The proficiency of this compressors in 32-bit Dadda multiplier factor are evaluated exploitation VerilogHDL and simulated and synthesized the usage of XILINX ISE style healthy evaluated by using the employment of modified Carry opt for adder.Comparing their parameters with those of the existing dadda multiplier designed using 4:2 compressors

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24

Edavoor, Pranose J., Sithara Raveendran, and Amol D. Rahulkar. "Novel 4:2 Approximate Compressor Designs for Multimedia and Neural Network Applications." Journal of Circuits, Systems and Computers, November 20, 2020, 2150138. http://dx.doi.org/10.1142/s0218126621501383.

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Low power dissipation in approximate arithmetic circuits has laid the foundation for area-efficient computational units for error resilient applications like image and signal processing. This paper proposes two novel low power high speed architectures for approximate 4:2 compressor that can be employed in multipliers for partial product summation. The two designs presented ([Formula: see text] and [Formula: see text]) have Error Distance (ED) of [Formula: see text] and Error Rate (ER) of 25%. The proposed [Formula: see text] and [Formula: see text] are able to achieve reduction in power and delay by (62.50%, 47.67%) and (83.13%, 60.20%), respectively, in comparison with the exact 4:2 compressor. To verify the effectiveness of the design, the proposed architectures are used to implement [Formula: see text] Dadda multiplier. The equal number of errors in positive and negative directions in the proposed designs aid in reducing the Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of the multiplier. Multiplication of images and two-level decomposition of 2D Haar wavelets are implemented using the designed Dadda multiplier. The efficiency of the image processing applications is measured in terms of Mean Structural Similarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR) and an average of 0.98 and 35[Formula: see text]dB, respectively, is obtained, which are in the acceptable range. In addition, a Convolutional Neural Network (CNN)-based LeNet-1 Handwritten Digit Recognition System (HDRS) is implemented using the proposed compressor-based multipliers. The proposed compressor-based architectures are able to achieve an average accuracy of 96.23%.

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25

"Design and Implementation of Inexact Compressors by using Multiplication." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (July 10, 2019): 141–48. http://dx.doi.org/10.35940/ijitee.h6996.078919.

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A feature model for the processing of digital is the estimated calculating at Nano metric scales. Accurate calculating is especially simulating for arithmetic designing of computer. This suggested project is contracts with the research and implementation of two new estimated 4-2 compressors for implementation in a multiplier. These implementations are depends on other characteristics of compression. Hence that inaccuracy in calculation as restrained by the rate of error and that called distance of normalized error can come across to figures of merits of implementation amount of transistors, delay and power consumption. Four various patterns for using the suggested estimated and evaluated for a Dadda multiplier wide ranging simulated outputs are given and the use of estimated multipliers to processing of image is given. The output displays that the given implementation achieved specified falls in the consuming of power, delay and count of transistors correlated to a specified implementation; in addition, two of the suggested multipliers implementation gives good abilities for multiplication of image to average NED and peak SNR (>50db) for the measured image examples

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26

"Novel Architecture for Binary Multiplication." International Journal of Innovative Technology and Exploring Engineering 8, no. 9S3 (August 23, 2019): 641–43. http://dx.doi.org/10.35940/ijitee.i3130.0789s319.

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Multipliers is the basic unit for all signal processing applications and other applications. In all technology advancement it plays a vital role, the targets are low power consumption, increase in speed, reduction in area etc. The computations that are done by a modern computers that includes microcomputers and microprocessor is astronomical. Even with the high speed computer chips the process of the data coming from the devices all over the world requires efficient algorithms and to achieve the compatibility we need to use the chip area effectively. The most often encountered computation in data processing or signal processing is the operation of multiplication. This architecture is to present a novice solution to reduce the total area of the multiplier by modifying the partial products addition multiplier. Generally, to compute the data with high speeds modern hardware uses the Wallace tree or dadda multiplication techniques. By reducing the number of partial products addition the number of gates can be reduced used to obtain the final result. In this proposed method we reduced the real-estate of the chip by using more number of full adder in the earlier stages of the partial products addition which is not present in the conventional multipliers.

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27

Kattekola, Naresh, Amol Jawale, Pallab Kumar Nath, and Shubhankar Majumdar. "Efficient partial product reduction for image processing application using approximate 4:2 compressor." Circuit World ahead-of-print, ahead-of-print (September 13, 2021). http://dx.doi.org/10.1108/cw-09-2020-0220.

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Purpose This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image. Design/methodology/approach The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block. Findings Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs. Originality/value The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

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28

"Complex Multipliers:Implementation using Efficient Algorithms for Signal Processing Application." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 1235–39. http://dx.doi.org/10.35940/ijrte.c5147.118419.

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The research efforts in low power electronic devices and the cellular networks has been strengthened with the continuous growth in mobile and portable systems . In the modern era there are various portable applications that needs low power(smaller & efficient battery) and higher mili ampere hour then before. Due to this, design of low power devices has now become a significant Performance criteria. While considering the elementary structure of Finite impulse Response Filter, that is the arrangement of multipliers(which is a systematic arrangements of adders) and dely. This manuscript represents the simulation , implementation & analysis report for performance evaluation to minimize delay & RAM consumption during calculation procedure. In this manuscript, we have coded , simulated & implemented selected multipliers such as Vedic, Wallace, Dadda, Booth, Array & Sequential multiplier. Comparative analysis has been done using Xylinx 14.4 with family Spartan6, device as xc6slx45, package csg324 with speed grade of -3 for bit length 2,4,8,16 & 32 using Wallace, dada, Sequential, array, Vedic & Booth Algorithm respectively.

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29

Arulkumar, M., and M. Chandrasekaran. "An Improved VLSI design of ALU based FIR Filter for Biomedical Image Filtering Application." Current Medical Imaging Formerly Current Medical Imaging Reviews 16 (August 17, 2020). http://dx.doi.org/10.2174/1573405616999200817101950.

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Aim: FIR filter is the most widely used device in DSP applications, which is also applicable to integrate with image processing approaches. The ALU based FIR structure is applicable for various devices to increase the performance. The ALU design operation includes accumulation, subtraction, shifting, multiplication and filtering. Existing methods are designed with various multipliers like Wallace tree multiplier, DADDA multiplier, Vedic multiplier and adders like carry select adder, and carry look-ahead adder. Objective: The main objective is to reduce the area, delay and power factors since optimum VLSI circuit is employed in this paper. By these adders and multipliers, operations are independently enabling main operations in DSP. The FIR filter is designed using a MAC unit with clock regenerative comparators. Introduction: In the field of VLSI industry, the low power, reduced time, and area-efficient designs are mostly preferred for various applications. Adders and multipliers play a vital role in VLSI circuit designs. The recent electronics industry uses a digital filter for various real-time applications. This utilizes Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, here the FIR filter is most stable than IIR filter. This FIR filter indicates the impulse signal into finite form and it is used mainly in DSP processors for getting high-speed. In these two ALU and FIR circuits, the adders and multiplier block's usage is increased it consumes much power. Method: The proposed research work uses the clock-gating technique for reducing power consumption. Here the latch-based clock gating technique provides an efficient result. XOR-based logic circuit reduces the design complexity and utilizes the less area. Carry save accumulator is a digital adder used for addition. It provides the two set of output, which is partial sum and carry output. The ripple carry adder uses full adder circuit for its operation. It propagates the carry value in last bit. For addition, the combination of CSA and RCA utilizes less area, high speed and provides the better through put. In multiplier block, the booth multiplier algorithm is used with XOR-based logic. Here this proposed FIR filter is designed for performing image filtration of retina image. This process improves the better visualization approach on medical field. Results: Thus, the design and analysis of proposed ALU based FIR filter with latch-based clock gating technique is designed and analyzed various parameters. Here the modified adders and multiplier is proposed for efficiency of the system. The modified carry save adder is proposed with combining ripple carry adder logic for improving the adders' performance. The enhanced booth multiplier is designed using add and shift method for reducing the number of stages to calculate the result. This process is applied to perform image processing of retina image. After designing the ALU based FIR filter structure in VLSI environment, the image is loaded on the MATLAB as the .png format then it is converted into hex file, which is read from the Xilinx to perform filtering the process. Then the 'dataout' is converted into binary file to obtain the result of filtering process. The enhanced booth multiplier reduces the delay by reducing the number of stages to calculate the result. Here the clock gating technique is proposed with the latch- based design for reducing the dynamic and clock power consumption. The number of adder's circuit in both ALU and FIR circuits is less since it improves the overall efficiency of the system. Conclusion: Thus the proposed methodology concluded that design and analysis of ALU based FIR filter for medical image processing gives the efficient result on the way of achieving the factors such that power (Static & Dynamic), Delay (Path delay) area utilization, MSE and PSNR. Here the image processing of FIR results to MSE and PSNR values, which obtained the better result than the existing VLSI based image processing works. The Latch- based clock gating circuit is connected with the proposed circuit, based on the gated clock signal it optimizes the gated circuit of the whole design since it also reduces the error and provides the efficient power report. This proposed VLSI model is simulated using Xilinx ISE 14.5 and Modelsim synthesizes it; here with the help of MATLAB with the adaptation of 2018a tool, the image filtering was done.

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30

Maitra, Subhashis. "16x16-bit Binary Multiplier using High Speed Modified Compressor." Micro and Nanosystems 12 (July 24, 2020). http://dx.doi.org/10.2174/1876402912999200724172742.

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Background: For higher order multiplications, a huge number of adders or compressors are used to perform the addition of the partial products. Objective: Hence the area and the propagation delay will increase. Researchers are trying to reduce the numbers of additions of partial products. Method: In this paper, different modified compressor have been proposed and based on that compressors, 16x16-bit binary multiplier has been discussed. Results: The proposed design provide better area, power consumption, critical path delay and less number of transistor counts when compared to other design using the conventional compressors. Here the proposed method has been used in Wallace tree multiplier or Dadda tree multiplier. The compressor used here has been implemented using Microwind DSCH 3.8 lite. Conclusion: The modified compressor makes the multiplier faster and reduces the number of addition of partial products..

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31

Priyadharshni, M., and S. Kumaravel. "Design of Imprecise Multipliers by Using Approximate Technique for Error Resilient Applications." Journal of Circuits, Systems and Computers, October 23, 2020, 2150114. http://dx.doi.org/10.1142/s0218126621501140.

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Approximate computing is the perfect way for error resilient applications with progress in speed and power but tradeoff with computational accuracy. In this paper, Imprecise Multipliers (IMs) are realized by segregating the partial products into two segments. The most significant bit (MSB) segment is accumulated as per Dadda tree structure and the least significant bit (LSB) segment is accumulated by approximate technique. The proposed Imprecise Multipliers, namely [Formula: see text] and [Formula: see text] are realized using Verilog HDL and simulated using TSMC 65[Formula: see text]nm process. For sake of comparison, the proposed multipliers [Formula: see text] and [Formula: see text] are compared with existing approximate multipliers. From the reported results, it may be noted that [Formula: see text] performs better in terms of area–delay product, power–delay product. While [Formula: see text] achieves a higher peak signal-to-noise ratio (PSNR) among all the multipliers existing in the literature.

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32

NAVEEN, R., K. THANUSHKODI, and C. SARANYA. "Low power wallace and dadda multiplier based on CLRCL full adder." IJARCCE, December 27, 2014, 8696–99. http://dx.doi.org/10.17148/ijarcce.2014.31208.

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