Relevant bibliographies by topics / Data encryption (Computer science) Field programmable gate arrays

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Academic literature on the topic 'Data encryption (Computer science) Field programmable gate arrays'

Author: Grafiati
Published: 4 June 2021
Last updated: 10 February 2022

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Journal articles on the topic "Data encryption (Computer science) Field programmable gate arrays"

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Amira, Abbes, Mazen A. R. Saghir, Naeem Ramzan, Christos Grecos, and Florian Scherb. "A Reconfigurable Wireless Environment for ECG Monitoring and Encryption." International Journal of Embedded and Real-Time Communication Systems 4, no. 3 (July 2013): 72–87. http://dx.doi.org/10.4018/ijertcs.2013070104.

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Connected health is the convergence of medical devices, security devices, and communication technologies. It enables patients to be monitored and treated remotely from their home or primary care facility rather than attend outpatient clinics or be admitted to hospital. Patients’ data and medical records within a connected health system should be securely transmitted and saved for further analysis and diagnosis. This paper presents a reconfigurable wireless system for electrocardiogram (ECG) monitoring which can be deployed in a connected health environment. Efficient field programmable gate array (FPGA) implementation for the ECG encryption block has been carried out on the RC10 prototyping board using the advanced encryption standard (AES) algorithm. Results presented have shown that the proposed AES implementation outperforms the existing FPGA-based systems in different key performance metrics and that ECG signals acquired using the VitalSens device can be encrypted/decrypted in real-time. A software based evaluation approach has been also performed to validate the proposed hardware implementation. The proposed solution can be deployed for electronic archiving of health records information systems and health monitoring technologies in personalized medicine.
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Gurumanapalli, Krishna, and Nagendra Muthuluru. "A Non Linear PUF Circuit Design for Two Factor Authentication in IoT Cryptography." International Journal of Intelligent Engineering and Systems 14, no. 1 (February 28, 2021): 169–80. http://dx.doi.org/10.22266/ijies2021.0228.17.

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Internet-of-Things (IoT) is growing network paradigm which enables mutual communication between the user and smart devices using the internet. The IoT devices are susceptible to the security threats, due to placement of restricted computational capabilities of the computing devices in IoT. The conventional encryption algorithm utilizes the high amount of resource block in it which increases the area and power. Moreover, Two Factor Authentication (TFA) scheme based authentication protocols does not have the efficiency to secure the data. Because the random number generated by the TFA is ideal for all IoT devices which are easy to hack by the unauthorized persons. In this Research paper, the Linear Feedback Shift Register (LFSR) based Reconfigurable Physical Unclonable Function (RPUF) is proposed to overcome the security issues caused in the IoT communication. The RPUF is designed based on the LFSR to generate the random number for every clock cycle. Normally, reconfigurable process helps to generate the different output values for every clock cycle. But, it failed to generate different outputs for same input values. Here, LFSR based RPUF helps to generated the different response values even the same challenge is given to the input side. The Lightweight TFA scheme is presented for IoT, where PUF has been considered as one of the major authentication factors. At last, Spartan 6 and Virtex 6 Field Programmable Gate Array (FPGA) performances are calculated for proposed TFA-RPUF-IoT and existing TFA-PUF-IoT protocols. In Spartan 6, TFA-RPUF-IoT protocol occupied 11 slices, 31 LUTs, 42 flip flops which are less compared to conventional TFA-PUF-IoT.
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Tang, Linhuai, Zhihong Huang, Gang Cai, Yong Zheng, and Jiamin Chen. "A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs." Algorithms 14, no. 2 (January 20, 2021): 30. http://dx.doi.org/10.3390/a14020030.

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Due to high parallelism, field-programmable gate arrays are widely used as accelerators in engineering and scientific fields, which involve a large number of operations of vector and matrix. High-performance accumulation circuits are the key to large-scale matrix operations. By selecting the adder as the reduction operator, the reduction circuit can implement the accumulation function. However, the pipelined adder will bring challenges to the design of the reduction circuit. To solve this problem, we propose a novel reduction circuit based on binary tree path partition, which can simultaneously handle multiple data sets with arbitrary lengths. It divides the input data into multiple groups and sends them to different iterations for calculation. The elements belonging to the same data set in each group are added to obtain a partial result, and the partial results of the same data set are added to achieve the final result. Compared with other reduction methods, it has the least area-time product.
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Hernández, Mario, Juan M. Cebrián, José M. Cecilia, and José M. García. "Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance." International Journal of High Performance Computing Applications 34, no. 2 (November 7, 2017): 199–207. http://dx.doi.org/10.1177/1094342017738352.

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The ever-increasing computational requirements of HPC and service provider applications are becoming a great challenge for hardware and software designers. These requirements are reaching levels where the isolated development on either computational field is not enough to deal with such challenge. A holistic view of the computational thinking is therefore the only way to success in real scenarios. However, this is not a trivial task as it requires, among others, of hardware–software codesign. In the hardware side, most high-throughput computers are designed aiming for heterogeneity, where accelerators (e.g. Graphics Processing Units (GPUs), Field-Programmable Gate Arrays (FPGAs), etc.) are connected through high-bandwidth bus, such as PCI-Express, to the host CPUs. Applications, either via programmers, compilers, or runtime, should orchestrate data movement, synchronization, and so on among devices with different compute and memory capabilities. This increases the programming complexity and it may reduce the overall application performance. This article evaluates different offloading strategies to leverage heterogeneous systems, based on several cards with the first-generation Xeon Phi coprocessors (Knights Corner). We use a 11-point 3-D Stencil kernel that models heat dissipation as a case study. Our results reveal substantial performance improvements when using several accelerator cards. Additionally, we show that computing of an approximate result by reducing the communication overhead can yield 23% performance gains for double-precision data sets.
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Kocz, J., V. Ravi, M. Catha, L. D’Addario, G. Hallinan, R. Hobbs, S. Kulkarni, et al. "DSA-10: a prototype array for localizing fast radio bursts." Monthly Notices of the Royal Astronomical Society 489, no. 1 (August 12, 2019): 919–27. http://dx.doi.org/10.1093/mnras/stz2219.

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ABSTRACT The Deep Synoptic Array 10-dish prototype (DSA-10) is an instrument designed to detect and localize fast radio bursts with arcsecond accuracy in real time. Deployed at Owens Valley Radio Observatory, it consists of ten 4.5-m diameter dishes, equipped with a 250-MHz bandwidth dual polarization receiver, centred at 1.4 GHz. The 20 input signals are digitized and field programmable gate arrays are used to transform the data to the frequency domain and transmit it over ethernet. A series of computer servers buffer both raw data samples and perform a real time search for fast radio bursts on the incoherent sum of all inputs. If a pulse is detected, the raw data surrounding the pulse are written to disc for coherent processing and imaging. The prototype system was operational from 2017 June to 2018 February conducting a drift scan search. Giant pulses from the Crab Pulsar were used to test the detection and imaging pipelines. The 10-dish prototype system was brought online again in 2019 March, and will gradually be replaced with the new DSA-110, a 110-dish system, over the next 2 yr to improve sensitivity and localization accuracy.
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Farooqi, Q. R., B. Snyder, and S. Anwar. "Real Time Monitoring of Diesel Engine Injector Waveforms for Accurate Fuel Metering and Control." Journal of Control Science and Engineering 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/973141.

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This paper presents the development, experimentation, and validation of a reliable and robust system to monitor the injector pulse generated by an engine control module (ECM) which can easily be calibrated for different engine platforms and then feedback the corresponding fueling quantity to the real-time computer in a closed-loop controller in the loop (CIL) bench in order to achieve optimal fueling. This research utilizes field programmable gate arrays (FPGA) and direct memory access (DMA) transfer capability to achieve high speed data acquisition and delivery. This work is conducted in two stages: the first stage is to study the variability involved in the injected fueling quantity from pulse to pulse, from injector to injector, between real injector stators and inductor load cells, and over different operating conditions. Different thresholds have been used to find out the best start of injection (SOI) threshold and the end of injection (EOI) threshold that capture the injector “on-time” with best reliability and accuracy. Second stage involves development of a system that interprets the injector pulse into fueling quantity. The system can easily be calibrated for various platforms. Finally, the use of resulting correction table has been observed to capture the fueling quantity with highest accuracy.
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Pilz, Sarah, Florian Porrmann, Martin Kaiser, Jens Hagemeyer, James M. Hogan, and Ulrich Rückert. "Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs." Algorithms 13, no. 2 (February 21, 2020): 47. http://dx.doi.org/10.3390/a13020047.

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This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison. Modern applications which involve comparisons across large data sets—such as large sequence sets in molecular biology—are by their nature computationally intensive. In this work, we present a scalable FPGA-based system architecture to accelerate the comparison of binary strings. The current architecture supports arbitrary lengths in the range 16 to 2048-bit, covering a wide range of possible applications. In our example application, we consider DNA sequences embedded in a binary vector space through Locality Sensitive Hashing (LSH) one of several possible encodings that enable us to avoid more costly character-based operations. Here the resulting encoding is a 512-bit binary signature with comparisons based on the Hamming distance. In this approach, most of the load arises from the calculation of the O ( m ∗ n ) Hamming distances between the signatures, where m is the number of queries and n is the number of signatures contained in the database. Signature generation only needs to be performed once, and we do not consider it further, focusing instead on accelerating the signature comparisons. The proposed FPGA-based architecture is optimized for high-throughput using hundreds of computing elements, arranged in a systolic array. These core computing elements can be adapted to support other string comparison algorithms with little effort, while the other infrastructure stays the same. On a Xilinx Virtex UltraScale+ FPGA (XCVU9P-2), a peak throughput of 75.4 billion comparisons per second—of 512-bit signatures—was achieved, using a design with 384 parallel processing elements and a clock frequency of 200 MHz. This makes our FPGA design 86 times faster than a highly optimized CPU implementation. Compared to a GPU design, executed on an NVIDIA GTX1060, it performs nearly five times faster.
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Nayak, Jayant Kumar, Vatsala Prasad, and Ranjan Ganguli. "A Field Programmable Gate Array (FPGA) Based Non-Linear Filters for Gas Turbine Prognostics." International Journal of Prognostics and Health Management 12, no. 3 (April 27, 2021). http://dx.doi.org/10.36001/ijphm.2021.v12i3.2960.

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The removal of noise from signals obtained through the health monitoring systems in gas turbines is an important consideration for accurate prognostics. Several filters have been designed and tested for this purpose, and their performance analysis has been conducted. Linear filters are inefficient in the removal of outliers and noise because they cause smoothening of the sharp features in the signal which can indicate the onset of a fault event. On the other hand, non-linear filters based on image processing methods can provide more precise results for gas turbine health signals. Among others, the weighted recursive median (WRM) filter has been shown to provide greater accuracy due to its weight adaptability depending on the signal type. However, sampling data at high rates is possible which needs hardware implementation of the filter. In this paper, the design, simulation and implementation of WRM filters on the FPGA (Field Programmable Gate Arrays) platforms Vivado Design Suite by Xilinx and Quartus Pro Lite Edition 19.3 has been performed. The architectural detail and performance result with the FPGA filters when subjected to abrupt and gradual fault signal is presented.
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Schumann, Johann, Kristin Y. Rozier, Thomas Reinbacher, Ole J. Mengshoel, Timmy Mbaya, and Corey Ippolito. "Towards Real-time, On-board, Hardware-supported Sensor and Software Health Management for Unmanned Aerial Systems." International Journal of Prognostics and Health Management 6, no. 1 (November 1, 2020). http://dx.doi.org/10.36001/ijphm.2015.v6i1.2243.

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For unmanned aerial systems (UAS) to be successfully deployed and integrated within the national airspace, it is imperative that they possess the capability to effectively complete their missions without compromising the safety of other aircraft, as well as persons and property on the ground. This necessity creates a natural requirement for UAS that can respondto uncertain environmental conditions and emergent failures in real-time, with robustness and resilience close enough to those of manned systems. We introduce a system that meets this requirement with the design of a real-time onboard system health management (SHM) capability to continuously monitor sensors, software, and hardware components. This system can detect and diagnose failures and violations of safety or performance rules during the flight of a UAS. Our approach to SHM is three-pronged, providing: (1) real-time monitoring of sensor and software signals; (2) signal analysis, preprocessing, and advanced on-the-fly temporal and Bayesian probabilistic fault diagnosis; and (3) an unobtrusive, lightweight, read-only, low-power realization using Field Programmable Gate Arrays (FPGAs) that avoids overburdening limited computing resources or costly re-certification of flight software. We call this approach rt-R2U2, a name derived from its requirements. Our implementation provides a novel approach of combining modular building blocks, integrating responsive runtime monitoring of temporal logic system safety requirements with model-based diagnosis and Bayesian network-based probabilistic analysis. We demonstrate this approach using actual flight data from theNASA Swift UAS.
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Dissertations / Theses on the topic "Data encryption (Computer science) Field programmable gate arrays"

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Orlando, Gerardo. "Efficient elliptic curve processor architectures for field programmable logic." Link to electronic thesis, 2002. http://www.wpi.edu/Pubs/ETD/Available/etd-0327102-103635.

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Van, Dyken Jason Daniel. "Schemes to reduce power in FPGA implementations of the advanced encryption standard." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/J_Van_Dyken_111307.pdf.

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Huang, Jian Li Hao. "FPGA implementations of elliptic curve cryptography and Tate pairing over binary field." [Denton, Tex.] : University of North Texas, 2007. http://digital.library.unt.edu/permalink/meta-dc-3963.

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Ramsey, Glenn. "Hardware/software optimizations for elliptic curve scalar multiplication on hybrid FPGAs /." Online version of thesis, 2008. http://hdl.handle.net/1850/7765.

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Huang, Jian. "FPGA Implementations of Elliptic Curve Cryptography and Tate Pairing over Binary Field." Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc3963/.

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Elliptic curve cryptography (ECC) is an alternative to traditional techniques for public key cryptography. It offers smaller key size without sacrificing security level. Tate pairing is a bilinear map used in identity based cryptography schemes. In a typical elliptic curve cryptosystem, elliptic curve point multiplication is the most computationally expensive component. Similarly, Tate pairing is also quite computationally expensive. Therefore, it is more attractive to implement the ECC and Tate pairing using hardware than using software. The bases of both ECC and Tate pairing are Galois field arithmetic units. In this thesis, I propose the FPGA implementations of the elliptic curve point multiplication in GF (2283) as well as Tate pairing computation on supersingular elliptic curve in GF (2283). I have designed and synthesized the elliptic curve point multiplication and Tate pairing module using Xilinx's FPGA, as well as synthesized all the Galois arithmetic units used in the designs. Experimental results demonstrate that the FPGA implementation can speedup the elliptic curve point multiplication by 31.6 times compared to software based implementation. The results also demonstrate that the FPGA implementation can speedup the Tate pairing computation by 152 times compared to software based implementation.
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Sewell, George E. "Security for the processor-to-memory interface using field programmable gate arrays." Diss., 2007. http://etd.library.vanderbilt.edu/ETD-db/available/etd-07242007-104504/.

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"Implementation of an FPGA based accelerator for virtual private networks." 2002. http://library.cuhk.edu.hk/record=b5895989.

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Cheung Yu Hoi Ocean.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 65-70).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Aims --- p.2
Chapter 1.3 --- Contributions --- p.3
Chapter 1.4 --- Thesis Outline --- p.3
Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4
Chapter 2.1 --- Introduction --- p.4
Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4
Chapter 2.3 --- Secure Virtual Private Network --- p.6
Chapter 2.4 --- LibDES --- p.9
Chapter 2.5 --- FreeS/WAN --- p.9
Chapter 2.6 --- Commercial VPN solutions --- p.9
Chapter 2.7 --- Summary --- p.11
Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12
Chapter 3.1 --- Introduction --- p.12
Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12
Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14
Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16
Chapter 3.3 --- The IDEA Algorithm --- p.17
Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20
Chapter 3.3.2 --- Previous work on IDEA --- p.21
Chapter 3.4 --- Block Cipher Modes of operation --- p.23
Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23
Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25
Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27
Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27
Chapter 3.6 --- Pilchard --- p.30
Chapter 3.6.1 --- Memory Cache Control Mode --- p.31
Chapter 3.7 --- Electronic Design Automation Tools --- p.32
Chapter 3.8 --- Summary --- p.33
Chapter 4 --- Implementation
Chapter 4.1 --- Introduction --- p.36
Chapter 4.1.1 --- Hardware Platform --- p.36
Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36
Chapter 4.1.3 --- Pilchard Software --- p.38
Chapter 4.2 --- DES in ECB mode --- p.39
Chapter 4.2.1 --- Hardware --- p.39
Chapter 4.2.2 --- Software Interface --- p.40
Chapter 4.3 --- DES in CBC mode --- p.42
Chapter 4.3.1 --- Hardware --- p.42
Chapter 4.3.2 --- Software Interface --- p.42
Chapter 4.4 --- Triple-DES in CBC mode --- p.45
Chapter 4.4.1 --- Hardware --- p.45
Chapter 4.4.2 --- Software Interface --- p.45
Chapter 4.5 --- IDEA in ECB mode --- p.48
Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48
Chapter 4.5.2 --- Hardware --- p.48
Chapter 4.5.3 --- Software Interface --- p.50
Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51
Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52
Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53
Chapter 4.9 --- Summary --- p.54
Chapter 5 --- Results --- p.55
Chapter 5.1 --- Introduction --- p.55
Chapter 5.2 --- Benchmarking environment --- p.55
Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56
Chapter 5.3.1 --- Performance of Triple-DES core --- p.55
Chapter 5.3.2 --- Performance of IDEA core --- p.58
Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59
Chapter 5.4.1 --- Triple-DES --- p.59
Chapter 5.4.2 --- IDEA --- p.60
Chapter 5.5 --- Summary --- p.61
Chapter 6 --- Conclusion --- p.62
Chapter 6.1 --- Future development --- p.63
Bibliography --- p.65
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Books on the topic "Data encryption (Computer science) Field programmable gate arrays"

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Francisco, Rodriquez-Henriquez, ed. Cryptographic algorithms on reconfigurable hardware. New York: Springer, 2006.

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Conference papers on the topic "Data encryption (Computer science) Field programmable gate arrays"

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Krainyk, Yaroslav, and Yevhen Davydenko. "Mathematical Model of Transposition Chaotic Encryption System Based on Field-Programmable Gate Arrays for Multimedia Data." In 2019 IEEE International Scientific-Practical Conference Problems of Infocommunications, Science and Technology (PIC S&T). IEEE, 2019. http://dx.doi.org/10.1109/picst47496.2019.9061400.

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