Journal articles on the topic 'Data pipelining technology'

Data transmission of electroencephalography (EEG) signals over Wireless Body Area Network (WBAN) is currently a widely used system that comes together with challenges in terms of efficiency and effectivity. In this study, an effective Very-Large-Scale Integration (VLSI) circuit design of lossless EEG compression circuit is proposed to increase both efficiency and effectivity of EEG signal transmission over WBAN. The proposed design was realized based on a novel lossless compression algorithm which consists of an adaptive fuzzy predictor, a voting-based scheme and a tri-stage entropy encoder. The tri-stage entropy encoder is composed of a two-stage Huffman and Golomb-Rice encoders with static coding table using basic comparator and multiplexer components. A pipelining technique was incorporated to enhance the performance of the proposed design. The proposed design was fabricated using a 0.18 μm CMOS technology containing 8405 gates with 2.58 mW simulated power consumption under an operating condition of 100 MHz clock speed. The CHB-MIT Scalp EEG Database was used to test the performance of the proposed technique in terms of compression rate which yielded an average value of 2.35 for 23 channels. Compared with previously proposed hardware-oriented lossless EEG compression designs, this work provided a 14.6% increase in compression rate with a 37.3% reduction in hardware cost while maintaining a low system complexity.

Abstract. The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz−1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

The experience of the use of applied containerized biomedical software tools in cloud environment is summarized. The reproducibility of scientific computing in relation with modern technologies of scientific calculations is discussed. The main approaches to biomedical data preprocessing and integration in the framework of the intelligent analytical system are described. At the conditions of pandemic, the success of health care system depends significantly on the regular implementation of effective research tools and population monitoring. The earlier the risks of disease can be identified, the more effective process of preventive measures or treatments can be. This publication is about the creation of a prototype for such a tool within the project «Development of methods, algorithms and intelligent analytical system for processing and analysis of heterogeneous clinical and biomedical data to improve the diagnosis of complex diseases» (M/99-2019, M/37-2020 with support of the Ministry of Education and Science of Ukraine), implementted by the V.M. Glushkov Institute of Cybernetics, National Academy of Sciences of Ukraine, together with the United Institute of Informatics Problems, National Academy of Sciences of Belarus (F19UKRG-005 with support of the Belarussian Republican Foundation for Fundamental Research). The insurers, entering the market, can insure mostly low risks by facilitating more frequent changes of insurers by consumers (policyholders) and mixing the overall health insurance market. Socio-demographic variables can be risk adjusters. Since age and gender have a relatively small explanatory power, other socio-demographic variables were studied – marital status, retirement status, disability status, educational level, income level. Because insurers have an interest in beneficial diagnoses for their policyholders, they are also interested in the ability to interpret relevant information – upcoding: insurers can encourage their policyholders to consult with doctors more often to select as many diagnoses as possible. Many countries and health care systems use diagnostic information to determine the reimbursement to a service provider, revealing the necessary data. For processing and analysis of these data, software implementations of construction for classifiers, allocation of informative features, processing of heterogeneous medical and biological variables for carrying out scientific research in the field of clinical medicine are developed. The experience of the use of applied containerized biomedical software tools in cloud environment is summarized. The reproducibility of scientific computing in relation with modern technologies of scientific calculations is discussed. Particularly, attention is paid to containerization of biomedical applications (Docker, Singularity containerization technology), this permits to get reproducibility of the conditions in which the calculations took place (invariability of software including software and libraries), technologies of software pipelining of calculations, that allows to organize flow calculations, and technologies for parameterization of software environment, that allows to reproduce, if necessary, an identical computing environment. The main approaches to biomedical data preprocessing and integration in the framework of the intelligent analytical system are described. The experience of using the developed linear classifier, gained during its testing on artificial and real data, allows us to conclude about several advantages provided by the containerized form of the created application: it permits to provide access to real data located in cloud environment; it is possible to perform calculations to solve research problems on cloud resources both with the help of developed tools and with the help of cloud services; such a form of research organization makes numerical experiments reproducible, i.e. any other researcher can compare the results of their developments on specific data that have already been studied by others, in order to verify the conclusions and technical feasibility of new results; there exists a universal opportunity to use the developed tools on technical devices of various classes from a personal computer to powerful cluster.

Summary This paper describes a study of the potential of a tight reservoir zone for disposal of brine generated in salt cavern leaching operations. The study included field injection testing, numerical analysis using uncoupled and coupled reservoir, geomechanical and fracturing modeling, laboratory work and design of a field injection monitoring program. It was shown that a surprising brine disposal capacity exists in the tight (0.03 md) Oriskany target formation. Initial screening was followed by carefully designed injection testing, laboratory work and subsequent evaluation with the aid of detailed coupled fracture and reservoir numerical models, and numerical well test analysis. Low initial estimates of brine disposal capacity were increased significantly by incorporating more sophisticated, coupled reservoir and geomechanical numerical models. The models, which account for stress dependent porosity and permeability and fracture propagation, were calibrated to laboratory and field test data. Using these models, an excellent match of the injection data was obtained, and predictions of injectivity were made under various project scenarios. The coupled model has been also used to design the monitoring program for the first phase of the injection operations. Introduction Gas storage in salt caverns has many advantages over conventional storage operations in reservoirs. In the U.S. alone, over 30 caverns have been built and put into operation. On the other hand, the selection of the site, design and execution of the leaching process, commissioning, operating and monitoring the caverns requires specialized, multidisciplinary technology.1,2 This paper deals only with one facet of the overall process, namely, the disposal of the brine generated during the leaching process by reinjection. This topic has many similarities to other injection processes in petroleum engineering and will be of interest to those working in waterflooding or waste disposal at or near fracturing conditions, and in geomechanics and fracturing. In cavern leaching operations, large amounts of concentrated brine are generated which need to be treated or disposed of. In general, there are several ways to dispose of or utilize the brine, such as selling it for salt products manufacture, building a salt product manufacturing plant, disposal in suitable permeable formations, or even pipelining to the sea. The economical and environmental aspects of each alternative guide the selection of the best method (or combination of several methods). Even more importantly, the efficiency of the brine disposal is one of the critical elements for the economics of a planned cavern gas storage project. In the subject project described below, disposal by reinjecting the brine was considered in conjunction with selling the majority of the brine to a salt product company. The Tioga Gas Storage Project The location of the project in Tioga, Pennsylvania, was selected by its developer Market Hub Partners (MHP) based on gas market analysis and geological considerations. Key elements included finding a salt formation which would be an excellent candidate for cavern leaching, close to existing pipelines and infrastructure. Such a formation was found below the existing Tioga gas storage field. As shown in Fig. 1, MHP is planning to build up to ten storage caverns in this massive (2200 ft thick) salt formation, separated from the Oriskany gas storage formation by 400 ft of limestone and anhydrite shale. The structural crossection of the storage site, with a proposed cavern location, is shown in Fig. 2. Each cavern will provide around 2,500,000 MScf of storage and in the process of leaching will generate about 25 million bbls of brine per cavern. These fluid volumes provide a large incentive to find a suitable horizon for disposal of the brine, and to prove up the injection capacity. Disposal Site Selection and Geology Two sites were selected for brine disposal, based on a geological review including the interpretation of 7 seismic lines and 120 wells in the vicinity of the Tioga storage pool. The brine disposal areas are 1.5 miles south of the gas storage field, and isolated from it by a series of faults of more than 1,000 ft of thrust (see Fig. 2). The target injection zone consists of the middle Devonian Oriskany sandstone and Helderberg limestone. These formations are isolated from the shallow drinking water aquifer by 4,800 ft of upper Devonian shales, including a strike of very tight limestone. The underlying formations consist of a layer of anhydrite on top of the salt section (Salina). The first brine disposal test well SWD#01 (see Fig. 3) was drilled in June 1995 and confirmed the results of the geological review. SWD#01 was cored in the Oriskany, Helderberg, Anhydrite and salt. Exploratory Testing of the Target Zones A first DST, followed by the injection of 600 barrels of brine, was performed in the Oriskany. The injection/fall-off test was conducted above parting pressure, in order to achieve a commercial rate (22 gpm). The well was then deepened to reach TD, at 5,750 ft GL. A set of logs were run, including an FMI log, which confirmed an induced fracture in the Oriskany zone. A second DST was performed, in the Oriskany, Helderberg, and Anhydrite sections, followed by the injection of 1,200 barrels of brine. The pressure signature was similar to DST#1. A second FMI log was conducted, which exhibited new induced fracturing in the Helderberg. SWD#01 was then cased, cemented and perforated in the Oriskany and Helderberg. Stress tests were conducted in the Oriskany and the Helderberg.

In this paper, a new high speed control circuit is proposed which will act as a critical path for the data which will go from input to output to improve the performance of wave pipelining circuits The wave pipelining is a method of high performance circuit designs which implements pipelining in logic without the use of intermediate registers. Wave pipelining has been widely used in the past few years with a great deal of significant features in technology and applications. It has the ability to improve speed, efficiency, economy in every aspect which it presents. Wave pipelining is being used in wide range of applications like digital filters, network routers, multipliers, fast convolvers, MODEMs, image processing, control systems, radars and many others. In previous work, the operating speed of the wave-pipelined circuit can be increased by the following three tasks: adjustment of the clock period, clock skew and equalization of path delays. The path-delay equalization task can be done theoretically, but the real challenge is to accomplish it in the presence of various different delays. So, the main objective of this paper is to solve the path delay equalization problem by inserting the control circuit in wave pipelined based circuit which will act as critical path for the data that moves from input to output. The proposed technique is evaluated for DSP applications by designing 4- tap FIR filter using Distributed arithmetic algorithm (DAA). Then comparison of this design is done with 4-tap FIR filter designs using conventional pipelining and non pipelining. The synthesis and simulation results based on Xilinx ISE Navigator 12.3 shows that wave pipelined DAA based filter is faster by a factor of 1.43 compared to non pipelined one and the conventional pipelined filter is faster than non pipelined by factor of 1.61 but at the cost of increased logic utilization by 200 %. So, the wave-pipelined DA filters designed with the proposed control circuit can operate at higher frequency than that of non-pipelined but less than that of pipelined. The gain in speed in pipelined compared to that of wavepipelined is at the cost of increased area and more dissipated power. When latency is considered, wavepipelined design filters with the proposed scheme are having the lowest latency among three schemes designed.

The paper presents the implementation of compliant DDR3 memory controller. It discusses the overall architecture of the DDR3 controller along with the detailed design and operation of its individual sub blocks, the pipelining implemented in the design to increase the design throughput. It also discusses the advantages of DDR3 memories over DDR2 memories operation. Double Data Rate (DDR) SDRAMs have been prevalent in the PC memory market in recent years and are widely used for networking systems. These memory devices are rapidly developing, with high density, high memory bandwidth and low device cost. However, because of the high-speed interface technology and complex instruction-based memory access control, a specific purpose memory controller is necessary for optimizing the memory access trade off. In this paper, a specific purpose DDR3 controller for highperformance is proposed.

The bit size of the data length process depends on the clock speed operation .the clock speed increases with the bit size of the data length .but this increases deal in the circuit to overcome this pipeline and parallel processing is used. This will increase the performance of the circuit with the advancement of the high speed technology the data length process per clock is increasing rapidly from Intel 1 intel20 to Intel series. Adder is an important adder structure design which uses parallel and pipelining scheme are RCA and SFA. To design these adders we need high speed processing digital electronic circuit which must be high speed and low power. There are various types of logic families which we are discuss in this paper. From static to dynamic circuit design why dynamic is faster than static. and various types of dynamic circuit design structure this paper basically focus on constant delay logic style and why it is superior to other dynamic structures such as domino logic ,dynamic logic np CMOS logic,C2MOS logic ,NORA CMOS logic design, Zipper CMOS,FTL logic.

Invention of new electronic devices in this technology driven-world has been setting a new scale for faster reach in terms of utilization and communication. The imperfection in the System on Chip (SoC) lead to an innovation of Network on Chip (NoC) that elucidates the communication defects and thereby set a new path for the researchers to enhance the network connectivity. Nature is an inspiration for most of the technologies invented by the researchers. In this paper, we have dealt the existing physical flows and future difficulties with Reliable Reconfigurable Real-Time Operating System (R3TOS) as a software interface with NoC with the proposed customized topology of Transmission Rate based Topology Design using Dolphin Echolocation (TRTD-DE) algorithm. Echolocation is biological scanning system that used by dolphins for movement and chasing the prey. The above ability along with Data flow pipelining (DFP) constructs the customized topology that process the parallel flow of data in order with the availability of the input data. The topology effectively increases the performance due to the clustering phenomena. The algorithm greatly reduces the latency period which is the significant of the topology and increases the throughput. The objectives of the research in the reduction of transmission rate and energy utilization are tested with different multimedia benchmark applications. The transmission rate reduced to average of 41.39% while average of energy consumption reduced to 31.9%.

In this paper the Advanced Encryption Standard (AES) was endorsed by the National Institute of Standards and Technology in 2001. It was intended to supplant the maturing Data Encryption Standard (DES) and be valuable for a wide scope of utilizations with differing throughput, zone, control dissemination and vitality utilization necessities .Though they are very adaptable, FPGAs are regularly less effective than Application Specific Integrated Circuits (ASICs); There have been numerous AES executions that attention on acquiring high throughput or low region use, however almost no examination done in the territory of low power or vitality productive based AES; actually, it is uncommon for assessments on power dispersal to be made by any means. This postulation introduces new effective equipment usage to those propelled encryption standard (AES) calculation. Two primary commitments are introduced in this thesis, the initial you quit offering on that one will be a secondary speed 128 odds AES encrypted, and the second person is another 32 odds AES configuration. In 1st commitment An 128 odds circle unrolled sub-pipelined AES encrypted is exhibited. In this encrypted a effective blending to those encryption methodology sub-steps will be executed following relocating them. Those second commitment displays An 32 odds AES plan. In this design, the S-BOX is actualized for inward pipelining Furthermore it is imparted the middle of those principle round and the enter development units. Also, the way development unit is actualized will fill in on the fly What's more previously, parallel with the fundamental round unit. These outlines bring attained higher FPGA (Throughput/Area) effectiveness analyzing to past AES outlines.