Relevant bibliographies by topics / Data processors

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
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Academic literature on the topic 'Data processors'

Author: Grafiati
Published: 4 June 2021
Last updated: 17 February 2022

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Journal articles on the topic "Data processors"

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Burnett, Rachel. "Data controllers and data processors." ITNOW 47, no. 5 (September 1, 2005): 34. http://dx.doi.org/10.1093/itnow/bwi108.

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Sinharoy, Balaram. "Compiler Optimization to Improve Data Locality for Processor Multithreading." Scientific Programming 7, no. 1 (1999): 21–37. http://dx.doi.org/10.1155/1999/235625.

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Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle), processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effectively reduces the cache size available to each individual thread. Increased processor utilization and the increase in the cache miss rate demands higher memory bandwidth. A novel compiler optimization method has been presented in this paper that improves data locality for each of the threads and enhances data sharing among the threads. The method is based on loop transformation theory and optimizes both spatial and temporal data locality. The created threads exhibit high level of intra‐thread and inter‐thread data locality which effectively reduces both the data cache miss rates and the total execution time of numerically intensive computation running on a multithreaded processor.
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ZIMAN, MÁRIO, and VLADIMÍR BUŽEK. "REALIZATION OF UNITARY MAPS VIA PROBABILISTIC PROGRAMMABLE QUANTUM PROCESSORS." International Journal of Quantum Information 01, no. 04 (December 2003): 527–41. http://dx.doi.org/10.1142/s0219749903000401.

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We analyze probabilistic realizations of programmable quantum processors that allow us to realize unitary operations on qubits as well as on qudits. Programmable processors are composed of two inputs — the data register and the program register. In the input state of the program register information about the operation that is supposed to be performed on the data is encoded. At the output of the probabilistic processor a measurement over the program register is performed. An intrinsic property of probabilistic processors is that they sometimes fail, but we know when this happens. We present a complete analysis of two processors: (1) The so-called [Formula: see text] processor that is based on a simple controlled-NOT gate. (2) The so-called [Formula: see text] processor that utilizes the quantum-information-distributor circuit.
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BRUCK, JEHOSHUA, and CHING-TIEN HO. "EFFICIENT GLOBAL COMBINE OPERATIONS IN MULTI-PORT MESSAGE-PASSING SYSTEMS." Parallel Processing Letters 03, no. 04 (December 1993): 335–46. http://dx.doi.org/10.1142/s012962649300037x.

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We present a class of efficient algorithms for global combine operations in k-port message-passing systems. In the k-port communication model, in each communication round, a processor can send data to k other processors and simultaneously receive data from k other processors. We consider algorithms for global combine operations in n processors with respect to a commutative and associative reduction function. Initially, each processor holds a vector of m data items and finally the result of the reduction function over the n vectors of data items, which is also a vector of m data items, is known to all n processors. We present three efficient algorithms that employ various trade-offs between the number of communication rounds and the number of data items transferred in sequence. For the case m=1, we have an algorithm which is optimal in both the number of communication rounds and the number of data items transferred in sequence.
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Suh, Ilhyun, and Yon Dohn Chung. "A Workload Assignment Strategy for Efficient ROLAP Data Cube Computation in Distributed Systems." International Journal of Data Warehousing and Mining 12, no. 3 (July 2016): 51–71. http://dx.doi.org/10.4018/ijdwm.2016070104.

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Data cube plays a key role in the analysis of multidimensional data. Nowadays, the explosive growth of multidimensional data has made distributed solutions important for data cube computation. Among the architectures for distributed processing, the shared-nothing architecture is known to have the best scalability. However, frequent and massive network communication among the processors can be a performance bottleneck in shared-nothing distributed processing. Therefore, suppressing the amount of data transmission among the processors can be an effective strategy for improving overall performance. In addition, dividing the workload and distributing them evenly to the processors is important. In this paper, the authors present a distributed algorithm for data cube computation that can be adopted in shared-nothing systems. The proposed algorithm gains efficiency by adopting the workload assignment strategy that reduces the total network cost and allocates the workload evenly to each processor, simultaneously.
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Barnard, Richard C., Kai Huang, and Cory Hauck. "A mathematical model of asynchronous data flow in parallel computers*." IMA Journal of Applied Mathematics 85, no. 6 (September 25, 2020): 865–91. http://dx.doi.org/10.1093/imamat/hxaa031.

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Abstract We present a simplified model of data flow on processors in a high-performance computing framework involving computations necessitating inter-processor communications. From this ordinary differential model, we take its asymptotic limit, resulting in a model which treats the computer as a continuum of processors and data flow as an Eulerian fluid governed by a conservation law. We derive a Hamilton–Jacobi equation associated with this conservation law for which the existence and uniqueness of solutions can be proven. We then present the results of numerical experiments for both discrete and continuum models; these show a qualitative agreement between the two and the effect of variations in the computing environment’s processing capabilities on the progress of the modelled computation.
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Molyakov, Andrey. "Main Scientific and Technological Problems in the Field of Architectural Solutions for Supercomputers." Computer and Information Science 13, no. 3 (July 24, 2020): 89. http://dx.doi.org/10.5539/cis.v13n3p89.

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In this paper author describes creation of a domestic accelerator processor capable of replacing NVIDIA GPGPU graphics processors for solving scientific and technical problems and other tasks requiring high performance, but which are characterized by good or medium localization of the processed data. Moreover, this paper illustrates creation of a domestic processor or processors for solving the problems of creating information systems for processing big data, as well as tasks of artificial intelligence (deep learning, graph processing and others). Therefore, these processors are characterized by intensive irregular work with memory (poor and extremely poor localization of data), while requiring high energy efficiency. The author points out the need for a systematic approach, training of young specialists on supporting innovative research.
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Aasaraai, Kaveh, and Andreas Moshovos. "NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution." International Journal of Reconfigurable Computing 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/915178.

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Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies. Instead, these processors use non-blocking caches to extract memory level parallelism and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. NCOR does not require CAMs and utilizes smart cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic elements.
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DEHNE, FRANK, and HAMIDREZA ZABOLI. "PARALLEL CONSTRUCTION OF DATA CUBES ON MULTI-CORE MULTI-DISK PLATFORMS." Parallel Processing Letters 23, no. 01 (March 2013): 1350002. http://dx.doi.org/10.1142/s0129626413500023.

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On-line Analytical Processing (OLAP) has become one of the most powerful and prominent technologies for knowledge discovery in VLDB (Very Large Database) environments. Central to the OLAP paradigm is the data cube, a multi dimensional hierarchy of aggregate values that provides a rich analytical model for decision support. Various sequential algorithms for the efficient generation of the data cube have appeared in the literature. However, given the size of contemporary data warehousing repositories, multi-processor solutions are crucial for the massive computational demands of current and future OLAP systems. In this paper we discuss the development of MCMD-CUBE, a new parallel data cube construction method for multi-core processors with multiple disks. We present experimental results for a Sandy Bridge multi-core processor with four parallel disks. Our experiments indicate that MCMD-CUBE achieves very close to linear speedup. A critical part of our MCMD-CUBE method is parallel sorting. We developed a new parallel sorting method termed MCMD-SORT for multi-core processors with multiple disks which outperforms other previous methods.
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Plantin, Jean-Christophe. "The data archive as factory: Alienation and resistance of data processors." Big Data & Society 8, no. 1 (January 2021): 205395172110075. http://dx.doi.org/10.1177/20539517211007510.

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Archival data processing consists of cleaning and formatting data between the moment a dataset is deposited and its publication on the archive’s website. In this article, I approach data processing by combining scholarship on invisible labor in knowledge infrastructures with a Marxian framework and show the relevance of considering data processing as factory labor. Using this perspective to analyze ethnographic data collected during a six-month participatory observation at a U.S. data archive, I generate a taxonomy of the forms of alienation that data processing generates, but also the types of resistance that processors develop, across four categories: routine, speed, skill, and meaning. This synthetic approach demonstrates, first, that data processing reproduces typical forms of factory worker’s alienation: processors are asked to work along a strict standardized pipeline, at a fast pace, without acquiring substantive skills or having a meaningful involvement in their work. It reveals, second, how data processors resist the alienating nature of this workflow by developing multiple tactics along the same four categories. Seen through this dual lens, data processors are therefore not only invisible workers, but also factory workers who follow and subvert a workflow organized as an assembly line. I conclude by proposing a four-step framework to better value the social contribution of data workers beyond the archive.
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Dissertations / Theses on the topic "Data processors"

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Chen, Tien-Fu. "Data prefetching for high-performance processors /." Thesis, Connect to this title online; UW restricted, 1993. http://hdl.handle.net/1773/6871.

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García, Almiñana Jordi. "Automatic data distribution for massively parallel processors." Doctoral thesis, Universitat Politècnica de Catalunya, 1997. http://hdl.handle.net/10803/5981.

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Massively Parallel Processor systems provide the required computational power to solve most large scale High Performance Computing applications. Machines with physically distributed memory allow a cost-effective way to achieve this performance, however, these systems are very diffcult to program and tune. In a distributed-memory organization each processor has direct access to its local memory, and indirect access to the remote memories of other processors. But the cost of accessing a local memory location can be more than one order of magnitude faster than accessing a remote memory location. In these systems, the choice of a good data distribution strategy can dramatically improve performance, although different parts of the data distribution problem have been proved to be NP-complete.
The selection of an optimal data placement depends on the program structure, the program's data sizes, the compiler capabilities, and some characteristics of the target machine. In addition, there is often a trade-off between minimizing interprocessor data movement and load balancing on processors. Automatic data distribution tools can assist the programmer in the selection of a good data layout strategy. These use to be source-to-source tools which annotate the original program with data distribution directives.
Crucial aspects such as data movement, parallelism, and load balance have to be taken into consideration in a unified way to efficiently solve the data distribution problem.
In this thesis a framework for automatic data distribution is presented, in the context of a parallelizing environment for massive parallel processor (MPP) systems. The applications considered for parallelization are usually regular problems, in which data structures are dense arrays. The data mapping strategy generated is optimal for a given problem size and target MPP architecture, according to our current cost and compilation model.
A single data structure, named Communication-Parallelism Graph (CPG), that holds symbolic information related to data movement and parallelism inherent in the whole program, is the core of our approach. This data structure allows the estimation of the data movement and parallelism effects of any data distribution strategy supported by our model. Assuming that some program characteristics have been obtained by profiling and that some specific target machine features have been provided, the symbolic information included in the CPG can be replaced by constant values expressed in seconds representing data movement time overhead and saving time due to parallelization. The CPG is then used to model a minimal path problem which is solved by a general purpose linear 0-1 integer programming solver. Linear programming techniques guarantees that the solution provided is optimal, and it is highly effcient to solve this kind of problems.
The data mapping capabilities provided by the tool includes alignment of the arrays, one or two-dimensional distribution with BLOCK or CYCLIC fashion, a set of remapping actions to be performed between phases if profitable, plus the parallelization strategy associated.
The effects of control flow statements between phases are taken into account in order to improve the accuracy of the model. The novelty of the approach resides in handling all stages of the data distribution problem, that traditionally have been treated in several independent phases, in a single step, and providing an optimal solution according to our model.
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Agarwal, Virat. "Algorithm design on multicore processors for massive-data analysis." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34839.

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Analyzing massive-data sets and streams is computationally very challenging. Data sets in systems biology, network analysis and security use network abstraction to construct large-scale graphs. Graph algorithms such as traversal and search are memory-intensive and typically require very little computation, with access patterns that are irregular and fine-grained. The increasing streaming data rates in various domains such as security, mining, and finance leaves algorithm designers with only a handful of clock cycles (with current general purpose computing technology) to process every incoming byte of data in-core at real-time. This along with increasing complexity of mining patterns and other analytics puts further pressure on already high computational requirement. Processing streaming data in finance comes with an additional constraint to process at low latency, that restricts the algorithm to use common techniques such as batching to obtain high throughput. The primary contributions of this dissertation are the design of novel parallel data analysis algorithms for graph traversal on large-scale graphs, pattern recognition and keyword scanning on massive streaming data, financial market data feed processing and analytics, and data transformation, that capture the machine-independent aspects, to guarantee portability with performance to future processors, with high performance implementations on multicore processors that embed processorspecific optimizations. Our breadth first search graph traversal algorithm demonstrates a capability to process massive graphs with billions of vertices and edges on commodity multicore processors at rates that are competitive with supercomputing results in the recent literature. We also present high performance scalable keyword scanning on streaming data using novel automata compression algorithm, a model of computation based on small software content addressable memories (CAMs) and a unique data layout that forces data re-use and minimizes memory traffic. Using a high-level algorithmic approach to process financial feeds we present a solution that decodes and normalizes option market data at rates an order of magnitude more than the current needs of the market, yet portable and flexible to other feeds in this domain. In this dissertation we discuss in detail algorithm design challenges to process massive-data and present solutions and techniques that we believe can be used and extended to solve future research problems in this domain.
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Dreibelbis, Harold N., Dennis Kelsch, and Larry James. "REAL-TIME TELEMETRY DATA PROCESSING and LARGE SCALE PROCESSORS." International Foundation for Telemetering, 1991. http://hdl.handle.net/10150/612912.

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International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada
Real-time data processing of telemetry data has evolved from a highly centralized single large scale computer system to multiple mini-computers or super mini-computers tied together in a loosely coupled distributed network. Each mini-computer or super mini-computer essentially performing a single function in the real-time processing sequence of events. The reasons in the past for this evolution are many and varied. This paper will review some of the more significant factors in that evolution and will present some alternatives to a fully distributed mini-computer network that appear to offer significant real-time data processing advantages.
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Bartlett, Viv A. "Exploiting data dependencies in low power asynchronous VLSI signal processors." Thesis, University of Westminster, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252037.

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Revuelta, Fernández Borja. "Study of Scalable Architectures on FPGA for Space Data Processors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254909.

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Spacecrafts are notably complex systems designed and constructed in multidisciplinary teams. The on-board computer of a spacecraft is part of the on-board data systems in charge of the on-board processing and handling of payload data collected from the instruments, which require high-performance radiationhardened-by-design (RHBD) processing devices. Over the last decades, the demand of high-performance systems used as on-board payload data processing systems has been increasing steadily due to new mission requirements, such as flexibility, faster development time, and new applications. At the same time, this user trend creates a need for higher performance components operating in radiation environments. The architecture proposed in this thesis is motivated by the results of recent activities supported by the European Space Agency (ESA) in the fields of Network-on-Chips (NoC) and floating-point VLIW Digital Signal Processors (DSPs). This architecture aims to study scaling aspects of VLIW-enable DSP SoC designs using FPGAs. The project shall perform the necessary pre-study activities required for the SoC design, such as synthesis of the IPs on the target FPGA technology. Lastly, using several DSPs for processing, a LEON3 processor for control, and several components from the GRLIB IP Library, the architecture implemented provides the user an with early version of a platform for further software development on multi-DSP platforms. Also, this architecture consists on a quad-core DSP system, providing a high-performance platform.
Satelliter och rymdfarkoster är komplexa system som utvecklas av tvärvetenskapliga designteam. I ombordsystemen är omborddatorn ansvarig för processering och hantering av vetenskaplig data från nyttolasterna, och kräver strålningstoleranta processorer med hög prestanda. Under de senaste årtiondena har efterfrågan på högpresterande system för omborddatabehandling ökat stadigt på grund av nya uppdragskrav, såsom ökad flexibilitet, snabbare utvecklingstid och nya applikationer. Av samma anledningar har efterfrågan för strålningstoleranta processorkomponenter med ännu högra prestanda ökat med liknande takt. I den här mastersavhandlingen föreslås en arkitektur som är motiverad av aktiviteter med stöd av ESA (den Europeiska rymdorganisationen) inom nätverk i integrerade kretsar (“Network-On-Chip”, NoC) och signalprocessorer (“DSP”, Digital Signal Processor) med flyttalsstöd. Den föreslagna arkitekturen avses vara lämplig för att användas till att undersöka skalering av komplex kretsdesign av integrerade system (“System-on-Chip”, SoC) med signalprocessorer, m.h.a. FPGA-teknologi. Slutligen, genom att använda flera dedikerade processorer för signalbehandling, en LEON3-processor för kontroll, och flera komponenter från GRLIB-biblioteket, ges det möjlighet för en potentiell avändare att göra mjukvarutester på ett flerkärnigt inbyggt processorsystem. Arkitekturen har designats med ett fyrkärnigt signalprocesserings system, vilket anses ge en hög prestanda.
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Mullins, Robert D. "Dynamic instruction scheduling and data forwarding in asynchronous superscalar processors." Thesis, University of Edinburgh, 2001. http://hdl.handle.net/1842/12701.

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Improvements in semiconductor technology have supported an exponential growth in microprocessor performance for many years. The ability to continue on this trend throughout the current decade poses serious challenges as feature sizes enter the deep sub-micron range. The problems due to increasing power consumption, clock distribution and the growing complexity of both design and verification, may soon limit the extent to which the underlying technological advances may be exploited. One approach which may ease these problems is the adoption of an asynchronous design style - one in which the global clock signal is omitted. Commonly-cited advantages include: the ability to exploit local variations in processing speed, the absence of a clock signal and its distribution network, and the ease of reuse and composability provided through the use of delay-insensitive module interfaces. While the techniques to design such circuits have matured over the past decade, studies of the impact of asynchrony of processor architecture have been less common. One challenge in particular is to develop multiple-issue architectures that are able to fully exploit asynchronous operation. Multiple-issue architectures have traditionally exploited the determinism and predictability ensured by synchronous operation. Unfortunately, this limits the effectiveness of the architecture when the clock is removed. The work presented in this dissertation describes in detail the problems of exploiting asynchrony in the design of superscalar processors. A number of techniques are presented for implementing both data forwarding and dynamic scheduling mechanisms, techniques that are central to exploiting instruction-level parallelism and achieving high-performance. A technique called instruction compounding is introduced, which appends dependency information to instructions during compilation, which can be exploited at run-time. This simplifies the implementation of both the dynamic scheduling and data-forwarding mechanisms.
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Åström, Fransson Donny. "Utilizing Multicore Processors with Streamed Data Parallel Applications for Mobile Platforms." Thesis, KTH, Elektronik- och datorsystem, ECS, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-125822.

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Performance has always been a major concern among computers and microprocessors. So have the qualities of the applications that are executed by these processors. When the multicore evolution began, programmers faced a shift in programming paradigms required to utilize the full potential of these processors. Now that the same evolution has reached the market of mobile devices, the developers focusing on mobile platforms are facing the same challenge. This thesis focuses on assessing some of the possible application quality gains that can be achieved by adopting parallel programming techniques for mobile platforms. In particular, throughput performance, low-latency performance and power consumption. A Proof of Concept application was developed to measure these specific qualities using a streamed data parallel approach. By adopting proper parallel programming techniques to utilize the multicore processor architecture, it was possible to achieve 90% better throughput performance or the same latency quality with 60% lower CPU frequency. Unfortunately, the power consumption could not be accurately measured using the available hardware.
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Duric, Milovan. "Specialization and reconfiguration of lightweight mobile processors for data-parallel applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2016. http://hdl.handle.net/10803/386568.

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The worldwide utilization of mobile devices makes the segment of low power mobile processors leading in the entire computer industry. Customers demand low-cost, high-performance and energy-efficient mobile devices, which execute sophisticated mobile applications such as multimedia and 3D games. State-of-the-art mobile devices already utilize chip multiprocessors (CMP) with dedicated accelerators that exploit data-level parallelism (DLP) in these applications. Such heterogeneous system design enable the mobile processors to deliver the desired performance and efficiency. The heterogeneity however increases the processors complexity and manufacturing cost when adding extra special-purpose hardware for the accelerators. In this thesis, we propose new hardware techniques that leverage the available resources of a mobile CMP to achieve cost-effective acceleration of DLP workloads. Our techniques are inspired by classic vector architectures and the latest reconfigurable architectures, which both achieve high power efficiency when running DLP workloads. The high requirement of additional resources for these two architectures limits their applicability beyond high-performance computers. To achieve their advantages in mobile devices, we propose techniques that: 1) specialize the lightweight mobile cores for classic vector execution of DLP workloads; 2) dynamically tune the number of cores for the specialized execution; and 3) reconfigure a bulk of the existing general purpose execution resources into a compute hardware accelerator. Specialization enables one or more cores to process configurable large vector operands with new special purpose vector instructions. Reconfiguration goes one step further and allow the compute hardware in mobile cores to dynamically implement the entire functionality of diverse compute algorithms. The proposed specialization and reconfiguration techniques are applicable to a diverse range of general purpose processors available in mobile devices nowadays. However, we chose to implement and evaluate them on a lightweight processor based on the Explicit Data Graph Execution architecture, which we find promising for the research of low-power processors. The implemented techniques improve the mobile processor performance and the efficiency on its existing general purpose resources. The processor with enabled specialization/reconfiguration techniques efficiently exploits DLP without the extra cost of special-purpose accelerators.
La utilización de dispositivos móviles a nivel mundial hace que el segmento de procesadores móviles de bajo consumo lidere la industria de computación. Los clientes piden dispositivos móviles de bajo coste, alto rendimiento y bajo consumo, que ejecuten aplicaciones móviles sofisticadas, tales como multimedia y juegos 3D.Los dispositivos móviles más avanzados utilizan chips con multiprocesadores (CMP) con aceleradores dedicados que explotan el paralelismo a nivel de datos (DLP) en estas aplicaciones. Tal diseño de sistemas heterogéneos permite a los procesadores móviles ofrecer el rendimiento y la eficiencia deseada. La heterogeneidad sin embargo aumenta la complejidad y el coste de fabricación de los procesadores al agregar hardware de propósito específico adicional para implementar los aceleradores. En esta tesis se proponen nuevas técnicas de hardware que aprovechan los recursos disponibles en un CMP móvil para lograr una aceleración con bajo coste de las aplicaciones con DLP. Nuestras técnicas están inspiradas por los procesadores vectoriales clásicos y por las recientes arquitecturas reconfigurables, pues ambas logran alta eficiencia en potencia al ejecutar cargas de trabajo DLP. Pero la alta exigencia de recursos adicionales que estas dos arquitecturas necesitan, limita sus aplicabilidad más allá de las computadoras de alto rendimiento. Para lograr sus ventajas en dispositivos móviles, en esta tesis se proponen técnicas que: 1) especializan núcleos móviles ligeros para la ejecución vectorial clásica de cargas de trabajo DLP; 2) ajustan dinámicamente el número de núcleos de ejecución especializada; y 3) reconfiguran en bloque los recursos existentes de ejecución de propósito general en un acelerador hardware de computación. La especialización permite a uno o más núcleos procesar cantidades configurables de operandos vectoriales largos con nuevas instrucciones vectoriales. La reconfiguración da un paso más y permite que el hardware de cómputo en los núcleos móviles ejecute dinámicamente toda la funcionalidad de diversos algoritmos informáticos. Las técnicas de especialización y reconfiguración propuestas son aplicables a diversos procesadores de propósito general disponibles en los dispositivos móviles de hoy en día. Sin embargo, en esta tesis se ha optado por implementarlas y evaluarlas en un procesador ligero basado en la arquitectura "Explicit Data Graph Execution", que encontramos prometedora para la investigación de procesadores de baja potencia. Las técnicas aplicadas mejoraran el rendimiento del procesador móvil y la eficiencia energética de sus recursos para propósito general ya existentes. El procesador con técnicas de especialización/reconfiguración habilitadas explota eficientemente el DLP sin el coste adicional de los aceleradores de propósito especial.
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Picciau, Andrea. "Concurrency and data locality for sparse linear algebra on modern processors." Thesis, Imperial College London, 2017. http://hdl.handle.net/10044/1/58884.

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Graphics processing units (GPUs) are used as accelerators for algorithms in which the same instructions are carried out on different data. Algorithms for sparse linear algebra can achieve good performance on GPU, although they tend to have an irregular pattern of accesses to memory. The performance of these algorithms is highly dependent on input data. In fact, the parallelism these algorithms can achieve is limited by the opportunities for concurrency given by the data. Focusing on the solution of sparse riangular linear systems of equations, this thesis shows that a good partitioning of the data and a good scheduling of the computation can greatly improve performance on GPUs. For this class of algorithms, a partition of the data that maximises concurrency in the execution does not necessarily achieve the best performance. Instead, improving data locality by reducing concurrency reduces the latency of memory access and consequently the execution time. First, this work characterises the problem formally using graph theory and performance models. Then, algorithms that can be used effectively to partition the data are described. These algoritms aim to balance concurrency and data locality automatically. This approach is evaluated experimentally on the solution of linear equations with the preconditioned conjugate gradient method. Also, the thesis shows that the proposed approach can be used in the case when a matrix changes during the execution of an algorithm from one iteration to the other, like in the simplex method. In this case, the approach proposed in this thesis allows to update the partition of the matrix from one iteration to the other. Finally, the algorithms and performance models developed in the thesis are used to discuss the limitations of the acceleration of the simplex method with GPUs.
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Books on the topic "Data processors"

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Data processors' survival guide to accounting. New York: J. Wiley, 1985.

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Incorporated, Advanced Micro Devices. Eight-bit 80C51 embedded processors data book. [Sunnyvale, CA]: Advanced Micro Devices, Inc., 1990.

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(Europe), NEC Electronics. 32-bit digital signal processors data book. Düsseldorf: NEC Electronics, 1993.

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(Europe), NEC Electronics. 24-bit digital signal processors data book. Düsseldorf: NEC Electronics, 1993.

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(Europe), NEC Electronics. Digital signal processors uPD77C25/77P25 data book. Düsseldorf: NEC Electronics, 1993.

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Inc, Xilinx. The programmable gate array data book. San Jose, Calif: XILINX, Inc., 1988.

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LaBarre, James E. Basic keyboarding skills for information processors. 2nd ed. Chicago: Science Research Associates, 1987.

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(Europe), NEC Electronics. 16-bit digital signal processors (uPD7720) data book. Düsseldorf: NEC Electronics, 1993.

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Semiconductors, ITT. TPU 3035, TPU 3040: Teletext processors : preliminary data sheet. Freiburg: ITT Semiconductors, 1996.

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Catthoor, Francky. Data Access and Storage Management for Embedded Programmable Processors. Boston, MA: Springer US, 2002.

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Book chapters on the topic "Data processors"

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Franklin, Manoj. "Multiscalar Processor—Register Data Flow." In Multiscalar Processors, 109–50. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-1039-0_6.

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Franklin, Manoj. "Multiscalar Processor—Memory Data Flow." In Multiscalar Processors, 151–78. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-1039-0_7.

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Helpenstein, Helmut J. "Development of Processors." In CAD Geometry Data Exchange Using STEP, 280–377. Berlin, Heidelberg: Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-642-78335-7_4.

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Reeves, Anthony P. "Languages for Parallel Processors." In Data Analysis in Astronomy II, 225–38. Boston, MA: Springer US, 1986. http://dx.doi.org/10.1007/978-1-4613-2249-8_22.

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Kim, See-Mu, and S. Manoharan. "Data Prefetching Using Dual Processors." In The Kluwer International Series in Engineering and Computer Science, 207–20. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-0849-6_15.

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Burggraf, H., and D. Rathjen. "Beamforming on Linear Antennas with Optical Processors." In Underwater Acoustic Data Processing, 307–12. Dordrecht: Springer Netherlands, 1989. http://dx.doi.org/10.1007/978-94-009-2289-1_34.

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Lambert, Paul B. "Outsourcing to Third-Party Data Processors." In Essential Introduction to Understanding European Data Protection Rules, 233–42. Boca Raton : CRC Press, 2017.: Auerbach Publications, 2017. http://dx.doi.org/10.1201/9781138069848-24.

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Lambert, Paul B. "Outsourcing to Third-Party Data Processors." In Essential Introduction to Understanding European Data Protection Rules, 233–42. Boca Raton : CRC Press, 2017.: Auerbach Publications, 2017. http://dx.doi.org/10.1201/9781315115269-24.

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Grabowski, H., and R. Glatz. "Testing and Validation of IGES Processors." In Product Data Interfaces in CAD/CAM Applications, 221–35. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-642-82426-5_20.

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Leupers, Rainer. "Register Allocation for DSP Data Paths." In Code Optimization Techniques for Embedded Processors, 59–79. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3169-9_3.

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Conference papers on the topic "Data processors"

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Juan, Toni, Juan J. Navarro, and Olivier Temam. "Data caches for superscalar processors." In the 11th international conference. New York, New York, USA: ACM Press, 1997. http://dx.doi.org/10.1145/263580.263595.

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Yu, Lina, and Hongfeng Yu. "Legion-based scientific data analytics on heterogeneous processors." In 2016 IEEE International Conference on Big Data (Big Data). IEEE, 2016. http://dx.doi.org/10.1109/bigdata.2016.7840863.

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Fischer, Lorenz, and Abraham Bernstein. "Workload scheduling in distributed stream processors using graph partitioning." In 2015 IEEE International Conference on Big Data (Big Data). IEEE, 2015. http://dx.doi.org/10.1109/bigdata.2015.7363749.

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Ortega, Cristobal, Victor Garcia, Miquel Moreto, Marc Casas, and Roxana Rusitoru. "Data Prefetching on In-order Processors." In 2018 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2018. http://dx.doi.org/10.1109/hpcs.2018.00061.

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Lo, Shi-Wu. "Data sharing protocols for SMT processors." In the 2006 ACM symposium. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1141277.1141485.

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Ellis, Kenneth, and Winser Alexander. "Block Data Processing Using Commercial Processors." In 1994 International Conference on Parallel Processing-Vol 1 (ICPP'94). IEEE, 1994. http://dx.doi.org/10.1109/icpp.1994.64.

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"Signal and data processors - Session 27." In Proceedings of the IEEE 2004 Custom Integrated Circuits Conference. IEEE, 2004. http://dx.doi.org/10.1109/cicc.2004.1358887.

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Ross, Kenneth A. "Efficient Hash Probes on Modern Processors." In 2007 IEEE 23rd International Conference on Data Engineering. IEEE, 2007. http://dx.doi.org/10.1109/icde.2007.368997.

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Dasari, Naga Shailaja, Ranjan Desh, and M. Zubair. "ParK: An efficient algorithm for k-core decomposition on multicore processors." In 2014 IEEE International Conference on Big Data (Big Data). IEEE, 2014. http://dx.doi.org/10.1109/bigdata.2014.7004366.

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Fort, Marta, J. Antoni Sellares, and Nacho Valladares. "Computing Popular Places Using Graphics Processors." In 2010 IEEE International Conference on Data Mining Workshops (ICDMW). IEEE, 2010. http://dx.doi.org/10.1109/icdmw.2010.45.

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Reports on the topic "Data processors"

1

Wheat, Jr., Robert Mitchell, Dale A. Dalmas, and Gregory E. Dale. A Four Channel Beam Current Monitor Data Acquisition System Using Embedded Processors. Office of Scientific and Technical Information (OSTI), August 2015. http://dx.doi.org/10.2172/1209457.

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Farhi, Edward, and Hartmut Neven. Classification with Quantum Neural Networks on Near Term Processors. Web of Open Science, December 2020. http://dx.doi.org/10.37686/qrl.v1i2.80.

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We introduce a quantum neural network, QNN, that can represent labeled data, classical or quantum, and be trained by supervised learning. The quantum circuit consists of a sequence of parameter dependent unitary transformations which acts on an input quantum state. For binary classification a single Pauli operator is measured on a designated readout qubit. The measured output is the quantum neural network’s predictor of the binary label of the input state. We show through classical simulation that parameters can be found that allow the QNN to learn to correctly distinguish the two data sets. We then discuss presenting the data as quantum superpositions of computational basis states corresponding to different label values. Here we show through simulation that learning is possible. We consider using our QNN to learn the label of a general quantum state. By example we show that this can be done. Our work is exploratory and relies on the classical simulation of small quantum systems. The QNN proposed here was designed with near-term quantum processors in mind. Therefore it will be possible to run this QNN on a near term gate model quantum computer where its power can be explored beyond what can be explored with simulation.
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Duque, Earl, Steve Legensky, Brad Whitlock, David Rogers, Andrew Bauer, Scott Imlay, David Thompson, and Seiji Tsutsumi. Summary of the SciTech 2020 Technical Panel on In Situ/In Transit Computational Environments for Visualization and Data Analysis. Engineer Research and Development Center (U.S.), June 2021. http://dx.doi.org/10.21079/11681/40887.

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At the AIAA SciTech 2020 conference, the Meshing, Visualization and Computational Environments Technical Committee hosted a special technical panel on In Situ/In Transit Computational Environments for Visualization and Data Analytics. The panel brought together leading experts from industry, software vendors, Department of Energy, Department of Defense and the Japan Aerospace Exploration Agency (JAXA). In situ and in transit methodologies enable Computational Fluid Dynamic (CFD) simulations to avoid the excessive overhead associated with data I/O at large scales especially as simulations scale to millions of processors. These methods either share the data analysis/visualization pipelines with the memory space of the solver or efficiently off load the workload to alternate processors. Using these methods, simulations can scale and have the promise of enabling the community to satisfy the Knowledge Extraction milestones as envisioned by the CFD Vision 2030 study for "on demand analysis/visualization of a 100 Billion point unsteady CFD simulation". This paper summarizes the presentations providing a discussion point of how the community can achieve the goals set forth in the CFD Vision 2030.
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Ruiz, Steven Adriel. Data Processor 3 QASPR Project. Office of Scientific and Technical Information (OSTI), November 2017. http://dx.doi.org/10.2172/1408803.

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Craig, Samuel. Passive Surveillance Data Processor/Analyzer. Fort Belvoir, VA: Defense Technical Information Center, March 1986. http://dx.doi.org/10.21236/ada169141.

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DYNAMICS RESEARCH CORP FAIRBORN OH. Processor and Data Bus Interface Analyses. Fort Belvoir, VA: Defense Technical Information Center, December 1987. http://dx.doi.org/10.21236/ada198801.

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Wong, Eugene, and Jean Walrand. Multidimensional Signals, Data and Processes. Fort Belvoir, VA: Defense Technical Information Center, May 1992. http://dx.doi.org/10.21236/ada255318.

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Wong, Eugene, and Jean Walrand. Multidimensional Signals, Data and Processes. Fort Belvoir, VA: Defense Technical Information Center, May 1992. http://dx.doi.org/10.21236/ada254797.

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Gimenes Rodrigues Albuquerque, Luiza. Data review processes in the analytical laboratory. Office of Scientific and Technical Information (OSTI), January 2020. http://dx.doi.org/10.2172/1634814.

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Bruce Ohme and Michael Johnson. Deep Trek Re-configurable Processor for Data Acquisition (RPDA). Office of Scientific and Technical Information (OSTI), June 2009. http://dx.doi.org/10.2172/982893.

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