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Dissertations / Theses on the topic 'Dataflow computation'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

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1

Lagercrantz, Erik. "Stencil Computation Auto-Tuning via Dataflow Graph Transformations." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-252358.

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Fine-tuning of optimizations such as loop tiling and array padding is typically required in order to achieve good performance in memory-intensive numerical applications on current computer architectures. Auto-tuning techniques can automate this traditionally laborious task and achieve good performance, but the techniques have so far been application-specific and difficult to adapt to new applications. This thesis investigates developing a framework and language supporting a more general purpose auto-tuner. A high level language capable of expressing programs that deal with multi-dimensional ar

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2

Gog, Ionel Corneliu. "Flexible and efficient computation in large data centres." Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/271804.

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Increasingly, online computer applications rely on large-scale data analyses to offer personalised and improved products. These large-scale analyses are performed on distributed data processing execution engines that run on thousands of networked machines housed within an individual data centre. These execution engines provide, to the programmer, the illusion of running data analysis workflows on a single machine, and offer programming interfaces that shield developers from the intricacies of implementing parallel, fault-tolerant computations. Many such execution engines exist, but they embed

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3

Bouakaz, Adnan. "Real-time scheduling of dataflow graphs." Phd thesis, Université Rennes 1, 2013. http://tel.archives-ouvertes.fr/tel-00945453.

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The ever-increasing functional and nonfunctional requirements in real-time safety-critical embedded systems call for new design flows that solve the specification, validation, and synthesis problems. Ensuring key properties, such as functional determinism and temporal predictability, has been the main objective of many embedded system design models. Dataflow models of computation (such as KPN, SDF, CSDF, etc.) are widely used to model stream-based embedded systems due to their inherent functional determinism. Since the introduction of the (C)SDF model, a considerable effort has been made to so

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4

Lesparre, Youen. "Evaluation de l'affectation des tâches sur une architecture à mémoire distribuée pour des modèles flot de données." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066086/document.

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Avec l'augmentation de l'utilisation des smartphones, des objets connectés et des véhicules automatiques, le domaine des systèmes embarqués est devenu omniprésent dans notre environnement. Ces systèmes sont souvent contraints en terme de consommation et de taille. L'utilisation des processeurs many-cores dans des systèmes embarqués permet une conception rapide tout en respectant des contraintes temps-réels et en conservant une consommation énergétique basse.Exécuter une application sur un processeur many-core requiert un dispatching des tâches appelé problème de mapping et est connu comme étan

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5

Moreews, François. "Concevoir et partager des workflows d’analyse de données : application aux traitements intensifs en bioinformatique." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S089/document.

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Dans le cadre d'une démarche d'Open science, nous nous intéressons aux systèmes de gestion de workflows (WfMS) scientifiques et à leurs applications pour l'analyse de données intensive en bioinformatique. Nous partons de l'hypothèse que les WfMS peuvent évoluer pour devenir des plates-formes pivots capables d'accélérer la mise au point et la diffusion de méthodes d'analyses innovantes. Elles pourraient capter et fédérer autour d'une thématique disciplinaire non seulement le public actuel des consommateurs de services mais aussi celui des producteurs de services. Pour cela, nous considérons que

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6

SAU, CARLO. "Dataflow based design suite for the development and management of multi-functional reconfigurable systems." Doctoral thesis, Università degli Studi di Cagliari, 2016. http://hdl.handle.net/11584/266751.

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Embedded systems development constitutes an extremely challenging scenario for the designers since several constraints have to be meet at the same time. Flexibil- ity, performance and power efficiency are typically colliding requirements that are hardly addressed together. Reconfigurable systems provide a valuable alternative to common architectures to challenge contemporarily all those issues. Such a kind of systems, and in particular the coarse grained ones, exhibit a certain level of flexi- bility while guaranteeing strong performance. However they suffer of an increased design and manageme

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7

Deroui, Hamza. "Etude et implantation d'algorithmes pour le placement et l'ordonnancement d'applications Dataflow." Thesis, Rennes, INSA, 2019. http://www.theses.fr/2019ISAR0022.

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La complexité des architectures MPSoC (Multiprocessor System-on-Chip) augmente de manière exponentielle pour répondre à la demande croissante en puissance de calcul des applications DSP (Digital Signal Processor). Les architectures MPSoC modernes, telles que les architectures à coeurs multiple, incorporent déjà des centaines d’éléments de traitement (PE) dans une seule puce et prévoient d’intégrer jusqu’à un millier de PE dans un avenir proche. Conséquemment, la programmation des architectures MPSoC modernes avec les langages de programmation traditionnels basés sur des threads est devenue de

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8

Sultan, Ziad. "Algèbre linéaire exacte, parallèle, adaptative et générique." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM030/document.

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Les décompositions en matrices triangulaires sont une brique de base fondamentale en calcul algébrique. Ils sont utilisés pour résoudre des systèmes linéaires et calculer le rang, le déterminant, l'espace nul ou les profiles de rang en ligne et en colonne d'une matrix. Le projet de cette thèse est de développer des implantations hautes performances parallèles de l'élimination de Gauss exact sur des machines à mémoire partagée.Dans le but d'abstraire le code de l'environnement de calcul parallèle utilisé, un langage dédié PALADIn (Parallel Algebraic Linear Algebra Dedicated Interface) a été imp

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9

Lesparre, Youen. "Evaluation de l'affectation des tâches sur une architecture à mémoire distribuée pour des modèles flot de données." Electronic Thesis or Diss., Paris 6, 2017. http://www.theses.fr/2017PA066086.

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Avec l'augmentation de l'utilisation des smartphones, des objets connectés et des véhicules automatiques, le domaine des systèmes embarqués est devenu omniprésent dans notre environnement. Ces systèmes sont souvent contraints en terme de consommation et de taille. L'utilisation des processeurs many-cores dans des systèmes embarqués permet une conception rapide tout en respectant des contraintes temps-réels et en conservant une consommation énergétique basse.Exécuter une application sur un processeur many-core requiert un dispatching des tâches appelé problème de mapping et est connu comme étan

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10

Tucker, Roy Colin. "Visualisation Studio for the analysis of massive datasets." Thesis, University of Plymouth, 2016. http://hdl.handle.net/10026.1/4870.

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This thesis describes the research underpinning and the development of a cross platform application for the analysis of simultaneously recorded multi-dimensional spike trains. These spike trains are believed to carry the neural code that encodes information in a biological brain. A number of statistical methods already exist to analyse the temporal relationships between the spike trains. Historically, hundreds of spike trains have been simultaneously recorded, however as a result of technological advances recording capability has increased. The analysis of thousands of simultaneously recorded

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11

Alvarez, Gustavo Adolfo Patiño. "Caracterização analítica de carga de trabalho baseada em cenários de aplicações multimídia." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26072013-171107/.

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As metodologias clássicas de análise de desempenho de sistemas sobre silício (System on chip, SoC) geralmente são descritas em função do tempo de execução do pior-caso1 das tarefas a serem executadas. No entanto, nas aplicações do mundo real, o tempo de execução destas tarefas pode variar devido à presença dos diferentes eventos de entrada que ativam o sistema, colocando uma exigência diferente de execução sobre os recursos do sistema. Geralmente, um modelo da carga de trabalho é uma parte integrante de um modelo de desempenho utilizado para avaliar o desempenho de um sistema. O quão bom for u

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12

Bengtsson, Jerker. "Models and Methods for Development of DSP Applications on Manycore Processors." Doctoral thesis, Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-14706.

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Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we

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13

Bush, V. J. "Recursion transformations for run-time control of parallel computations." Thesis, University of Manchester, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382888.

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14

Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embed

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15

Spertus, Ellen. "Dataflow Computation for the J-Machine." 1990. http://hdl.handle.net/1721.1/7030.

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The dataflow model of computation exposes and exploits parallelism in programs without requiring programmer annotation; however, instruction- level dataflow is too fine-grained to be efficient on general-purpose processors. A popular solution is to develop a "hybrid'' model of computation where regions of dataflow graphs are combined into sequential blocks of code. I have implemented such a system to allow the J-Machine to run Id programs, leaving exposed a high amount of parallelism --- such as among loop iterations. I describe this system and provide an analysis of its strengths

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16

Chien-TzuKuang and 匡建慈. "An Integrated Development Environment for Cloud Computation with Dataflow Programming Model." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/67482837768418238474.

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碩士<br>國立成功大學<br>資訊工程學系碩博士班<br>101<br>With the progress of information technology, computing-intensive and data-intensive applications sprang up like mushrooms. Because of the demand, multi-core processor architecture, cluster computing, and parallel computing on graphical processor unit were developed to provide enormous computing power. Moreover, because of facility charge of super computer or extra hardware devices, cloud computing service and cloud integrated environment became an emerging trend. What you have to do is to connect to internet and to utilize the service provided by cloud syst

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17

Varadarajan, Keshavan. "A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution." Thesis, 2012. https://etd.iisc.ac.in/handle/2005/2302.

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A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)). These units communicate directly, viz. send-receive like primitives, as opposed to the shared memory based communication used in multi-core processors. CGRAs are a well-researched topic and the design space of a CGRA is quite large. The design space can be represented as a 7-tuple (C, N, T, P, O, M, H) where each of the terms have the following meaning: C -choice of computation unit, N -

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18

Varadarajan, Keshavan. "A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2302.

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A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)). These units communicate directly, viz. send-receive like primitives, as opposed to the shared memory based communication used in multi-core processors. CGRAs are a well-researched topic and the design space of a CGRA is quite large. The design space can be represented as a 7-tuple (C, N, T, P, O, M, H) where each of the terms have the following meaning: C -choice of computation unit, N -

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19

Alle, Mythri. "Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm." Thesis, 2012. https://etd.iisc.ac.in/handle/2005/2453.

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Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabric is limited by the size of instruction buffers associated with each Compute element. When an application cannot be accommodated entirely, application is partitioned such that each of these partitions c

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20

Alle, Mythri. "Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2453.

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Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabric is limited by the size of instruction buffers associated with each Compute element. When an application cannot be accommodated entirely, application is partitioned such that each of these partitions c

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21

Chun-Wei, Liu, and 劉俊偉. "Using dataflow computation chart of Petri net theory and modified fuzzy analytic network process (ANP) for application to analysis on innovation process of LED standing/desk lamp and establishment of the related knowledgebase." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/63127574601010413335.

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碩士<br>國立臺灣科技大學<br>機械工程系<br>102<br>The paper uses the functions of process loop and mathematical model possessed by Petri net theory, which is a graphical model serving as a tool for dynamic simulation and analysis. Modified fuzzy analytic network process (ANP) selects procedures for the best plan, constructs Petri net dataflow computation chart, and establishes innovation process hybrid cloud and innovation process structure for LED standing/desk lamp. As for Modified fuzzy ANP theory, through the technique of patent keywords, and focusing on three techniques of LED standing/desk lamp to be

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22

Goens, Jokisch Andres Wilhelm. "Improving Model-Based Software Synthesis: A Focus on Mathematical Structures." 2021. https://tud.qucosa.de/id/qucosa%3A74884.

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Computer hardware keeps increasing in complexity. Software design needs to keep up with this. The right models and abstractions empower developers to leverage the novelties of modern hardware. This thesis deals primarily with Models of Computation, as a basis for software design, in a family of methods called software synthesis. We focus on Kahn Process Networks and dataﬂow applications as abstractions, both for programming and for deriving an eﬃcient execution on heterogeneous multicores. The latter we accomplish by exploring the design space of possible mappings of computation and data to ha

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