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Dissertations / Theses on the topic 'DCR Direct Conversion Receiver'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Emira, Ahmed Ahmed Eladawy. "Bluetooth/WLAN receiver design methodology and IC implementations." Texas A&M University, 2003. http://hdl.handle.net/1969.1/49.

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Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the s

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2

SOHAL, KARAN. "Design of Wideband Direct-Conversion Receiver for 5G Wireless Applications." Doctoral thesis, Università degli studi di Pavia, 2022. http://hdl.handle.net/11571/1454405.

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This thesis presents the design of a wideband direct-conversion receiver in 28nm CMOS technology as part of the heterogeneous transceiver for 5G wireless applications. The receiver down-converts the RF signal from the 7 GHz IF frequency to baseband. One of the key challenges for the receiver is the wide baseband bandwidth in the order of GHz, which makes the design of the receiver's baseband section particularly demanding. Furthermore, as the number of bands and antennas (MIMO) increases, the number of external RF filters must be reduced, which imposes strict linearity requirements since the r

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3

Erixon, Mats. "Design of a Direct-conversion Radio Receiver Front-end in CMOS Technology." Thesis, Linköping University, Department of Science and Technology, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1197.

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<p>In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. </p><p>Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakag

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4

Chen, Minghui. "Multiple Gb/s DQPSK direct-conversion baseband receiver for 60-GHz communications." Diss., Restricted to subscribing institutions, 2007. http://proquest.umi.com/pqdweb?did=1375535621&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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5

Kouchev, Ilian. "Design of a highly linear direct-conversion receiver for third-generation mobile communications /." Konstanz : Hartung-Gorre, 2006. http://www.loc.gov/catdir/toc/fy0707/2007358988.html.

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Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16687.<br>Summary in German and English, text in English. Includes bibliographical references (p. 175-180).

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6

Matinpour, Babak. "Development of a compact monolithic direct down-conversion microwave receiver for wireless applications." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13721.

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7

Hu, Anqiao. "Multi-modulus divider in fractional-N frequency synthesizer for direct conversion DVB-H receiver." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1196105249.

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Hu, Anqiao. "Multi-modulus divider in fractional-N frequency synthesizer for direct conversion DVB-H receiver." The Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=osu1196105249.

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9

Upadhyaya, Parag. "High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver." Online access for everyone, 2005. http://www.dissertations.wsu.edu/Thesis/Spring2005/p%5Fupadhyaya%5F050505.pdf.

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10

Sheng, Xiaoqin. "RF Mixer Design for Zero IF Wi-Fi Receiver in CMOS." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2771.

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<p>In this thesis work, a design of RF down-conversion mixer for WLAN standard, such as Wi-Fi or Bluetooth is presented. The target technology is 0.35um CMOS process. Several mixer topologies are analyzed and simulated at the schematic level using the Cadence Spectre-RF software. The active double balanced mixer is chosen for the ultimate implementation. For this mixer simulation results from schematic level to layout level are presented and discussed in detail. </p><p>To build an RF front-end, the complete mixer is integrated with an available LNA block. The performance of the front-end is ev

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11

Park, Jinsung. "A highly linear and low flicker-noise CMOS direct conversion receiver front-end for multiband applications." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07092007-054701/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Dr. Chang-Ho Lee, Committee Member ; Dr . Kevin T Kornegay, Committee Member ; Dr. Emmanouil M Tentzeris, Committee Member ; Dr. Joy Laskar, Committee Chair ; Dr. Oliver Brand, Committee Member.

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12

Alam, Shaikh Md Khairul. "A CMOS front end for high linearity zero-if WCDMA receiver." The Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=osu1164834218.

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13

Park, Seok-Bae. "Compact high performance analog CMOS baseband design solutions for multistandard wireless transceivers." Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1149024229.

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14

Cordova, Vivas David Javier. "Design of CMOS active downconversion mixers for gigahertz multi-band and multiple-standard operation." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/117761.

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Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e can

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Gerzaguet, Robin. "Méthodes de traitement numérique du signal pour l'annulation d'auto-interférences dans un terminal mobile." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GRENT014/document.

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Les émetteurs-récepteurs actuels tendent à devenir multi-standards c’est-àdireque plusieurs standards de communication peuvent cohabiter sur la même puce. Lespuces sont donc amenées à traiter des signaux de formes très différentes, et les composantsanalogiques subissent des contraintes de conception de plus en plus fortes associées au supportdes différentes normes. Les auto-interférences, c’est à dire les interférences généréespar le système lui-même, sont donc de plus en plus présentes, et de plus en plus problématiquesdans les architectures actuelles. Ces travaux s’inscrivent dans le paradig

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Hung, Chi-Shiun, and 洪啟訓. "Performance Evaluation of UWB-OFDM System with Direct Conversion Receiver (DCR) influenced by the LO frequency offset." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/71863581948768624137.

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碩士<br>南台科技大學<br>電子工程系<br>95<br>The UWB standard committee (802.13 task group 3a) stipulated that Direct Sequence CDMA or multi-band OFDM may be adopted as the transmission technology in 2003. In this thesis, we focus on the UWB multi-band OFDM (MB-OFDM) with RF band of 3 to5 GHz, and evaluate the influence of the frequency offset by simulation using MATLAB. In which, direct conversion receiver (DCR) is adopts as the receiver architecture. DCR will become popular since the problem of image is circumvented and no image filter is required. However, this approach suffers form some impacts such as

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Chin, mu-chun, and 覃木春. "Performance Evaluation of UWB DS-CDMA System with Direct Conversion Receiver (DCR) influenced by the LO frequency offset." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/28936076926840912673.

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碩士<br>南台科技大學<br>電子工程系<br>95<br>Ultra-wideband (UWB) communication technology has the characteristics of low-cost, low power consumption and high-speed data transmission. In recent years, UWB technology has developed into two major systems. One is Orthogonal Frequency Division Multiplexing (OFDM) system which is led by Intel, and the other is Direct Sequence Code Division Multiple Access (DS-CDMA) system which is supported by Motorola. This thesis presents the influence of frequency offset in the DS-CDMA system by simulation using MATLAB program. In the simulation, the Radio Frequency (RF) ba

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Hsieh, Jian-Yu, and 謝建宇. "A Direct Conversion Receiver for IEEE 802.11a." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/33815608715016619937.

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碩士<br>國立中正大學<br>電機工程所<br>95<br>This thesis develops a 5.25GHz direct conversion receiver for IEEE 802.11a by using TSMC CMOS 0.18μm process. The receiver includes high linearity and low power low noise amplifier (LNA), variable gain even harmonic mixer, low phase noise and low power voltage controlled oscillator (VCO) and power divider. High linearity and low power are the issues for the proposed receiver. In the thesis, we use complete theoretical analyses to assist circuit design and to discuss the relation of gain, linearity, power dissipation, transistor sizes and biased voltage. Make the

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Liu, Hsien-Fong, and 劉先鳳. "Direct Conversion Receiver Design for 2.4GHz WLAN." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/42178285098578811688.

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碩士<br>國立交通大學<br>電子工程系<br>87<br>For the trend of system on chip, direct conversion front end, which possesses highly integration properties, attracts prosperous researches especially with silicon solution. The major design challenges are the DC offset and even-order distortion and flick noise as discussed mainly in most literatures In this thesis, the architecture of direct conversion receiver for 2.4Ghz WLAN is proposed. To convey the major drawbacks of the direct conversion such as DC offset and linearity demand, four types of mixers have been derived and been designed under CMOS 0

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Chang, Po-Yu, and 張伯宇. "Front-End Design of UWB Direct-Conversion Receiver." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/36686227406582456223.

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碩士<br>國立清華大學<br>電機工程學系<br>97<br>The target of this research is to design and implement an ultra-wideband (UWB) direct-conversion receiver front-end occupied a small area with good performance to cost down. We have designed and implemented an UWB low noise amplifier (LNA), a wideband passive mixer and a UWB receiver front-end with compact sizes. The LNA was implemented in TSMC 0.13 μm CMOS technology and based on the resistive-feedback architecture with bandwidth extension by gate inductive- peaking. The gate inductor with only 0.4 nH is the only coil used in this circuit which extends the

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Chen, Chun-Hao, and 陳春豪. "Analog baseband circuit design for direct conversion receiver." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/17655369005105974293.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>91<br>This paper presents a circuit design and implantation for the analogous filter and amplifier sections of a direct conversion receiver. It is designed for 5GHz wireless LAN fabricated in a TSMC 0.35-µm SiGe BiCMOS technology. The design includes a first order low pass channel selection filter, a fifth order Butterworth filter, two stage programmable gain amplifiers (PGA), dc offset cancellation circuit, and a PTAT current source. The Gm-C channel selection filter can be programmable to two differ

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Chean, Kee, and 紀震. "LNA and Limiter Circuit Design for Direct Conversion Receiver." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/04693974373236650479.

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碩士<br>國立交通大學<br>電信工程系所<br>93<br>These major topics of the thesis are Low Noise Amplifier（LNA） of the front-end direct conversion receiver and Limiting Amplifier in front of demodulation, and applying TSMC CMOS 0.25um and 0.18um process, respectively. Utilized the results of TSMC 0.25um process RF CMOS Testkey and design the inductive degeneration LNA. The implemented chip is composed of LNA and Mixer, and the S11 is about -15.8dB, gain is about 3dB at converting frequency 500kHz, which RF frequency is 868MHz, and the noise figure is about 19.4dB at 10MHz. Following, the implemented chip made u

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Hsu, Chia-Hao, and 許家豪. "Direct RF to Digital Conversion for Monolithic mQAM Receiver." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/18036764957225357812.

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碩士<br>崑山科技大學<br>電子工程研究所<br>98<br>We propose a direct conversion, called RF2D, from the RF signal modulated by mQAM to digital code for low power, small area, and monolithic receiver realization. A differential Wilson current mirror undertakes saturation amplifier cooperating with a current mode phase detector, a D flip-flop clocking with carrier frequency, converts the RF signal to serial digital pulses whose widths are the phases of the original mQAM baseband signal. Then, high-speed counters based on TSPC, evaluate the widths to digital counts. The association of a digital count and amplitud

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Huang, Chih-Yung, and 黃智勇. "Design of 3.5-GHz CMOS Even-Harmonic Direct Conversion Receiver." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/49580738334958666035.

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碩士<br>國立中正大學<br>電機工程所<br>97<br>Abstract In this thesis CMOS direct-conversion even-harmonic mixers and receiver are presented. First, a 3.5-GHz even-harmonic mixer with low LO driving power was designed. Under a -6 dBm LO power driving, the measured voltage conversion gain is 14.9 dB for 3.5 GHz RF signal and 10 MHz IF output. The input P1dB is -11.6 dBm, input IP3 is -1.18 dBm, and input IP2 is -4.14 dBm. The power consumption is 5.96 mW and the chip size is 0.56 mm2. The second even-harmonic CMOS mixer was particularly incorporated with an autonomy DC-offset compensation circuit to reduce th

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"Medical Implant Receiver System." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.16040.

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abstract: The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This enables both control of the implant as well as relay of information collected. This research has focused on a high performance receiver for medical implant applications. One commonly quoted specification to compare receivers is energy per bit required. T

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Hao-ChunChang and 張皓鈞. "Carrier Frequency Offset Estimation in Direct Conversion Receiver Systems Using ESPRIT." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/zjy6p9.

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碩士<br>國立成功大學<br>電腦與通信工程研究所<br>106<br>Carrier frequency offset (CFO) and frequency-dependent I/Q imbalance (FD IQI) are well-known non-ideal effects of the broad band direct conversion receivers. The former may cause phase rotation of the received signals, and the latter results in image frequency interference on signal spectrum. Both of them significantly degrade the error rate of the receiver. Most of the CFO estimation techniques in the literature do not consider the effect of FD IQI, resulting in inaccurate CFO estimation. In the thesis, we consider CFO estimation in the presence of FD IQI.

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YDING and 丁彥. "DESIGN OF LOW VOLTAGE 5-GHz CMOS DIRECT-CONVERSION FRONT-END RECEIVER." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/93941482612086639133.

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碩士<br>國立交通大學<br>電機資訊學院碩士在職專班<br>92<br>Wireless local network is a fast growing market that enables lower power dissipation and higher data rates. The IEEE 802.11a standard which channel 0 is useless among 52 sub-carriers; this is favorable for direct-conversion architecture. This thesis proposes a CMOS direct-conversion receiver, and is realized by TSMC 0.18μm technology via Chip Implementation Center. The major issue in the direct-conversion architecture is self-mixing problem; a new offset compensation circuit is used as the mixer loads to alleviate the DC offset. The receiver comprises a lo

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Chen, Po-Chia, and 陳柏嘉. "A CMOS RF FRONT-END DESIGN FOR 2.4 GHz DIRECT CONVERSION RECEIVER." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/27876038886139651644.

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碩士<br>大同大學<br>電機工程研究所<br>89<br>This thesis presents the design of a monolithic 2.4GHz RF front-end for the direct conversion receiver with 0.35um tsmc CMOS digital process. The direct conversion receiver including an LNA (Low Noise Amplifier), a mixer, and a VCO (Voltage-Controlled Oscillator) is well known as a simple, convenient, and highly integrated communication system. The LNA is designed as differential one with gain 12 dB, NF (Noise Figure) 1.7dB, P1dB (1dB input compression point) -12 dBm, IIP3 (Input third order interception point) —10 dBm, and 55 mW power consumption (with output bu

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Syu, Jin-Siang, and 徐金詳. "CMOS Flicker Noise Solutions by Low-IF Receiver Architecture and Deep-N-Well BJT Direct-Conversion Receiver." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/34899975266856641406.

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博士<br>國立交通大學<br>電信工程研究所<br>99<br>This dissertation consists of five chapters, including performance improvements of various mixer topologies and receivers. Chapter 2 introduces single-/dual-band highly linear Gilbert upconverters. The difference of OIP¬3 and OP1dB, widely used as a criterion for mixer linearity, is over 22 dB by using an input bias-offset cross-coupled pair and output shunt-shunt feedback buffer amplifier. In Chapter 3, passive quadrature signal generators are deeply discussed, including amplitude/phase relations by using phasor analyses. Further, a bipolar-juncion- transistor

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Chen, Jehchuen, and 陳界錞. "Studies on Mixer and Channel Select Filter for ISM Band Direct Conversion Receiver." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/21499940715594495562.

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Chang, SSu-Wei, and 張斯緯. "Research on 3-5-GHz CMOS RFICs for UWB Direct-Conversion Receiver Application." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/04425970275120036683.

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碩士<br>國立成功大學<br>電腦與通信工程研究所<br>94<br>This thesis presents the research on front-end RFICs of direct-conversion for DS-UWB receiver, including of two broad-band double-balanced mixers, a broad-band transmitting amplifier and a broad-band front-end chip all applied at UWB low band. The front-end chip includes a broad-band differential LNA and a broad-band double-balanced mixer. The chips are fabricated by a TSMC standard 0.18-μm CMOS process. The circuit measurements are performed by using a FR-4 PCB test fixture except for the transmitting amplifier chip. The first mixer chip uses charge-injecti

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Lee, Tsonrng-Lin, and 李宗霖. "A 5-GHz Direct Conversion Receiver with I/Q Phase and Gain Error Calibration." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/34459555270625541941.

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碩士<br>國立交通大學<br>電子工程系所<br>93<br>Wireless Local Area Networks (WLANs) based on IEEE 802.11a and HIPER LAN have drawn transceiver research efforts and turn widely deployed in recent years. With the coming of soc era, a low cost RF transceiver is in strong demand. For wide band wireless transceiver direct conversion architecture is a superior candidate for fewer external required components, thus low cost design goal can be achieved. This activates the research of this work. This thesis describes the design of a 5GHz, variable gain, and direct conversion receiver for wireless LNA application. The

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Chuang, Ge-Wei, and 莊格瑋. "Direct Conversion Receiver Using Active Bandpass Filter for Channel Select and Characterization of RF Device." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/18268788394087470275.

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碩士<br>國立交通大學<br>電信工程研究所<br>102<br>This thesis focuses on the application of wireless communication network, using the TSMC 0.18um CMOS process designs to achieve the RF circuits. It is divided into two parts. The first part is active filter and its application to 5GHz channel select receiver. The second part is the characteristic measurement of RF device. The RF components contain Schottky diode and two kinds of bipolar transistors─SiGe HBT and CMOS Vertical-npn BJT. In the chapter 2, we discuss the design method of high sideband rejection bandpass filter and the technique of Q-enhancement. Th

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Yi-Kai, Lo, and 羅怡凱. "The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/69474282197457527021.

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碩士<br>國立交通大學<br>電子工程系所<br>95<br>As the increasing demands for low-power and high data-rate wireless communication, conventional wireless local area network of IEEE 802.11 a/b/g has found it difficult to suffice these requirements. In this thesis, the design methodology and implementation of a 3.1~10.6 GHz direct-conversion receiver for UWB application are presented according to the recently published IEEE 802.15.3a specification. The proposed direct-conversion receiver are composed of a new wideband low-noise amplifier (WLNA) used to receive 3.1~10.6 GHz signal simultaneously and a carrier gen

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Sekyiamah, Charles Prof. "Design Of A 20MHz Transimpedance Amplifier With Embedded Low-pass Filter For A Direct Conversion Wireless Receiver." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-9815.

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Accelerated growth in wireless communications in recent years has led to the emergence of portable devices that employ several wireless communication standards to provide multiple functionality such as cellular communication, wireless data communication and connectivity, entertainment and navigation, within the same device. Industry drive is towards reduction of the number of radio frequency (RF) front-end receivers required to cater to the various standards/bands within a single device to reduce cost, size and power consumption. The current trend is to use broadband/multi-standard or recon

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Nien, Chia-Ying, and 粘家熒. "The Design of Sub-0.7V 5-GHz CMOS Direct-Conversion Receiver Front-End for Wireless LAN Applications." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/5c883n.

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碩士<br>國立交通大學<br>電子工程系所<br>94<br>A sub-0.7V 5-GHz direct-conversion receiver for low-power and wireless applications is proposed in this thesis. The receiver composed of a low-noise amplifier, a set of I/Q downconverters with a DC compensation circuit, and a quadrature voltage-controlled oscillator is realized in a 0.18-�慆 CMOS technology supported by Taiwan Semiconductor Manufacturing Company via Chip Implementation Center. The proposed receiver is completely designed, fabricated and tested. Measured results exhibit that the receiver can operate well under supply voltages of 0.65 V and 0.7

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林忠佑. "2.4/5.8GHz Low Noise Low Power Direct Conversion Receiver Utilizing Passive Mixer and HEMT Low Noise Amplifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/93534100106971471686.

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碩士<br>國立交通大學<br>電信工程研究所<br>98<br>In this thesis, we use TSMC CMOS 0.18μm and WIN 0.15μm to design the radio frequency circuits for network application. The thesis consists of two parts. The first part focus on two different design for the Direct Conversion Receiver. The second part compares different type LNA(Low Noise Amplifier) utilizing different process in different circuit type. First, we analyzes different Receiver type that we usually use today, and introduces flicker noise performance in passive mixer. We implement TSMC CMOS 0.18μm to design Receivers with passive mixer and two differe

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Hodgson, James K. "Design of a 10 MHz Transimpedance Low-Pass Filter with Sharp Roll-Off for a Direct Conversion Wireless Receiver." 2009. http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-266.

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A fully-differential base-band transimpedance low-pass filter is designed for use in a direct conversion wireless receiver. Existing base-band transimpedance amplifiers (TIA) often utilize single-pole filters which do not provide good stop-band rejection and may even allow the filter to saturate in the presence of large interferers near the edge of the pass-band. The designed filter is placed in parallel with an existing single-pole TIA filter and diverts stop-band current signals away from the existing filter, providing added rejection and safeguarding the filter from saturating. The presente

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Hsu, Yen-Huang, and 許炎煌. "Design of CMOS Inductorless Even-Harmonic Mixers and Octave-Phase Voltage-Controlled Oscillator for 3.5-GHz Direct Conversion Receiver." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/32825882058281485502.

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碩士<br>國立中正大學<br>電機工程所<br>96<br>CMOS even-harmonic mixers and octave-phase VCO are designed in this thesis for 3.5-GHz direct-conversion receiver. First, an inductorless even-harmonic mixer was deigned, which utilizes the low-impedance characteristic of MOS source node as the input port to overcome the impedance match difficulty when high-impedance gate node is conventionally used as the input port. Therefore, the input match can be easily achieved by properly selecting the MOS size without using any inductors in the match network and hence the chip size is dramatically reduced. The implemented

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Ou, Meng-Yueh, and 歐孟岳. "A Low-Voltage and Low-Power 2.4 GHz CMOS Direct-Conversion Receiver for Bio-Acquisition in Wireless Sensor Network." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/71452723754265650575.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>This work describes the design of a wireless receiver front-end circuit for Bio-Acquisition in Wireless Sensor Network (WSN). The front-end circuit includes a cascode low noise amplifier (LNA), an active balun and a folded-cascode even-harmonic mixer. The balun employs differential amplifier architecture utilizing the concept of RC feedback to transform single-ended signal into differential form. The frequency-doubling circuit in the LO stage is employed to double the LO frequency, thus the self-mixing resulted from LO leakage could be avoided. The even-harm

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Kim, Ju Sung. "Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10512.

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Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mi

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Forbes, Travis Michael 1986. "Circuit techniques for programmable broadband radio receivers." Thesis, 2013. http://hdl.handle.net/2152/28712.

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The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each st

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