Relevant bibliographies by topics / DDR SDRAM

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'DDR SDRAM'

Author: Grafiati
Published: 4 June 2021
Last updated: 26 July 2025

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Journal articles on the topic "DDR SDRAM"

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Wang, Shu Hai, Yuan Yuan Tian, and Shu Wang Chen. "DDR Memory Controller Design Based on FPGA." Advanced Materials Research 1049-1050 (October 2014): 779–82. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.779.

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With the rapid development of electronic science and computer science, the large scale integrated circuit applied in the military, economic and social life is more and more widely. Because the DDR SDRAM has twice the SDRAM memory data rate, now has been widely used. The DDR memory controller design for the DDR SDRAM and the connection between the FPGA provides a solution [3]. This paper analyzes the current international technology trends and storage controller DDR2 SDRAM controller detailed technical specifications. DDR2 SDRAM controller configuration based on register information units, with
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Mandavi, Katare*1 &. Ass. Pro. Ankit Chouhan2. "A REVIWE ARTICLE OF SDRAM DESIGN WITH NECESSORY CRITERIA OF DDR CONTROLLER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 6 (2017): 333–37. https://doi.org/10.5281/zenodo.809195.

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Double Data Rate Synchronous DRAM (DDR SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. The DDR SDRAM is an enhancement to the conventional SDRAM running at bus speed over 75MHz. The DDR SDRAM (referred to as DDR) doubles the bandwidth of the memory by transferring data twice per cycle on both the rising and falling edges of the clock signal. The designed DDR Controller supports data width of 64 bits, Burst Length of 4 and CAS (Column Address Strobe) latency of 2. DDR Controller provides a synchronous command interface to the DDR S
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Yan, Lu, and An Song Feng. "The Design of DDR-SDRAM Controller Based on Spartan3." Advanced Materials Research 468-471 (February 2012): 2455–58. http://dx.doi.org/10.4028/www.scientific.net/amr.468-471.2455.

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The controller of DDR-SDRAM was designed with Spartan 3 of Xilinx.The design of the controller is made of the initialized program for power on and read/write control program.The design that uses state machine designing method was realized by VHDL language .The design was verified by software simulation of modelsim first,then it was verified by the PCB.The result of test indicates that the design of the controller for DDR-SDRAM met the demand of design and realized the control of the read/write DDR-SDRAM.
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Agarwal, Aadhar. "Design and FPGA Implementation of DDR SDRAM Controller." International Journal for Research in Applied Science and Engineering Technology V, no. IV (2017): 1258–63. http://dx.doi.org/10.22214/ijraset.2017.4224.

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Volobuev, S. V., and V. G. Ryabtsev. "Interface Features of the DDR SDRAM Memory Test Diagnostic Device." Proceedings of Universities. Electronics 26, no. 3-4 (2021): 282–90. http://dx.doi.org/10.24151/1561-5405-2021-26-3-4-282-290.

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The I/О synchronization scheme plays an important role in achieving maximum speed and reliability of data transmission during memory operation. This paper presents the interface architecture of the DDR SDRAM test diagnostic device. It was demonstrated that the proposed interface components provide the formation of a bidirectional synchro signal for gating written and read data when performing test diagnostics of chips and DDR SDRAM memory devices. Compared to traditional methods, the proposed interface components were made on integrated electronic elements, which reduced the size and power con
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Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumpi
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Zeba, khan, and Vinod Kapse Dr. "DDR-SDRAM Controller ASIC Design for High Speed Interfacing." International Journal of Advanced and Innovative Research 7, no. 2 (2018): 46–50. https://doi.org/10.5281/zenodo.1184886.

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The goal of this work is to develop DRAM controller between Main Processor and the main memory for fast interfacing of the data and this is achieved with the help of a new Super Harvard type of interfacing parallel interfacing for the data, program data and instructions, also the proposed work used four stage pipelining to achieve high throughput and high speed interfacing. Vertex Corse grain FPGA has been used for the design of the work hence the area can be minimized also the mix modeling architecture is been used. The architecture is designed in Xilinx EDA using Verilog HDL and verification
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Ma, Ling, Ke Zhu Song, Jun Feng Yang, and Ping Cao. "Hardware Implementation of a Real-Time Data Processing Algorithm in Marine Engineering Data Acquisition." Advanced Materials Research 268-270 (July 2011): 110–15. http://dx.doi.org/10.4028/www.scientific.net/amr.268-270.110.

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According to the architecture characteristics of the mass data acquisition system in marine seismic exploration, this paper designed a real-time data processing algorithm which can convert the collected time-sequence data to channel-sequence data. A hardware implementation of the algorithm based on FPGA+DDR SDRAM is developed to complete the whole conversion process. Here, FPGA is used to achieve time sequence data receiving, analyzing, preliminary processing and the interface to DDR SDRAM. Two DDR SDRAM’s are used in ping-pang mode to store time-sequence data and to cooperate with FPGA in rea
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Klehn, B., and M. Brox. "A Comparison of current SDRAM types: SDR, DDR, and RDRAM." Advances in Radio Science 1 (May 5, 2003): 265–71. http://dx.doi.org/10.5194/ars-1-265-2003.

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Abstract. The ever increasing demand for bandwidth of computer-systems lead to several standards of SDRAMs. This article compares SDR, DDRI, DDRII, and RDRAM systems. Besides the overall basic innovations, differences will be discussed. Topics like architecture, interfaces, and modules are described.
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Rajesh, Gurram, K. Srinivasa Reddy, and U. Srinivasa Rao. "ASIC Design Methodology & Implementation of Double Data Rate (DDR) SDRAM Controller." IOSR Journal of Electronics and Communication Engineering 9, no. 4 (2014): 62–67. http://dx.doi.org/10.9790/2834-09446267.

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Dissertations / Theses on the topic "DDR SDRAM"

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Ferm, Daniel. "Design of a Gigabit Router Packet Buffer using DDR SDRAM Memory." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6148.

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<p>The computer engineering department at Linköping University has a research project which investigates the use of an on-chip network in a router. There has been an implementation of it in a FPGA and for this router there is a need for buffer memory. This thesis extends the router design with a DDR memory controller which uses the features provided by the Virtex-II FPGA family.</p><p>The thesis shows that by carefully scheduling the DDR SDRAM memory high volume transfers are possible and the memory can be used quite effciently despite its rather complex interface.</p><p>The DDR memory control
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Bonatto, Alexsandro Cristóvão. "Núcleos de interface de memória DDR SDRAM para sistemas-em-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/17291.

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Dispositivos integrados de sistemas-em-chip (SoC), especialmente aqueles dedicados às aplicações multimídia, processam grandes quantidades de dados armazenados em memórias. O desempenho das portas de memória afeta diretamente no desempenho do sistema. A melhor utilização do espaço de armazenamento de dados e a redução do custo e do consumo de potência dos sistemas eletrônicos encorajam o desenvolvimento de arquiteturas eficientes para controladores de memória. Essa melhoria deve ser alcançada tanto para interfaces com memórias internas quanto externas ao chip. Em sistemas de processamento de v
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Andreasson, Robert. "Design of an FPGA Based JTAG Recorder for use in Production of IPTV Set-Top Boxes." Thesis, Linköping University, Computer Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50504.

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<p>This thesis evaluates the possibility to replace the manufacturer dependent JTAG device used in the production tests of IPTV set-top boxes for storing the boot loader in the main memory in order to start the box for the first time. An FPGA based prototype was built in order to see if it is possible to record the JTAG signals, to an external DDR SDRAM, without understanding them and be able to perform a delayed playback resulting in the same bahavoir as with the original JTAG device.Overall the thesis was succesful and it shows that it is infact feasible to create a JTAG recorder based on an
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Heithecker, Sven. "Communication and memory scheduling in reconfigurable image processing systems." Berlin Dissertation.de, 2008. http://d-nb.info/994809271/04.

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Plesco, Alexandru. "Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2010. http://tel.archives-ouvertes.fr/tel-00544349.

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Une grande variété de produits vendus, notamment de télécommunication et multimédia, proposent des fonctionnalités de plus en plus avancées. Celles-ci induisent une augmentation de la complexité de conception. Pour satisfaire un budget de performance et de consommation d'énergie, ces fonctionnalités peuvent être accélérées par l'utilisation d'accélérateurs matériels dédiés. Pour respecter les délais nécessaires de mise sur le marché et le prix de développement, les méthodes traditionnelles de conception de matériel ne sont plus suffisantes et l'utilisation d'outils de synthèse de haut niveau (
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Lessinger, Samuel. "Proposta de uma plataforma reconfigurável para testes de módulos SDRAM DDR3." Universidade do Vale do Rio dos Sinos, 2017. http://www.repositorio.jesuita.org.br/handle/UNISINOS/6724.

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Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2017-10-25T13:48:51Z No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5)<br>Made available in DSpace on 2017-10-25T13:48:52Z (GMT). No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5) Previous issue date: 2017-09-21<br>PADIS - Programa de apoio ao desenvolvimento tecnológico da indústria de semicondutores<br>O presente trabalho consiste em uma proposta de uma plataforma reconfigurável para testes de módulos de memória SDRAM
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Herrmann, Martin [Verfasser]. "Radiation Characterization of Highly Integrated DDR3 SDRAM Devices for Spaceborne Mass Storage Applications / Martin Herrmann." München : Verlag Dr. Hut, 2018. http://d-nb.info/116853478X/34.

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Lodaya, Bhaveen. "On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory." Master's thesis, Universitätsbibliothek Chemnitz, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-233196.

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User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limi
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Trtílek, Jakub. "Přídavný paměťový modul pro vysokorychlostní kameru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318190.

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Goal of the diploma thesis is a design of fast memory module and to introduce myself with issues involved in data storage in memory of high speed camera. The work is concerned about two designs adding memory capacity of high speed camera with DDR3 memory modules. For production is selected the more suitable design that is better for commercial purposes. The main objective is to design a schematic with FPGA as a main controller, that will operate data flow from CMOS sensor to superior development board MicroZed. Final design should allow us to sell the high speed camera as a separate unit.
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Nouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.

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Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Pr
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Books on the topic "DDR SDRAM"

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Aiyappa, Rekha. Section 55. DDR SDRAM Controller. Microchip Technology Incorporated, 2017.

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Aiyappa, Rekha. Section 55. DDR SDRAM Controller. Microchip Technology Incorporated, 2016.

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Aiyappa, Rekha. Section 55. DDR SDRAM Controller FRM. Microchip Technology Incorporated, 2019.

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Yang, Ada. Section 55. DDR SDRAM Controller FRM. Microchip Technology Incorporated, 2019.

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Takenaka, Norio. PIC32 FRM, Section 55. DDR2 SDRAM Controller. Microchip Technology Incorporated, 2016.

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Dufseth, Rhonda. SAMA5D2 System in Package (SiP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM. Microchip Technology Incorporated, 2020.

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Anderson, Julie. SAMA5D2 System in Package (SiP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM Data Sheet. Microchip Technology Incorporated, 2018.

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Anderson, Julie. SAM9X60 System-In-Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM and up to 64 Mbits SDR-SDRAM. Microchip Technology Incorporated, 2019.

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Dufseth, Rhonda. SAM9X60 System-In-Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM and up to 64 Mbits SDR-SDRAM. Microchip Technology Incorporated, 2020.

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Book chapters on the topic "DDR SDRAM"

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Picatoste-Olloqui, Eduardo, Francisco Cardells-Tormo, Jordi Sempere-Agullo, and Atilà Herms-Berenguer. "Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_30.

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Zheng, Lim Zong, Mohd Tafir Mustaffa, and Ch’ng Siew Sin. "High-Speed Transmitter Designs for DDR3 SDRAM Memory Interfaces." In Lecture Notes in Electrical Engineering. Springer Singapore, 2014. http://dx.doi.org/10.1007/978-981-4585-42-2_42.

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HimaBindhu, J., B. Nagaveni, S. Kiran Kumar Reddy, V. Jyothi, and P. Konda Reddy. "Implementation of High Speed DDR3 SDRAM Memory Controller by Using XILINX Software." In Proceedings of the 6th International Conference on Communications and Cyber Physical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-7137-4_51.

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Nidagundi, Jayashree C. "Design of I/O Interface for DDR2 SDRAM Transmitter Using gpdk 180 nm Technology." In Communications in Computer and Information Science. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0404-1_16.

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Liu, Bingkun, Dashuai Wang, and Jianhua Liu. "Image Acquisition and Storage System of Binocular Camera Based on FPGA." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2023. http://dx.doi.org/10.3233/faia230859.

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In order to better solve the problem that image processing technology is strict in real-time and stability, a binocular camera image acquisition and storage system based on FPGA is designed with the advantage of FPGA parallel processing. The system uses Xilinx ARTIX-7 XC7A35T as the master chip to control the CMOS camera as the image sensor for image acquisition, stores the acquired images in DDR3 SDRAM, and displays the images in the host computer by reading the memory data. The results show that the system has good real-time performance and stability, and meets the requirements of image tran
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Conference papers on the topic "DDR SDRAM"

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Sachin and Santosh Kumar Gupta. "A Novel High Speed 2-Step TDC-Based All-Digital DLL for DDR SDRAM Applications." In 2024 4th International Conference on Sustainable Expert Systems (ICSES). IEEE, 2024. https://doi.org/10.1109/icses63445.2024.10763029.

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Ganesh, Chokkakula, SK Shoukath Vali, U. Vaibhava Reddy, Shaik Afreen, and Girija Sravani Kondavitee. "High-Performance ASIC Design for Pipelined DDR2 SDRAM Controllers." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012442.

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Kim, Woongki, Dongwoo Bae, Saqib Ali Khan, et al. "Effects of Proton and Gamma Radiation on DDR4 SDRAM in Elevated Temperature." In 2024 RADECS Data Workshop. IEEE, 2024. https://doi.org/10.1109/radecs61975.2024.11017557.

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Priyanka, Bojanki, B. Anil Kumar, and D. Suresh Kumar. "High Coverage DDR4 SDRAM Memory Design and Verification Using System Verilog and UVM." In 2024 2nd International Conference on Cyber Physical Systems, Power Electronics and Electric Vehicles (ICPEEV). IEEE, 2024. https://doi.org/10.1109/icpeev63032.2024.10931883.

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Sreehari, S., and Jaison Jacob. "AHB DDR SDRAM enhanced memory controller." In 2013 International Conference on Advanced Computing & Communication Systems (ICACCS). IEEE, 2013. http://dx.doi.org/10.1109/icaccs.2013.6938767.

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Makam, Darshan, and H. V. Jayashree. "An innovative design of the DDR/DDR2 SDRAM compatible controller." In International Conference on Nanoscience, Engineering and Technology (ICONSET 2011). IEEE, 2011. http://dx.doi.org/10.1109/iconset.2011.6168042.

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Bakshi, A., S. S. Pandey, T. Pradhan, and R. Dey. "ASIC implementation of DDR SDRAM Memory Controller." In 2013 International Conference on Emerging Trends in Computing, Communication and Nanotechnology (ICE-CCN). IEEE, 2013. http://dx.doi.org/10.1109/ice-ccn.2013.6528467.

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Xin Yang, Jun Mu, Sakir Sezer, John McCanny, and Earl Swartzlander. "High performance IP lookup circuit using DDR SDRAM." In 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641547.

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Siqueira, Hadley M., Ivan S. Silva, Marcio E. Kreutz, and Edgard F. Correa. "DDR SDRAM Memory Controller for Digital TV Decoders." In 2011 Brazilian Symposium on Computing System Engineering (SBESC). IEEE, 2011. http://dx.doi.org/10.1109/sbesc.2011.16.

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Reddy, N. Satish, Ganesh Chokkakula, Bhumarapu Devendra, and K. Sivasankaran. "ASIC implementation of high speed pipelined DDR SDRAM controller." In 2014 International Conference on Information Communication and Embedded Systems (ICICES). IEEE, 2014. http://dx.doi.org/10.1109/icices.2014.7033980.

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