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Dissertations / Theses on the topic 'DDR SDRAM'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Ferm, Daniel. "Design of a Gigabit Router Packet Buffer using DDR SDRAM Memory." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6148.

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<p>The computer engineering department at Linköping University has a research project which investigates the use of an on-chip network in a router. There has been an implementation of it in a FPGA and for this router there is a need for buffer memory. This thesis extends the router design with a DDR memory controller which uses the features provided by the Virtex-II FPGA family.</p><p>The thesis shows that by carefully scheduling the DDR SDRAM memory high volume transfers are possible and the memory can be used quite effciently despite its rather complex interface.</p><p>The DDR memory control

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2

Bonatto, Alexsandro Cristóvão. "Núcleos de interface de memória DDR SDRAM para sistemas-em-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/17291.

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Dispositivos integrados de sistemas-em-chip (SoC), especialmente aqueles dedicados às aplicações multimídia, processam grandes quantidades de dados armazenados em memórias. O desempenho das portas de memória afeta diretamente no desempenho do sistema. A melhor utilização do espaço de armazenamento de dados e a redução do custo e do consumo de potência dos sistemas eletrônicos encorajam o desenvolvimento de arquiteturas eficientes para controladores de memória. Essa melhoria deve ser alcançada tanto para interfaces com memórias internas quanto externas ao chip. Em sistemas de processamento de v

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3

Andreasson, Robert. "Design of an FPGA Based JTAG Recorder for use in Production of IPTV Set-Top Boxes." Thesis, Linköping University, Computer Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50504.

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<p>This thesis evaluates the possibility to replace the manufacturer dependent JTAG device used in the production tests of IPTV set-top boxes for storing the boot loader in the main memory in order to start the box for the first time. An FPGA based prototype was built in order to see if it is possible to record the JTAG signals, to an external DDR SDRAM, without understanding them and be able to perform a delayed playback resulting in the same bahavoir as with the original JTAG device.Overall the thesis was succesful and it shows that it is infact feasible to create a JTAG recorder based on an

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4

Heithecker, Sven. "Communication and memory scheduling in reconfigurable image processing systems." Berlin Dissertation.de, 2008. http://d-nb.info/994809271/04.

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5

Plesco, Alexandru. "Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2010. http://tel.archives-ouvertes.fr/tel-00544349.

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Une grande variété de produits vendus, notamment de télécommunication et multimédia, proposent des fonctionnalités de plus en plus avancées. Celles-ci induisent une augmentation de la complexité de conception. Pour satisfaire un budget de performance et de consommation d'énergie, ces fonctionnalités peuvent être accélérées par l'utilisation d'accélérateurs matériels dédiés. Pour respecter les délais nécessaires de mise sur le marché et le prix de développement, les méthodes traditionnelles de conception de matériel ne sont plus suffisantes et l'utilisation d'outils de synthèse de haut niveau (

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6

Lessinger, Samuel. "Proposta de uma plataforma reconfigurável para testes de módulos SDRAM DDR3." Universidade do Vale do Rio dos Sinos, 2017. http://www.repositorio.jesuita.org.br/handle/UNISINOS/6724.

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Submitted by JOSIANE SANTOS DE OLIVEIRA (josianeso) on 2017-10-25T13:48:51Z No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5)<br>Made available in DSpace on 2017-10-25T13:48:52Z (GMT). No. of bitstreams: 1 Samuel Lessinger_.pdf: 3503378 bytes, checksum: 92c0e6ccfb6dfb145bc9a84b3ce1ceed (MD5) Previous issue date: 2017-09-21<br>PADIS - Programa de apoio ao desenvolvimento tecnológico da indústria de semicondutores<br>O presente trabalho consiste em uma proposta de uma plataforma reconfigurável para testes de módulos de memória SDRAM

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7

Herrmann, Martin [Verfasser]. "Radiation Characterization of Highly Integrated DDR3 SDRAM Devices for Spaceborne Mass Storage Applications / Martin Herrmann." München : Verlag Dr. Hut, 2018. http://d-nb.info/116853478X/34.

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8

Lodaya, Bhaveen. "On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory." Master's thesis, Universitätsbibliothek Chemnitz, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-233196.

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User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limi

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9

Trtílek, Jakub. "Přídavný paměťový modul pro vysokorychlostní kameru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318190.

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Goal of the diploma thesis is a design of fast memory module and to introduce myself with issues involved in data storage in memory of high speed camera. The work is concerned about two designs adding memory capacity of high speed camera with DDR3 memory modules. For production is selected the more suitable design that is better for commercial purposes. The main objective is to design a schematic with FPGA as a main controller, that will operate data flow from CMOS sensor to superior development board MicroZed. Final design should allow us to sell the high speed camera as a separate unit.

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10

Nouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.

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Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Pr

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11

Hsieh, Shun-an, and 謝舜安. "THE CONTROLLER IP DESIGN OF MULTIPLE DATA ACCESS PORT FOR DDR SDRAM." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/12408988075884289355.

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碩士<br>大同大學<br>電機工程學系(所)<br>100<br>At first we introduce the electrical characteristic of the random access memory, including static random access memory（SRAM）and double data rate dynamic random access memory（DDR SDRAM）,and consider to construct a multiple data access port memory controller to DDR SDRAM devices. In order to implement the multiple data access port function to a single DDR SDRAM device, we use time division multiplexing technique and use a central arbiter to control the resource using scheduling. We also use a flexible weightighting parameter and priority code for those data ac

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12

Lin, I.-Fan, and 林依凡. "DDR SDRAM Buffer Management in Advanced TCA Based Load Balanced Birkhoff-von Neumann Switch." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/34517681733085147727.

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13

Mei, Szu-Kai, and 梅斯凱. "The Study of DDR3 SDRAM Bus Layout." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/20666066123702055538.

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碩士<br>健行科技大學<br>電子工程所<br>101<br>With the development of technology, DDR modules, with their important functions for accessing data memory, have been widely applied in the fields of computer, information, communication, consumer electronics, etc. When the processing speed of electronic products continues to improve, the need of haveing faster memory to process transmitted data makes the routing design between CPU and memory more difficult to be handled. Therefore, how to meet the increasingly demanding requirements of layout on circuit boards has become an important issue. This study focus

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14

Wu, Chien-Ting, and 吳建霆. "FPGA and DDR3 SDRAM Data Bus Layout Design." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23163275594909554902.

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碩士<br>清雲科技大學<br>電機工程所<br>100<br>Information and electronic products continue to improve the operation of the clock in order to enhance performance. This makes the design of the connection between the CPU and memory in the system more and more intractable. To improve performance, DDR3 addition to the faster bit rate (from 400Mbps up to 1.6 Gbps), the highest is also a lot of reform on the connection topology (from the T- topology into a Fly-by topology). Therefore, how to meet the increasingly stringent requirements to become an important issue in the circuit board layout. With the rapid increa

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15

Ming-Kong, Hong, and 洪銘冠. "The Design and Implementation of an AXI4-Compatible DDR4-SDRAM Controller." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/bajbpy.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>107<br>Abstract The increasing demand for speed and flexibility of functions, the clock frequency of memory is getting higher and higher. In addition, due to the trend of integrating various modules into an SoC (System-on-Chip), embedding an SDRAM controller is of importance an efficient way to drive the memory so as to achieve high performance. Since most SoC chips use the ARM Cortex microcontrollers, in this thesis we design and implement an SDRAM controller, which connects AMBA AXI4 and DDR4 SDRAM. The SDRAM controller is divided into four modules, including asyn

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16

LUNG, YEN-LIN, and 龍彥霖. "The Design and Implementation of an AXI4-Compatible DDR4-SDRAM Controller." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/jttm8m.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>107<br>In the era of more and more complex functions in SoC (System on Chip), the access to data is so huge that how to improve the access speed of the memory is an important issue. Although the clock of memory continues to increase, its access speed is still much lower than the processor speed. Therefore, to increase the performance of the SoC, it is necessary to improve the performance of memory access. For this reason, it is important to design an efficient memory controller. The ARM Cortex series of microcontrollers are widely used in SoC chips, so this thesis de

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17

Hsu, Kuo-Lun, and 徐國倫. "The Design and Implementation of an AXI3-Interface-Based DDR4-SDRAM Controller." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6r442n.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>106<br>With the advance of science and technology, the functionality of system-on-chip (SoC) has become more complex, and the performance is higher and higher, leading to the increasing demand of a large amount of memory. As a consequence, the large-capacity memory is indispensable to current SoCs. Unfortunately, the memory access speed is far below the processor’s speed and hence limits the performance of the system. Hence, to promote the performance of SoCs, it is necessary to design an efficient memory controller to coordinate the operations between the processor

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18

Chang, Keng-Hua, and 張耿華. "The Design and Implementation of an AXI4-Interface-Based DDR4-SDRAM Controller." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4yk5h6.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>106<br>With the maturity of SoC (System-on-Chip), the function of SoC is much complexity than before, thereby increasing the demand of large memory capacity. To reduce the system cost and increase the system design flexibility, the use of SDRAM is an essential option. As a consequence, the SDRAM controller has become an important module on most SoC chips. Because most SoCs adopt the ARM Cortex microcontrollers as their basic platforms, in this thesis we propose an SDRAM controller that is compatible with AMBA AXI4 and DDR4 SDRAM. The SDRAM controller consists of four

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19

Cheng, Yu-Liang, and 鄭宇良. "The Design and Implementation of a DDR4-SDRAM Controller Based on AHB5 Interface." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/kucuuw.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>106<br>Because the System-on-Chip (SoC) system has become more complicated than before, the need of large-capacity internal memory in SoCs is increasing. Therefore, SDRAM and its related controller are needed in SoCs . The architecture based on ARM architecture dominates the market. Hence, in this thesis, we design and implement an AMBA- AHB5-based dynamic memory controller. The dynamic memory controller contains three parts: the AHB5 interface, controller, and physical layer. This controller has three important features. First, it provides a portable user access int

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