Journal articles on the topic 'DDR SDRAM'
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Wang, Shu Hai, Yuan Yuan Tian, and Shu Wang Chen. "DDR Memory Controller Design Based on FPGA." Advanced Materials Research 1049-1050 (October 2014): 779–82. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.779.
Full textMandavi, Katare*1 &. Ass. Pro. Ankit Chouhan2. "A REVIWE ARTICLE OF SDRAM DESIGN WITH NECESSORY CRITERIA OF DDR CONTROLLER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 6 (2017): 333–37. https://doi.org/10.5281/zenodo.809195.
Full textYan, Lu, and An Song Feng. "The Design of DDR-SDRAM Controller Based on Spartan3." Advanced Materials Research 468-471 (February 2012): 2455–58. http://dx.doi.org/10.4028/www.scientific.net/amr.468-471.2455.
Full textAgarwal, Aadhar. "Design and FPGA Implementation of DDR SDRAM Controller." International Journal for Research in Applied Science and Engineering Technology V, no. IV (2017): 1258–63. http://dx.doi.org/10.22214/ijraset.2017.4224.
Full textVolobuev, S. V., and V. G. Ryabtsev. "Interface Features of the DDR SDRAM Memory Test Diagnostic Device." Proceedings of Universities. Electronics 26, no. 3-4 (2021): 282–90. http://dx.doi.org/10.24151/1561-5405-2021-26-3-4-282-290.
Full textMunaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.
Full textZeba, khan, and Vinod Kapse Dr. "DDR-SDRAM Controller ASIC Design for High Speed Interfacing." International Journal of Advanced and Innovative Research 7, no. 2 (2018): 46–50. https://doi.org/10.5281/zenodo.1184886.
Full textMa, Ling, Ke Zhu Song, Jun Feng Yang, and Ping Cao. "Hardware Implementation of a Real-Time Data Processing Algorithm in Marine Engineering Data Acquisition." Advanced Materials Research 268-270 (July 2011): 110–15. http://dx.doi.org/10.4028/www.scientific.net/amr.268-270.110.
Full textKlehn, B., and M. Brox. "A Comparison of current SDRAM types: SDR, DDR, and RDRAM." Advances in Radio Science 1 (May 5, 2003): 265–71. http://dx.doi.org/10.5194/ars-1-265-2003.
Full textRajesh, Gurram, K. Srinivasa Reddy, and U. Srinivasa Rao. "ASIC Design Methodology & Implementation of Double Data Rate (DDR) SDRAM Controller." IOSR Journal of Electronics and Communication Engineering 9, no. 4 (2014): 62–67. http://dx.doi.org/10.9790/2834-09446267.
Full textHamamoto, T., K. Furutani, T. Kubo, et al. "A 667-Mb/s Operating Digital DLL Architecture for 512-Mb DDR SDRAM." IEEE Journal of Solid-State Circuits 39, no. 1 (2004): 194–206. http://dx.doi.org/10.1109/jssc.2003.820851.
Full textLiu, Zhuorui, Yan Li, and Xiaoyang Zeng. "Low-Power-Management Engine: Driving DDR Towards Ultra-Efficient Operations." Micromachines 16, no. 5 (2025): 543. https://doi.org/10.3390/mi16050543.
Full textLiu, Zhuorui, Yan Li, and Xiaoyang Zeng. "ADPO: Adaptive DRAM Controller for Performance Optimization." Micromachines 16, no. 4 (2025): 409. https://doi.org/10.3390/mi16040409.
Full textKirihata, T., G. Mueller, B. Ji, et al. "A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture." IEEE Journal of Solid-State Circuits 34, no. 11 (1999): 1580–88. http://dx.doi.org/10.1109/4.799866.
Full textYamasaki, Nobuyuki. "Design Concept of Responsive Multithreaded Processor for Distributed Real-Time Control." Journal of Robotics and Mechatronics 16, no. 2 (2004): 194–99. http://dx.doi.org/10.20965/jrm.2004.p0194.
Full textBick, Konstantin, Duy Nguyen, Hyuk-Jae Lee, and Hyun Kim. "Fast and Accurate Memory Simulation by Integrating DRAMSim2 into McSimA+." Electronics 7, no. 8 (2018): 152. http://dx.doi.org/10.3390/electronics7080152.
Full textKuge, S., T. Kato, K. Furutani, et al. "A 0.18-/spl mu/m 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica." IEEE Journal of Solid-State Circuits 35, no. 11 (2000): 1680–89. http://dx.doi.org/10.1109/4.881215.
Full textChangsik Yoo, Kye-Hyun Kyung, Kyunam Lim, et al. "A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration." IEEE Journal of Solid-State Circuits 39, no. 6 (2004): 941–51. http://dx.doi.org/10.1109/jssc.2004.827806.
Full textRentería, Leonardo, Margarita Mayacela, Klever Torres, Wladimir Ramírez, Rolando Donoso, and Rodrigo Acosta. "FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits." Computation 12, no. 9 (2024): 174. http://dx.doi.org/10.3390/computation12090174.
Full textYamasaki, Nobuyuki. "Responsive Multithreaded Processor for Distributed Real-Time Systems." Journal of Robotics and Mechatronics 17, no. 2 (2005): 130–41. http://dx.doi.org/10.20965/jrm.2005.p0130.
Full textWu, Zhao Hua. "The Modeling and Prediction Study of BLP Device Solder Joint Three-Dimensional Shape." Applied Mechanics and Materials 121-126 (October 2011): 2338–42. http://dx.doi.org/10.4028/www.scientific.net/amm.121-126.2338.
Full textDr., K.C. Mahajan* Mukesh K. Yadav. "INTELLECTUAL PROPERTY CORE OF AXI MEMORY CONTROLLER FOR FPGA." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 12 (2016): 194–203. https://doi.org/10.5281/zenodo.192574.
Full textLima, Cayo Raphael da Rocha, and Elenildo Aquino dos Santos. "Ventilação mecânica como estratégia protetora nos pacientes com SDRA: Uma revisão integrativa." Research, Society and Development 13, no. 1 (2024): e13013144839. http://dx.doi.org/10.33448/rsd-v13i1.44839.
Full textYoung-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, et al. "A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs." IEEE Journal of Solid-State Circuits 39, no. 11 (2004): 2087–92. http://dx.doi.org/10.1109/jssc.2004.835809.
Full textMuttaqin, Adharul, Zainul Abidin, Raden Arief Setyawan, and Itsna Az Zahra. "Development of advanced automated test equipment for digital system by using FPGA." Indonesian Journal of Electrical Engineering and Computer Science 15, no. 2 (2019): 661. http://dx.doi.org/10.11591/ijeecs.v15.i2.pp661-670.
Full textRodríguez Blanco, José Antonio, Jesús Daniel Rodríguez Blanco, Jonathan José Rodríguez Blanco, María Cristina Martínez Ávila, María Camila Acuña Caballero, and Carlos Emilio Remolina. "Enfermedad bullosa como complicación pulmonar en la convalecencia de COVID-19." Revista Colombiana de Neumología 32, no. 2 (2021): 66–71. http://dx.doi.org/10.30789/rcneumologia.v32.n2.2020.536.
Full textSanto Cepeda, Kristopher Alexander, Mario Enrique Sayas Herazo, Mara del Carmen Guerra Jimenez, and Mateo Alejandro Rosero Estrella. "Síndrome de distres respiratorio agudo." RECIMUNDO 4, no. 3 (2020): 86–93. http://dx.doi.org/10.26820/recimundo/4.(3).julio.2020.86-93.
Full textFerreira da Silva, Deysianne, Keylla Talitha Fernandes Barbosa, Fabiana Maria Rodrigues Lopes de Oliveira, Maria Hellena Ferreira Brasil, and Yanne Jannine Gomes Araujo Morais. "Associação entre exames laboratoriais e mau prognóstico em pacientes infectados pelo novo coronavírus." Ciência ET Praxis 19, no. 34 (2024): 99–112. http://dx.doi.org/10.36704/cipraxis.v19i34.7314.
Full textT., Mladenov, Mujahid F., Jung E., and Har D. "Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller." June 23, 2008. https://doi.org/10.5281/zenodo.1075818.
Full textSridevi, P. "Design of an efficient and faster SDRAM Controller." International Journal of Advanced Research in Science and Technology, 2015, 298–301. http://dx.doi.org/10.62226/ijarst20150207.
Full textAqueel, Shabana, and Kavita Khare. "A High Performance DDR3 SDRAM Controller." International Journal of Electronics and Electical Engineering, July 2012, 1–4. http://dx.doi.org/10.47893/ijeee.2012.1001.
Full textVeena H. K and Dr. A. H. Masthan Ali. "Design and Implementation of High Speed DDR SDRAM Controller on FPGA." International Journal of Engineering Research and V4, no. 07 (2015). http://dx.doi.org/10.17577/ijertv4is070428.
Full text"Design of Low Voltage 1.8V, Wide Range 50∼500MHz Delay Locked Loop for DDR SDRAM." KIPS Transactions:PartA 10A, no. 3 (2003): 247–54. http://dx.doi.org/10.3745/kipsta.2003.10a.3.247.
Full textOlson, M. Ben, Brandon Kammerdiener, Michael R. Jantz, Kshitij A. Doshi, and Terry Jones. "Online Application Guidance for Heterogeneous Memory Systems." ACM Transactions on Architecture and Code Optimization, May 4, 2022. http://dx.doi.org/10.1145/3533855.
Full textJUYO HERNANDEZ, LAURA MILENA, and Wilder Andres Villamil. "Efectos de las maniobras de reclutamiento alveolar sobre el nivel de oxigenación en pacientes pediátricos bajo ventilación mecánica invasiva." Movimiento Científico 14, no. 1 (2020). http://dx.doi.org/10.33881/2011-7191.mct.14105.
Full textBwire, George M., Beatrice Godwin Aiko, Idda H. Mosha, et al. "High viral suppression and detection of dolutegravir-resistance associated mutations in treatment-experienced Tanzanian adults living with HIV-1 in Dar es Salaam." Scientific Reports 13, no. 1 (2023). http://dx.doi.org/10.1038/s41598-023-47795-1.
Full textArroyo, Manuel F., Salvador Abreo, Jaime Villa, Carlos Rebolledo, and Jorge Camacho. "Vena poplítea, un acceso alternativo para el inicio de hemodiálisis en pacientes en decúbito prono durante la pandemia de COVID-19." Revista Colombiana de Nefrología 11, no. 3 (2024). https://doi.org/10.22265/acnef.11.3.735.
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