Relevant bibliographies by topics / Deblocking filter

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Deblocking filter'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Deblocking filter"

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Norkin, Andrey, Gisle Bjontegaard, Arild Fuldseth, Matthias Narroschke, Masaru Ikeda, Kenneth Andersson, Minhua Zhou, and Geert Van der Auwera. "HEVC Deblocking Filter." IEEE Transactions on Circuits and Systems for Video Technology 22, no. 12 (December 2012): 1746–54. http://dx.doi.org/10.1109/tcsvt.2012.2223053.

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List, P., A. Joch, J. Lainema, G. Bjontegaard, and M. Karczewicz. "Adaptive deblocking filter." IEEE Transactions on Circuits and Systems for Video Technology 13, no. 7 (July 2003): 614–19. http://dx.doi.org/10.1109/tcsvt.2003.815175.

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Jia, Tao. "Multi-Standards Deblocking Filter Based SIMD Technology." Advanced Materials Research 791-793 (September 2013): 1501–5. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.1501.

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Due to real-time video decoding requirements, hardware accelerators for video deblocking filtering has gradually become a research hotspot in recent years. Compared with the traditional deblocking filter hardware accelerators which support only single video coding standard, this paper implemented a deblocking filter structure, which filtering algorithm can be configured to support multiple video coding standards; Using SIMD technology to make filtering data fully parallel computing. This structure is a multi-standard deblocking filter accelerator, supports H264, AVS, VP8 to, RealVideo, four kinds of video coding standards. The clock frequency is 200MHz, and it can be used for real-time filtering of multi-standard HD video processing. Deblocking Filter Algorithm
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Wang, Jin Tao, Yong Quan Lu, Chu Qiu, Peng Dong Gao, Jie Fu, and Wen Hua Yu. "Research on Setting Parameter of Deblocking Filter for H.264." Applied Mechanics and Materials 20-23 (January 2010): 70–75. http://dx.doi.org/10.4028/www.scientific.net/amm.20-23.70.

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The emerging coding standard H.264 is mainly intended for video transmission in many areas. Considering the peculiarity of blocking artifacts which results from block based transform using DCT (discrete cosine transform ) that is most popular method for video coding. These blocking which is due to deficiency of correlation between blocks has much troublesome impact at low bit rate encoding. In this paper, we analyzed the performance of common deblocking filter within H.264 standard, investigated the principle of parameter setting for deblocking filter in an open source code(x264). The outputs of deblocking filter depend on the boundary strength parameter “BS” and the gradient of image samples across the boundary [1]. Usually the filter parameters αc and β were specified a default value zero during x264 running, but in fact selecting different values have a significant effect in the view of image quality. The two statistical parameters of Gray Level co-occurrence Matrix (GLCM), energy and entropy, were used to evaluate the texture of each video picture, and then specify appropriate values for the filter parameters αc and β. We may appraise the effect of deblocking in terms of calculating Mean Squared Difference of Slope (MSDS) for each video frame. In the end of this paper, the experimental results show that our approach, comparing with existing deblocking techniques, is one of the significant methods for reducing blocking artifacts.
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Yang, Jungyoup. "Adaptive deblocking filter for intrablocks." Optical Engineering 49, no. 12 (December 1, 2010): 120502. http://dx.doi.org/10.1117/1.3523479.

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Norkin, Andrey, Gisle Bjontegaard, Arild Fuldseth, Matthias Narroschke, Masaru Ikeda, Kenneth Andersson, Minhua Zhou, and Geert Van der Auwera. "Corrections to “HEVC Deblocking Filter”." IEEE Transactions on Circuits and Systems for Video Technology 23, no. 12 (December 2013): 2141. http://dx.doi.org/10.1109/tcsvt.2013.2276171.

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Nandhagopal, N., S. Navaneethan, and C. Arul Murugan. "The reordered deblocking filter and SAO architecture for HEVC system." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 617. http://dx.doi.org/10.14419/ijet.v7i2.8.10544.

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High Efficiency Video Coding (HEVC) used in broad band and wireless applications employs two in-loop filters to remove the blurring artifacts, blocking artifacts and ringing artifacts. The standard h.264/AVC deblocking filter which requires more memory initially filters the horizontal borders, followed by the vertical borders. The results of vertical borders filtering are utilized in the horizontal filtering process and the obtained results are further stored in temporary memory. The proposed system comprises of a reordering filter to reduce the order of the filter and a SAO to modify the decoded samples to a new offset value inorder to perform robust encryption mechanism. Hence reorder filter reduces the memory needed for this filtering process. In HEVC, SAO is an in-loop filter and located next to deblocking filter. The idea of SAO is to compensate renovated samples by adding an offset to each pixel, so that the distortion between renovated picture and original one can be reduced. Implementation of proposed simulation work is done by Verilog HDL and implemented using Virtex 6 FPGA to compute the power and hardware requirements in terms of LUT and slice registers.
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Correa, Guilherme, Luciano Agostini, and Luis A. da Silva Cruz. "Sample-Level Filtering Order for High-Throughput and Memory-Aware H.264 Deblocking Filter." ISRN Signal Processing 2012 (May 31, 2012): 1–6. http://dx.doi.org/10.5402/2012/805346.

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This paper presents a new sample-level filtering order for the Deblocking Filter process of the H.264/AVC video coding standard to be used instead of the traditional block-level order presented in previous works. This processing order allows a better exploration of the parallelism in the filtering process by reducing data dependencies in comparison to other works. The proposed sample-level order allows four parallel and independent samples filtering simultaneously, completing one complete macroblock filtering in fewer cycles and requiring less memory space than the related works. The proposed filtering order can be applied to the Deblocking Filter presented in a conventional H.264/AVC encoder or decoder and to the H.264/SVC interlayer Deblocking Filter. When compared to the original H.264/AVC filter and to the best related work found in the literature, the proposed scheme achieves a reduction of 72% and 25% in the number of clock cycles and a memory usage decrease of 75% and 43%, respectively.
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Wang, Gang, He Xin Chen, and Mian Shu Chen. "Research on the Algorithm of Adaptive Loop Filter Based on Flexible Quadtree." Applied Mechanics and Materials 423-426 (September 2013): 2491–95. http://dx.doi.org/10.4028/www.scientific.net/amm.423-426.2491.

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The algorithm of adaptive loop filter based on flexible quad tree (Q-ALF) is put forward targeting the problem that deblocking loop filter used by H.264/AVC cant further improve video coding quality. This algorithm, through the original image and the image after deblocking filter, works out wiener filter and selects a wiener filter with optimal size by taking the SAD of the image after Wiener filtering and the original image as RDO cost and based on RDO model, then uses this filter to filtrate the area that needs filtration. Simulation result shows that Q-ALF algorithm can improve the PSNR of the reconstructed image and decrease bit rate; meanwhile, Q-ALF algorithm can better eliminate blocking effect, improving the subjective performance of the reconstructed image.
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Palau, Roberta De Carvalho Nobre, Jones Goebel, Daniel Palomino, Guilherme Correa, Marcelo Porto, and Luciano Agostini. "Real-Time and Low-Power HEVC Deblocking Filter Architecture Targeting 8K UHD @ 60fps Videos." Journal of Integrated Circuits and Systems 15, no. 1 (May 26, 2020): 1–9. http://dx.doi.org/10.29292/jics.v15i1.59.

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This paper presents a low-power and high-throughput Deblocking Filter (DBF) hardware architecture for the High Efficiency Video Coding (HEVC) standard. The architecture implements the three HEVC deblocking filtering modes, namely: (i) normal filter, (ii) strong filter and (iii) chroma filter. The designed DBF architecture is able to process 64 samples per clock cycle, considering luminance and chrominance components. The architecture was described in VHDL and synthesized targeting the CMOS standard-cell TSMC 40nm library. The power results were reached with real input samples extracted from the HEVC reference software. Synthesis results show that the DBF design, when running at 124.4MHz, can reach a throughput of 60 frames per second (fps) for a 7680×4320 (8K UHD) video resolution. At this frequency, the DBF design presented a low power dissipation of 4.73mW. The presented DBF hardware surpasses all related works in terms of throughput and power dissipation and is the unique solution able to real-time processing of 8K UHD videos at 60 frames per second.
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Dissertations / Theses on the topic "Deblocking filter"

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Khraisha, Rakan. "Bit-rate aware reconfigurable architecture for h.264/avc deblocking filter." Master's thesis, University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4536.

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In H.264/AVC, DeBlocking Filter (DBF) achieves bit rate savings and it is used to improve visual quality by reducing the presence of blocking artifacts. However, these advantages come at the expense of increasing computational complexity of the DBF due to highly adaptive mode decision and small 4x4 block size. The DBF easily accounts for one third of the computational complexity of the decoder. The computational complexity required for various target applications from mobile to high definition video applications varies significantly. Therefore, it becomes apparent to design efficient architecture to adapt to different requirements. In this work, we exploit the scalability on both the hardware level and the algorithmic level to synergize the performance and to reduce computational complexity. First, we propose a modular DBF architecture which can be scaled to adapt to the required computing capability for various bit-rates, resolutions, and frame rates of video sequences. The scalable architecture is based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. The proposed design can be scaled to filter up to four different edges simultaneously, resulting in significant reduction of total processing time. Secondly, our experiments show by lowering the bit rate of video sequences, significant reduction in computational complexity can be achieved by the increased presence of skipped macroblocks, thus, avoiding redundant filtering operations. The implemented architecture has been evaluated using Xilinx Virtex-4 ML410 FPGA board. The design can operate at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.
ID: 028732065; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.Cp.E.)--University of Central Florida, 2010.; Includes bibliographical references.
M.S.Cp.E.
Masters
School of Electrical Engineering and Computer Science
Engineering and Computer Science
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Ernst, Eric Gerard. "Architecture design of a scalable adaptive deblocking filter for H.264/AVC /." Online version of thesis, 2007. http://hdl.handle.net/1850/5390.

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Rosa, Vagner Santos da. "Arquiteturas de hardware dedicadas para codificadores de vídeo H.264 : filtragem de efeitos de bloco e codificação aritmética binária adaptativa a contexto." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27669.

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Novas arquiteturas de hardware desenvolvidas para blocos chave do padrão de codificação de vídeo ISO/IEC 14496-10 são discutidas, propostas, implementadas e validades nesta tese. Também chamado de H.264, AVC (Advanced Video Coder) ou MPEG-4 parte 10, o padrão é o estado da arte em codificação de vídeo, apresentando as mais altas taxas de compressão possíveis por um compressor de vídeo padronizado por organismos internacionais (ISO/IEC e ITU-T). O H.264 já passou por três revisões importantes: na primeira foram incluídos novos perfis, voltados para a extensão da fidelidade e aplicações profissionais, na segunda veio o suporte a escalabilidade (SVC – Scalable Video Coder). Uma terceira revisão suporta fontes de vídeo com múltiplas vistas (MVC – Multi-view Video Coder). Nesta tese são apresentadas arquiteturas para dois módulos do codificador H.264: o CABAC e o Filtro de Deblocagem (Deblocking Filter). O CABAC (Context-Adaptive Binary Arithmetic Coder) possui desafios importantes devido às dependências de dados de natureza bit-a-bit. Uma revisão das alternativas arquiteturais e uma solução específica para a codificação CABAC é apresentada nesta tese. O filtro de deblocagem também apresenta diversos desafios importantes para seu desenvolvimento e foi alvo de uma proposta arquitetural apresentada neste trabalho. Finalmente a arquitetura de uma plataforma de validação genérica para validar módulos desenvolvidos para o codificador e decodificador H.264 também é apresentada. Os módulos escolhidos estão de acordo com os demais trabalhos realizados pelo grupo de pesquisa da UFRGS, que têm por objetivo desenvolver um decodificador e um codificador completos capazes de processar vídeo digital de alta definição no formato 1080p em tempo real.
New hardware architectures developed for key blocks of the ISO/IEC 14496-10 video coding standard are discussed, proposed, implemented, and validated in this thesis. The standard is also called H.264, AVC (Advanced Video Coder) or MPEG-4 part 10, and is the state-of-the-art in video coding, presenting the highest compression ratios achievable by an internationally standardized video coder (ISO/IEC and ITU-T). The H.264 has already been revised three times: the first included new profiles for fidelity extension and professional applications. The second brought the scalability support (SVC – Scalable Video Coder). The third revision supports video sources with multiple views (MVC – Multi-view Video Coder). The present work developed high performance architectures for CABAC (Context-Adaptive Binary Arithmetic Coder), which were challenging because of the bitwise data dependencies. A through revision of the alternative architectures and a specific architectural solution for CABAC encoding are presented in this thesis. A dedicated hardware architecture for a HIGH profile Deblocking Filter is also presented, developed, validated and synthesized for two different targets: FPGA and ASIC. The validation methodology is presented and applied to three different modules of the H.264 encoder. The H.264 blocks dealt with in this thesis work complement those developed by other works in the UFRGS research group and contribute to the development of complete encoders for real-time processing of high definition digital video at 1080p.
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Rossholm, Andreas. "On Enhancement and Quality Assessment of Audio and Video in Communication Systems." Doctoral thesis, Blekinge Tekniska Högskola, Institutionen för tillämpad signalbehandling, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-00604.

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The use of audio and video communication has increased exponentially over the last decade and has gone from speech over GSM to HD resolution video conference between continents on mobile devices. As the use becomes more widespread the interest in delivering high quality media increases even on devices with limited resources. This includes both development and enhancement of the communication chain but also the topic of objective measurements of the perceived quality. The focus of this thesis work has been to perform enhancement within speech encoding and video decoding, to measure influence factors of audio and video performance, and to build methods to predict the perceived video quality. The audio enhancement part of this thesis addresses the well known problem in the GSM system with an interfering signal generated by the switching nature of TDMA cellular telephony. Two different solutions are given to suppress such interference internally in the mobile handset. The first method involves the use of subtractive noise cancellation employing correlators, the second uses a structure of IIR notch filters. Both solutions use control algorithms based on the state of the communication between the mobile handset and the base station. The video enhancement part presents two post-filters. These two filters are designed to improve visual quality of highly compressed video streams from standard, block-based video codecs by combating both blocking and ringing artifacts. The second post-filter also performs sharpening. The third part addresses the problem of measuring audio and video delay as well as skewness between these, also known as synchronization. This method is a black box technique which enables it to be applied on any audiovisual application, proprietary as well as open standards, and can be run on any platform and over any network connectivity. The last part addresses no-reference (NR) bitstream video quality prediction using features extracted from the coded video stream. Several methods have been used and evaluated: Multiple Linear Regression (MLR), Artificial Neural Network (ANN), and Least Square Support Vector Machines (LS-SVM), showing high correlation with both MOS and objective video assessment methods as PSNR and PEVQ. The impact from temporal, spatial and quantization variations on perceptual video quality has also been addressed, together with the trade off between these, and for this purpose a set of locally conducted subjective experiments were performed.
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Yo-Ray, Lee. "Instruction Set Extension For Deblocking Filter." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709264754.

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Lee, Yo-Ray, and 李岳叡. "Instruction Set Extension For Deblocking Filter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91596609321006376554.

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碩士
國立清華大學
資訊工程學系
94
H.264/AVC is a new codec standard for video. A traditional DSP architecture is not e±cient enough for this new standard. The pro¯ling results show that Deblocking Filter consumes up to 33% running time of H.264 decoder. In this thesis, we focus on designing new instructions to speed up Deblocking Filter. Based on a standard Star¯sh DSP, we propose novel instructions and architecture for Deblocking Filter. In experiment result, we show that 28.5% improvement in computation time is achieved on Filter Processing part of Deblocking Filter by our new instructions.
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Huang, Yao-Min, and 黃耀民. "Hybrid Deblocking Filter for H.264 Video." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/74772673011801236769.

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碩士
國立中正大學
資訊工程所
94
Most video coding standards use block-based discrete cosine transform (DCT)and motion-compensated prediction (MCP) to reduce both spatial redundancy andtemporal. For very low bit rate coding, coarse-quantized DCT coefficients suffer discontinuities at block boundaries, namely blocking artifact, after reverse transform. Furthermore, motion-compensated prediction propagates blocking artifacts to inner-block regions, which makes artifact detection difficult. Blocking artifacts caused by motion-compensated prediction can be solved by a loop-filter, which is integrated to the codec and filtered frames are used as reference frames. The main drawback of loop-filter is its in-flexibility, i.e., users cannot enable/disable filtering freely but restricted by the received bitstream. In this study, a hybrid deblocking filter for H.264 video is proposed. To estimate inner-block discontinuities, a motion-compensated based approach is proposed. A map of detected blocking artifacts within each video frame is stored. Combining motion vectors and blocking artifact maps of previous frames, possible locations where blocking artifacts may occur can be estimated. Cooperating with oriented blocking artifact detecting and filtering, we successfully realize loop-filter performance with a post-filter. The proposed approach can also used in other DCT/MCP based codecs.
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Kao, Jui-Chang, and 高瑞昌. "Adaptive Deblocking Filter Algorithm for H.264." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/p85f2h.

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碩士
國立臺北科技大學
電子電腦與通訊產業研發碩士專班
95
The video compression technology is more important, because the digital multimedia is widely used in our life. Block-based video coding cooperating with block transform and block motion compensation is the most widely adopted way to reduce the data redundancy in various video coding standards such as JPEG, MPEG-1/2/4, and H.264/AVC. Not only energy is compacted and de-corrected but also redundancy information is reduced. Although block structure gains data compression, it results in blocking effect which impacts the quality of compressed video. In general, block compressed technology can usually obtain acceptable quality of video but suffer from annoying blocking artifacts when it becomes worse especially in the low bit rate or high quantization parameter video environment. H.264/AVC standards include the deblocking filters inside its coding loop, in order to reduce the block effect for the visual quality of images or videos. In this work, we propose an adaptive deblocking filter algorithm to reduce blocking effect for H.264 video coding system. If block effect can not be solved, the quality of compressed video must be bad even it sets parameters and thresholds appropriately. We not only propose a deblocking filter algorithm for reducing block effect but also present an effective search algorithm to reduce coding time. The advantages of our proposed algorithm are the lower complexity of computation and better offsetA and offsetB of possession in slice level. Experiment results show that our proposed method can improve visual quality of reconstructed video. We present an adaptive deblocking filter algorithm to reduce blocking effect and reduce coding times than the JM10.2 by about 10%.
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Sheu, Shin-Feng, and 許昕豐. "A Study of Deblocking Filter for Video." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/4sba79.

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碩士
國立成功大學
電機工程學系碩博士班
90
Increasing the bandwidth or bit rate in real-time video application to obtain better images quality is usually not possible or too costly. Post-processing appears to be the most practical solution because it does not require any change to existing standards. If the blocking effects can be significantly reduced, higher compression ratios at the same image quality or better quality at the same compression performance can be achieved. In this Thesis, we proposed a deblocking algorithm based on three filtering modes in terms of the activity across block boundaries. By given proper consideration of the masking effect of the HVS (Human Visual System), an adaptive filtering decision is integrated into deblocking processing. Based on three different deblocking modes appropriate for the characteristic of local region, the perceptual quality as well as the objective quality is improved without over smoothing the image details and insufficient reducing the strong blocking effect on flat region. According to the simulation results, the proposed method shows better performance than those deblocking methods by H.26L and MPEG-4 in terms of PSNR. Noticeable perceptual improvements of image quality are achievable.
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Lee, Wen-Ping, and 李文平. "A Deblocking Filter for H.264/AVC Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/68488858053208997210.

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Book chapters on the topic "Deblocking filter"

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Lin, Youn-Long Steve, Chao-Yang Kao, Huang-Chih Kuo, and Jian-Wen Chen. "Deblocking Filter." In VLSI Design for Video Coding, 107–24. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0959-6_7.

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Lian, Hao, and Mohammed Ghanbari. "Hardware Deblocking Filter and Impact." In Communications in Computer and Information Science, 161–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-85930-7_22.

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Zhao, Jianeng, and Yueli Hu. "Deblocking Filter in Video Denoising." In Advances in Intelligent Automation and Soft Computing, 839–45. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81007-8_96.

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Rosa, Vagner, Altamiro Susin, and Sergio Bampi. "A High Performance H.264 Deblocking Filter." In Advances in Image and Video Technology, 955–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-92957-4_83.

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Kopperundevi, P., and M. Surya Prakash. "An Efficient Hardware Architecture for Deblocking Filter in HEVC." In Lecture Notes in Electrical Engineering, 599–609. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4692-1_46.

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Choi, Jung-Ah, and Yo-Sung Ho. "Deblocking Filter Algorithm with Low Complexity for H.264 Video Coding." In Advances in Multimedia Information Processing - PCM 2008, 138–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89796-5_15.

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Kim, Byung-Joo, Jae-Il Koo, Min-Cheol Hong, and Seongsoo Lee. "Low-Power H.264 Deblocking Filter Algorithm and Its SoC Implementation." In Advances in Image and Video Technology, 771–79. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11949534_77.

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Bae, Jongwoo, Neungsoo Park, and Seong-Won Lee. "Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter." In Embedded and Ubiquitous Computing, 805–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11802167_81.

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Weng, Tsung-Hsi, Yi-Ting Wang, and Chung-Ping Chung. "Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering." In Algorithms and Architectures for Parallel Processing, 80–92. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24650-0_8.

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Song, Yunseok, and Yo-Sung Ho. "Deblocking Filter for Depth Videos in 3D Video Coding Extension of HEVC." In Lecture Notes in Computer Science, 292–99. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-24078-7_29.

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Conference papers on the topic "Deblocking filter"

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Mahjoub, Waseim Hashem, Hossam Osman, and Gamal M. Aly. "H.264 deblocking filter enhancement." In Systems (ICCES). IEEE, 2011. http://dx.doi.org/10.1109/icces.2011.6141046.

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Xie, Xi, Zhenyu Wang, and Ronggang Wang. "Improvement of Deblocking Filter for AVS3." In ICDSP 2020: 2020 4th International Conference on Digital Signal Processing. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3408127.3408141.

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Narroschke, Matthias. "Parallelized deblocking filter for hybrid video coding." In 2011 IEEE Visual Communications and Image Processing (VCIP). IEEE, 2011. http://dx.doi.org/10.1109/vcip.2011.6115999.

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Maiti, Kausik, Sirish K. Pasupuleti, Raj N. Gadde, and Sang Jo Lee. "Efficient deblocking filter implementation on reconfigurable processor." In 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). IEEE, 2016. http://dx.doi.org/10.1109/icassp.2016.7471836.

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Wu, Qingbo, and Hongliang Li. "Mode dependent deblocking filter for video coding." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271550.

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Yang, Jungyoup, Kwanghyun Won, and Byeungwoo Jeon. "Intra prediction mode based improved deblocking filter." In 2011 IEEE International Conference on Consumer Electronics (ICCE). IEEE, 2011. http://dx.doi.org/10.1109/icce.2011.5722813.

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Liu, Ting, Chunchun Chen, and Eryan Yang. "CUDA-based acceleration of post deblocking filter." In Electronics (PrimeAsia). IEEE, 2011. http://dx.doi.org/10.1109/primeasia.2011.6075069.

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Chan, Zhang, Jian Shuyun, and Liang Fan. "An Improved deblocking filter for H.264." In TENCON 2008 - 2008 IEEE Region 10 Conference (TENCON). IEEE, 2008. http://dx.doi.org/10.1109/tencon.2008.4766852.

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Raja, G., and M. J. Mirza. "Low complexity deblocking filter using motion vectors." In 2010 IEEE International Conference on Consumer Electronics (ICCE 2010). IEEE, 2010. http://dx.doi.org/10.1109/icce.2010.5418740.

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Yang, Zhigang, Wen Gao, Yan Liu, and Debin Zhao. "DSP Implementation of Deblocking Filter for AVS." In 2007 IEEE International Conference on Image Processing. IEEE, 2007. http://dx.doi.org/10.1109/icip.2007.4379557.

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