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1
Khraisha, Rakan. "Bit-rate aware reconfigurable architecture for h.264/avc deblocking filter." Master's thesis, University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4536.
Full textAbstract:
In H.264/AVC, DeBlocking Filter (DBF) achieves bit rate savings and it is used to improve visual quality by reducing the presence of blocking artifacts. However, these advantages come at the expense of increasing computational complexity of the DBF due to highly adaptive mode decision and small 4x4 block size. The DBF easily accounts for one third of the computational complexity of the decoder. The computational complexity required for various target applications from mobile to high definition video applications varies significantly. Therefore, it becomes apparent to design efficient architecture to adapt to different requirements. In this work, we exploit the scalability on both the hardware level and the algorithmic level to synergize the performance and to reduce computational complexity. First, we propose a modular DBF architecture which can be scaled to adapt to the required computing capability for various bit-rates, resolutions, and frame rates of video sequences. The scalable architecture is based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. The proposed design can be scaled to filter up to four different edges simultaneously, resulting in significant reduction of total processing time. Secondly, our experiments show by lowering the bit rate of video sequences, significant reduction in computational complexity can be achieved by the increased presence of skipped macroblocks, thus, avoiding redundant filtering operations. The implemented architecture has been evaluated using Xilinx Virtex-4 ML410 FPGA board. The design can operate at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.ID: 028732065; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.Cp.E.)--University of Central Florida, 2010.; Includes bibliographical references.
M.S.Cp.E.
Masters
School of Electrical Engineering and Computer Science
Engineering and Computer Science
2
Ernst, Eric Gerard. "Architecture design of a scalable adaptive deblocking filter for H.264/AVC /." Online version of thesis, 2007. http://hdl.handle.net/1850/5390.
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Rosa, Vagner Santos da. "Arquiteturas de hardware dedicadas para codificadores de vídeo H.264 : filtragem de efeitos de bloco e codificação aritmética binária adaptativa a contexto." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27669.
Full textAbstract:
Novas arquiteturas de hardware desenvolvidas para blocos chave do padrão de codificação de vídeo ISO/IEC 14496-10 são discutidas, propostas, implementadas e validades nesta tese. Também chamado de H.264, AVC (Advanced Video Coder) ou MPEG-4 parte 10, o padrão é o estado da arte em codificação de vídeo, apresentando as mais altas taxas de compressão possíveis por um compressor de vídeo padronizado por organismos internacionais (ISO/IEC e ITU-T). O H.264 já passou por três revisões importantes: na primeira foram incluídos novos perfis, voltados para a extensão da fidelidade e aplicações profissionais, na segunda veio o suporte a escalabilidade (SVC – Scalable Video Coder). Uma terceira revisão suporta fontes de vídeo com múltiplas vistas (MVC – Multi-view Video Coder). Nesta tese são apresentadas arquiteturas para dois módulos do codificador H.264: o CABAC e o Filtro de Deblocagem (Deblocking Filter). O CABAC (Context-Adaptive Binary Arithmetic Coder) possui desafios importantes devido às dependências de dados de natureza bit-a-bit. Uma revisão das alternativas arquiteturais e uma solução específica para a codificação CABAC é apresentada nesta tese. O filtro de deblocagem também apresenta diversos desafios importantes para seu desenvolvimento e foi alvo de uma proposta arquitetural apresentada neste trabalho. Finalmente a arquitetura de uma plataforma de validação genérica para validar módulos desenvolvidos para o codificador e decodificador H.264 também é apresentada. Os módulos escolhidos estão de acordo com os demais trabalhos realizados pelo grupo de pesquisa da UFRGS, que têm por objetivo desenvolver um decodificador e um codificador completos capazes de processar vídeo digital de alta definição no formato 1080p em tempo real.New hardware architectures developed for key blocks of the ISO/IEC 14496-10 video coding standard are discussed, proposed, implemented, and validated in this thesis. The standard is also called H.264, AVC (Advanced Video Coder) or MPEG-4 part 10, and is the state-of-the-art in video coding, presenting the highest compression ratios achievable by an internationally standardized video coder (ISO/IEC and ITU-T). The H.264 has already been revised three times: the first included new profiles for fidelity extension and professional applications. The second brought the scalability support (SVC – Scalable Video Coder). The third revision supports video sources with multiple views (MVC – Multi-view Video Coder). The present work developed high performance architectures for CABAC (Context-Adaptive Binary Arithmetic Coder), which were challenging because of the bitwise data dependencies. A through revision of the alternative architectures and a specific architectural solution for CABAC encoding are presented in this thesis. A dedicated hardware architecture for a HIGH profile Deblocking Filter is also presented, developed, validated and synthesized for two different targets: FPGA and ASIC. The validation methodology is presented and applied to three different modules of the H.264 encoder. The H.264 blocks dealt with in this thesis work complement those developed by other works in the UFRGS research group and contribute to the development of complete encoders for real-time processing of high definition digital video at 1080p.
4
Rossholm, Andreas. "On Enhancement and Quality Assessment of Audio and Video in Communication Systems." Doctoral thesis, Blekinge Tekniska Högskola, Institutionen för tillämpad signalbehandling, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-00604.
Full textAbstract:
The use of audio and video communication has increased exponentially over the last decade and has gone from speech over GSM to HD resolution video conference between continents on mobile devices. As the use becomes more widespread the interest in delivering high quality media increases even on devices with limited resources. This includes both development and enhancement of the communication chain but also the topic of objective measurements of the perceived quality. The focus of this thesis work has been to perform enhancement within speech encoding and video decoding, to measure influence factors of audio and video performance, and to build methods to predict the perceived video quality. The audio enhancement part of this thesis addresses the well known problem in the GSM system with an interfering signal generated by the switching nature of TDMA cellular telephony. Two different solutions are given to suppress such interference internally in the mobile handset. The first method involves the use of subtractive noise cancellation employing correlators, the second uses a structure of IIR notch filters. Both solutions use control algorithms based on the state of the communication between the mobile handset and the base station. The video enhancement part presents two post-filters. These two filters are designed to improve visual quality of highly compressed video streams from standard, block-based video codecs by combating both blocking and ringing artifacts. The second post-filter also performs sharpening. The third part addresses the problem of measuring audio and video delay as well as skewness between these, also known as synchronization. This method is a black box technique which enables it to be applied on any audiovisual application, proprietary as well as open standards, and can be run on any platform and over any network connectivity. The last part addresses no-reference (NR) bitstream video quality prediction using features extracted from the coded video stream. Several methods have been used and evaluated: Multiple Linear Regression (MLR), Artificial Neural Network (ANN), and Least Square Support Vector Machines (LS-SVM), showing high correlation with both MOS and objective video assessment methods as PSNR and PEVQ. The impact from temporal, spatial and quantization variations on perceptual video quality has also been addressed, together with the trade off between these, and for this purpose a set of locally conducted subjective experiments were performed.
5
Yo-Ray, Lee. "Instruction Set Extension For Deblocking Filter." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709264754.
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Lee, Yo-Ray, and 李岳叡. "Instruction Set Extension For Deblocking Filter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91596609321006376554.
Full textAbstract:
碩士國立清華大學
資訊工程學系
94
H.264/AVC is a new codec standard for video. A traditional DSP architecture is not e±cient enough for this new standard. The pro¯ling results show that Deblocking Filter consumes up to 33% running time of H.264 decoder. In this thesis, we focus on designing new instructions to speed up Deblocking Filter. Based on a standard Star¯sh DSP, we propose novel instructions and architecture for Deblocking Filter. In experiment result, we show that 28.5% improvement in computation time is achieved on Filter Processing part of Deblocking Filter by our new instructions.
7
Huang, Yao-Min, and 黃耀民. "Hybrid Deblocking Filter for H.264 Video." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/74772673011801236769.
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碩士國立中正大學
資訊工程所
94
Most video coding standards use block-based discrete cosine transform (DCT)and motion-compensated prediction (MCP) to reduce both spatial redundancy andtemporal. For very low bit rate coding, coarse-quantized DCT coefficients suffer discontinuities at block boundaries, namely blocking artifact, after reverse transform. Furthermore, motion-compensated prediction propagates blocking artifacts to inner-block regions, which makes artifact detection difficult. Blocking artifacts caused by motion-compensated prediction can be solved by a loop-filter, which is integrated to the codec and filtered frames are used as reference frames. The main drawback of loop-filter is its in-flexibility, i.e., users cannot enable/disable filtering freely but restricted by the received bitstream. In this study, a hybrid deblocking filter for H.264 video is proposed. To estimate inner-block discontinuities, a motion-compensated based approach is proposed. A map of detected blocking artifacts within each video frame is stored. Combining motion vectors and blocking artifact maps of previous frames, possible locations where blocking artifacts may occur can be estimated. Cooperating with oriented blocking artifact detecting and filtering, we successfully realize loop-filter performance with a post-filter. The proposed approach can also used in other DCT/MCP based codecs.
8
Kao, Jui-Chang, and 高瑞昌. "Adaptive Deblocking Filter Algorithm for H.264." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/p85f2h.
Full textAbstract:
碩士國立臺北科技大學
電子電腦與通訊產業研發碩士專班
95
The video compression technology is more important, because the digital multimedia is widely used in our life. Block-based video coding cooperating with block transform and block motion compensation is the most widely adopted way to reduce the data redundancy in various video coding standards such as JPEG, MPEG-1/2/4, and H.264/AVC. Not only energy is compacted and de-corrected but also redundancy information is reduced. Although block structure gains data compression, it results in blocking effect which impacts the quality of compressed video. In general, block compressed technology can usually obtain acceptable quality of video but suffer from annoying blocking artifacts when it becomes worse especially in the low bit rate or high quantization parameter video environment. H.264/AVC standards include the deblocking filters inside its coding loop, in order to reduce the block effect for the visual quality of images or videos. In this work, we propose an adaptive deblocking filter algorithm to reduce blocking effect for H.264 video coding system. If block effect can not be solved, the quality of compressed video must be bad even it sets parameters and thresholds appropriately. We not only propose a deblocking filter algorithm for reducing block effect but also present an effective search algorithm to reduce coding time. The advantages of our proposed algorithm are the lower complexity of computation and better offsetA and offsetB of possession in slice level. Experiment results show that our proposed method can improve visual quality of reconstructed video. We present an adaptive deblocking filter algorithm to reduce blocking effect and reduce coding times than the JM10.2 by about 10%.
9
Sheu, Shin-Feng, and 許昕豐. "A Study of Deblocking Filter for Video." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/4sba79.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
90
Increasing the bandwidth or bit rate in real-time video application to obtain better images quality is usually not possible or too costly. Post-processing appears to be the most practical solution because it does not require any change to existing standards. If the blocking effects can be significantly reduced, higher compression ratios at the same image quality or better quality at the same compression performance can be achieved. In this Thesis, we proposed a deblocking algorithm based on three filtering modes in terms of the activity across block boundaries. By given proper consideration of the masking effect of the HVS (Human Visual System), an adaptive filtering decision is integrated into deblocking processing. Based on three different deblocking modes appropriate for the characteristic of local region, the perceptual quality as well as the objective quality is improved without over smoothing the image details and insufficient reducing the strong blocking effect on flat region. According to the simulation results, the proposed method shows better performance than those deblocking methods by H.26L and MPEG-4 in terms of PSNR. Noticeable perceptual improvements of image quality are achievable.
10
Lee, Wen-Ping, and 李文平. "A Deblocking Filter for H.264/AVC Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/68488858053208997210.
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Chu, Yu-Ching, and 朱育慶. "Adaptive Deblocking Filter Algorithm for H.264 Standard." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/97214548476873605845.
Full textAbstract:
碩士國立東華大學
電機工程學系
93
Traditional block-based video coders such as H.261, H.263, H.264/AVC or MPEG-1/2/4 suffer from annoying blocking artifacts when they are applied in low bit-rate coding because inter block correlation is lost by block-based prediction, transformation, and quantization. In order to overcome the blocking artifact problem, a filter is applied to each decoded macroblock in order to reduce blocking distortion. The deblocking filter in H.264 is an efficient tool to reduce blocking artifact, but it also blurs the details or retains blocking artifact perceptible in some high-activity areas. In this paper, we improve the filtered pixel classification and filtering schemes used by the deblocking filter in H.264 to keep the sharpeness of real edges. The proposed algorithm is composed of a diagonal direction filtering method that can minimize over-smoothing. The experimental results obviously show the proposed method improves subjective and objective quality. The good performance is based on reliable detection of real and artificially created edges.
12
Zeng, Jian-Ping, and 曾建平. "VLSI Architecture for Deblocking Filter in H.264/AVC." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/14137456044414587354.
Full textAbstract:
碩士南台科技大學
電子工程系
95
The new video coding standard recommendation H.264 of ITU-T, also known as International Standard 14496-10 or MPEG-4 Part 10 Advanced Video Coding (AVC) of ISO/IEC, has been developed. It significantly outperforms the previous ones (H.261, MPEG-1 Video, MPEG-2 Video, H.263, and MPEG-4 Visual or part 2) in the aspect of bit-rate reduction. At the same time, preliminary studies using software based on this new standard, suggest that H.264 offers up to 50% better compression than MPEG-2 and up to 30% better than H.263+ and MPEG-4 advanced simple profile. In the complexity simulation of H.264/AVC decoder/encoder, the deblocking filter is the most complexity part. Obviously to improve decoder/encoder performance, the deblocking filter will be considered first to be improved. In this thesis, we study and analyze deblocking filter in H.264/AVC. In order to reduce the number of memory references and thus improve overall system performance, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV, 1920x1080 pixels/frame, 60 frames/video signals) video operation at 60 MHz. The proposed PBSR(Pipeline Buffer Shift Registers) and Window-based architecture deblocking filters are implemented by using Verilog HDL. The function of the implemented deblocking filters is also verified by ModelSim. It can be shown that the number of the total memory references is reduced by 78.75% and 52.5% respectively compared to the basic and advanced architectures of the previous works. As a result, the performance of our configurable window-based architecture with parallel engine significantly outperforms the previous designs in terms of memory references and processing cycles.
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Chia-WeiHuang and 黃家偉. "A Parallel Processing Deblocking Filter in H.264/AVC." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/11053601095692901952.
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Chen, Chung-Ming, and 陳崇明. "VLSI Architecture for Deblocking Filter in H.264/AVC." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/77476627821557561750.
Full textAbstract:
博士國立成功大學
電機工程學系碩博士班
95
In this work, we study and analyze the computational complexity of the deblocking filter in H.264/AVC decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time and power consuming in the decoder of this new video coding standard. In order to improve memory performance and speed up the deblocking filter for overall system performance and power consumption, we propose a configurable, extensible, and synthesizable window-based architecture with simultaneously processing of the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The proposed architecture has four major ideas. The first idea is to reduce the number of condition branch operations by implementing content activity check operations, the table-derived operations, and edge filtering operations into the Table-Free Edge Filtering Engine. The second idea is the Simultaneous Processing Architecture (SPA) with a new processing order to simultaneously process the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The third idea is to reduce the number of memory references using a configurable window-based architecture with a novel processing order to simultaneously process the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The last idea is to parallelize the Table-Free Edge Filtering Engine to speed up the system performance. As a result, the processing capability of the configurable window-based architecture is very appropriate for real-time deblocking of high-definition television (High-definition television, HDTV, 1920x1080 pixels/frame, 60 frames/sec video signals) video operation at 60MHz. Moreover, the system performance of our window-based architecture significantly outperforms the previous designs from 7 times to 20 times. The memory performance of the proposed architecture is improved by four times when compared to the software implementation.
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Kuo, Tzu-Rung, and 郭子榮. "A Study of Deblocking Effect Using Linear Filter Technology." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/33243880862368840174.
Full textAbstract:
碩士大葉大學
資訊工程學系碩士在職專班
94
Block-Based Discrete Cosine Transform has been wisely applied on compression standard of still image or video. However, at low bit rates the reconstructed images generally suffer from visually annoying artifacts as a result of very coarse quantization. For better vision quality and effect, there are many techniques developed to reduce the blocking effect. In general, post-processing at the decode side is very much desired, because it causes the least change to the compression and transmission scheme. In this thesis, according to the pixel variability of 8x8 blocks, we proposed an algorithm to reduce blocking effect. We distinguish image pixels into high activity region and low activity region according to the degree of blocking effect. We will do nothing for high activity region, and using adaptive linear filter for low activity region. As result, there will have good result on vision or statistics objectivity. We demonstrate the method would reduce blocking effect and enhance the human vision quality
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Dickey, Brian. "Hardware Implementation of a High Speed Deblocking Filter for the H.264 Video Codec." Thesis, 2012. http://hdl.handle.net/10012/6645.
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H.264/MPEG-4 part 10 or Advanced Video Coding (AVC) is a standard for video compression. MPEG-4 is currently one of the most widely used formats for recording, compression and distribution of high definition video. One feature of the AVC codec is the inclusion of an in-loop deblocking filter.
The goal of the deblocking filter is to remove blocking artifacts that exist at macroblock
boundaries. However, due to the complexity of the deblocking algorithm, the filter can
easily account for one-third of the computational complexity of a decoder.
In this thesis, a modification to the deblocking algorithm given in the AVC standard
is presented. This modification allows the algorithm to finish the filtering of a macroblock
to finish twenty clock cycles faster than previous single filter designs.
This thesis also presents a hardware architecture of the H.264 deblocking filter to be
used in the H.264 decoder. The developed architecture allows the filtering of videos streams using 4:2:2 chroma subsampling and 10-bit pixel precision in real-time.
The filter was described in VHDL and synthesized for a Spartan-6 FPGA device. Timing analysis showed that is was capable of filtering a macroblock using 4:2:0 chroma subsampling in 124 clock cycles and 4:2:2 chroma subsampling streams in 162 clock cycles. The filter can also provide real-time deblocking of HDTV video (1920x1080) of up to 988 frames per second.
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Ku, Tsung-Fan, and 古宗凡. "Adaptive Post-Processing Deblocking Filter Algorithm for Various Video Decoders." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/28250806232795130292.
Full textAbstract:
碩士國立東華大學
電機工程學系
94
At the low bit-rate video coding, the blocking effects are more perceptible and annoying to the human vision. Therefore, the deblocking filter is important in video compression technology to remove the blocking effects occurring at the low bit-rate. In this thesis, we propose a low-complexity adaptive post-processing deblocking filter to reduce the blocking effects. Our proposed algorithm can suit for existing block-based video compression standards without any modification. Our proposed algorithm can determine that the blocking effects occur at 4×4 or 8×8 block boundaries automatically. In the filter stage, our proposed algorithm provides four filter modes to eliminate the blocking effects that occur at different frequency regions. In order to improve the subjective quality, the chrominance filter is also presented in our proposed algorithm. Experiment results show that our proposed algorithm has better quality and lower processing time compared with previous works for MPEG-4 and H.264/AVC reconstructed sequences.
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Hsu, Po-Kai, and 許博凱. "VLSI Architecture of High Throughput Deblocking Filter for HEVC Systems." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/00224032554415965157.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
103
This thesis presents the VLSI architecture and hardware implementation of a high throughput deblocking filter for High Efficiency Video Coding (HEVC) systems. In particular, in order to reduce required memory bandwidth and to improve timing efficiency, novel data structures and memory access schemes for image pixels are utilized in this design.The detailed storage structure and data access scheme will be illustrated and VLSI architecture for the deblocking filter engine will be depicted in this thesis. In addition, the proposed deblocking filter is designed and implemented using TSMC 90nm standard cell library. Experimental results based on post-layout estimations show that the proposed design can achieve 60 frames per second for frame resolution of 4096 × 2048 pixels (Ultra HD resolution) assuming an operating frequency of 100MHz. Moreover, comparing to prior arts targeting on similar performance specifications, the proposed design occupies significantly less logic circuits and SRAMs.
19
Cheng-Yueh, Lo. "Architecture Design of Parallel-processing Deblocking Filter in H.264/AVC." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709293611.
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Wang, Yi-Ting, and 王薏婷. "Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/56109151764818586066.
Full textAbstract:
碩士國立交通大學
資訊科學與工程研究所
100
In the H.264 video compression standard, the deblocking filter contributes about one-third of all computation in the decoder. With multi-processor architectures becoming the future trend of system design, computation time reduction can be achieved if the deblocking filter well apportions its operations to multiple processing elements. In this paper, we apply a 16 pixel long boundary, the basic unit for deblocking in the H.264 standard and a 4 pixel long boundary as the basis for analyzing and exploiting possible parallelism in deblocking filtering. Moreover, a possible compromise to fully utilize limited hardware resources and hardware architectural requirements for deblocking are also proposed in this paper. Compared with the 2D wave-front method order for deblocking both 1920*1080 and 1080*1920 pixel sized frames, the 16 pixel long boundary method gains speedups of 1.57 and 2.15 times given an un-limited number of processing elements respectively, and the 4 pixel long boundary method gains speedups of 1.92 and 2.44 times given an un-limited number of processing elements respectively. Using this approach, the execution time of the deblocking filter is proportional to the square root of the growth of the frame size (keeping the same width/height ratio), pushing the boundary of practical real-time deblocking of increasingly larger video sizes.
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Yu-WenHung and 洪郁文. "Pipeline Architecture for Parallel Processing Deblocking Filter in H.264/AVC." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/03736318814664293789.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
100
Due to the rapid spread of Internet, multimedia plays an important role in daily life. H.264/AVC is a newly video compression standard, compared with the past standards, it has high compression efficiency, but it has high computational complexity as well. In the image compression process, because high compression rate requires larger quantization parameter, the boundary between the blocks becomes discontinuous. The most obvious phenomenon in the H.264 is the blocking artifact. In order to reduce the blocking artifact, H.264 adapted the deblocking filter as its main block in the decoder loop, it increases the image quality. In this thesis, we proposed a parallel processing deblocking filter with pipeline architecture, compared to the traditional deblocking filter, it takes less clock cycles to process a maroblock, and moreover, it reduces the memory requirement effectively.
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Lo, Cheng-Yueh, and 羅正岳. "Architecture Design of Parallel-processing Deblocking Filter in H.264/AVC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/68822249749074307695.
Full textAbstract:
碩士國立清華大學
電機工程學系
94
In our daily life, digital video is always an important part for us. Among television, computer monitor, cell-phone and palm game player, these equipments all need video technology to display what they are showing. Especially video coding has become more significant. Some popular techniques of video coding, like MPEG-2, MPEG-4, H.263 and H.264/AVC, have great impact on video quality. Among them, H.264/AVC has been paid most attention recently. H.264/AVC is the latest international video coding standard. It has precise manner of prediction and high compression rate that can achieve high visual quality and greatly reduce required bits in transmission. Because of its complex algorithm, it can achieve high performance. Like intra-prediction, integer-pixel and quarter-pixel motion estimation and context-adaptive binary arithmetic coding (CABAC), they have great improvement on video quality and compression. But due to its high complexity, the hardware VLSI implementation is very hard to be realized. De-blocking filter is an important component of H.264/AVC to reduce the block artifacts. It filters the reconstructed frame to improve video quality of human visual perception. With accessing reconstructed frame data continuously, the processing speed has become one bottleneck for real-time application. Also, the memory usage beside the de-blocking filter for reducing cost needs to be concerned. In this thesis, we propose a new architecture for de-blocking filter in H.264/AVC. New filtering order and overlapped bi-directional filtering will be presented. Two one-dimensional FIR filters are used for horizontal and vertical filtering. The pixel data can be fully reused. Maybe the logic area of the filter is larger, but for reducing the processing time and real-time application, our design may have real merits.
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Huang, Kai-lin, and 黃凱琳. "Deblocking Filter Algorithm by Color Psychology Analysis for Various Video Decoders." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/esx539.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
96
In this thesis, a post-processing deblocking filter is proposed to reduce the blocking effects. This proposed algorithm is suitable for the current block-based video standards without any modification. The proposed algorithm uses Sobel operator and wavelet transform to accurately detect blocking effects at 4×4 or 8×8 blocking boundaries automatically. In the filtering stage, the proposed algorithm provides four filter modes to eliminate blocking effects at different color regions according to human color vision and color psychology analysis. Experimental results show that the proposed algorithm has better subjective and objective qualities for H.264/AVC reconstructed video sequences compared with several existing methods.
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Shih, Sheng-Yu, and 石勝宇. "A High Performance Deblocking Filter for H.264 Advanced Video Coding." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/99535421352220443140.
Full textAbstract:
碩士國立清華大學
資訊工程學系
93
We propose an efficient hardware architecture for deblocking filter in H.264/AVC. We use a novel filtering order that results in significant saving in both filtering time and local memory usage. Compared with state-of-the-art designs, our architecture delivers the fastest level of performance while using much less memory. We have integrated the hardware deblocking filter into an H.264/AVC main profile decoder and verified it with an FPGA prototype.
25
Huang, Tzu-Hsuan, and 黃子軒. "The Implementation of High-Speed Deblocking Filter for H.264/AVC Decoder." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00524046174508958733.
Full textAbstract:
碩士南台科技大學
電子工程系
96
Nowadays the digital video and image technology is becoming the essential part to human life. As the development and demand of the technology, the good quality of digital image is becoming more and more required. However, the high-compression video often loses part of the data during deciding process, and it causes blocking effects in images. The blocking effect makes the discontinuous phenomenon between the blocks in an image. Therefore, we need a deblocking filter to reduce the blocking effect and maintain the image quality. This paper proposes a novel hardware construction for high performance consideration to enhance the efficiency of deblocking filter for H.264/AVC decoder. We use a new block-border processing order to save the cost and increase the efficiency. The experimental results show that our method has the improvement of 15% in performance as comparing to the Basic PBSR （Pipeline Buffer Shift Registers, PBSR） [20]. Also the hardware requirement of register array in our method can be saved about 30 %.
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Chiu, Ching-Chun, and 邱敬淳. "Detection of Video Shot Editing by Deblocking Filter of H.264/AVC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/72649378904965853470.
Full textAbstract:
碩士國立中央大學
資訊工程學系
105
The purpose of this research is to develop a forensic scheme to determine whether an investigated video has been tampered by editing processes, including shot deletion, replacement or insertion, and so on. A detection mechanism based on H.264/AVC de-blocking filter is proposed. Considering that the original video is encoded with H.264/AVC and so is the investigated video, when certain shots in the original encoded video is edited, the re-encoding, may make some I frames in the original GOP (Group of Pictures) be converted into P frames. Such abnormal coding information generated by the tampering operations is employed to assess the authenticity of the investigated video. Most of the proposed tampering detection methods utilize the information of the coding residuals. This study makes use of the de-blocking filter related information in H.264/AVC, which is more difficult to be attacked by anti-detection method than the existing methods. We extract the Boundary Strength (BS), which is the basis of the de-blocking filter for evaluating the filter strength of 4x4 block boundaries. Two graphs for analysis are formed, i.e., Prediction Residual Graph (PRG) and Inter-Prediction Graph (IPG) in a two-dimensional image. In order to deal with various kinds of anti-detection or tampering operations, the proposed method defines three kinds of discontinuities by analyzing PRG or IPG. Three evaluation methods are thus developed, including (1) VRF (Variation of Residual Footprint), which operates on PRG to improve the existing VPF (Variation of Prediction Footprint), (2) DOF (Degree of Fragments), which processes IPG and (3) VCF (Variation of Centroid Footprint), which calculates the offset of centroid in PRG. Finally, we estimate the distances between the detected peaks and find the distance that occurs most frequently to acquire the original GOP size, followed by the determination of the editing position. Besides, the latest anti-detection technology, an attacking method based on changing the quantized coefficients, is also used to verify the proposed detection mechanism based on the de-blocking filter. Experimental results show that, no matter using the fixed QP (Quantization Parameter) or CBR (Constant Bit Rate) encoding, the video after anti-detection attack still reveals abnormal phenomena, which demonstrate the robustness of the proposed method.
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Chen, Hsuan-Hung, and 陳宣宏. "Analysis and VLSI Architecture Design of Non-Deblocking Loop Filter in HEVC Encoder." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/74492628464416045509.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
100
Advanced video applications have an epochal impacts to the history of human visual perception system. Television and communication technology evolve toward more realistic and higher resolution. Many applications, such as high definition TV (HDTV), 3D device and Internet video streaming are developed to fulfill the human desire. However, the massive data size and data loss are still the challenges for these applications. With the advances in video coding technology, the demand of high quality and high definition video encourages the development of next generation video coding standard, High Efficiency Video Coding (HEVC). In 2010, ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) formed a Joint Collaborative Team on Video Coding (JCT-VC) and has began working on the next generation video coding standard HEVC. Many advanced techniques and enhanced coding tools are proposed in HEVC. In this thesis, we analyze and design the algorithm and hardware architecture of non-deblocking loop filter in HEVC. The non-deblocking loop filter aims to decrease the distortion between original pictures and reconstructed pixels. Sample adaptive offset and adaptive loop filter are two newly adopted tools in HEVC. The non-deblocking loop filter has 5\% coding efficiency gain; nevertheless, the cost is high complexity. In addition, the algorithm of non-deblocking loop filter is not hardware friendly. In order to implement the non-deblocking loop filter on hardware and reduce the complexity, we propose many techniques and hardware architecture. First, we propose many simplifications on SAO and ALF, especially on ALF. We show that much of the hardware resource can be saved yet keeps the video quality and coding performance. Second, we propose unified non-deblocking loop filter flow, two-stage non-deblocking loop filter architecture and LCU level-D data reuse to implement the non-deblocking loop filter on hardware. The proposed hardware architecture reduces 75\% of external memory access bandwidth, 99.9\% of memory usage and more than 40\% of hardware computation resource with only 1.29\% of coding efficiency loss. Based on the proposed algorithm and hardware architecture design, a worldwide first non-deblocking loop filter of HEVC standard hardware with 1.49G pixels/s throughput under the specification Ultra-HD $7680 imes4320$, 30fps is achieved.
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Pan, Yu-Nan, and 潘宇男. "Highly Efficient Motion Estimation and Deblocking Filter Architecture Design of H.264 Encoder." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60687301533829892282.
Full textAbstract:
博士國立中央大學
電機工程研究所
99
There are many attractive features for the upcoming video coding standard MPEG-4 AVC/JVT/H.264. However, the attractive features within H.264 are hard to design for real-time implementation. In previous works, most researches focus on the achievable specification such as mobile TV and HDTV. They concentrate about how to meet the video specification and memory bandwidth. Generally, there are two solutions to achieve the targets. One is Application Specification Integrated Circuits (ASIC), and the other one is using pure processor such as ARM or DSP. In this thesis, we propose high efficient Motion Estimation (ME) and deblocking filter architecture design using on power aware H.264 encoder. In the first part, we propose a speed-improve ME algorithm and a high efficiency architecture design. ME in H.264 employs seven permitted block sizes to improve the rate-distortion performance. This novel feature achieves significant coding gain over coding a macroblock (MB) using the fixed block size. However, ME is computationally intensive with the complexity increasing linearly to the number of the allowed block sizes. A high performance hybrid ME algorithm for H.264/AVC is proposed first. The hybrid ME algorithm used the proposed mode decision algorithm, Edge Information Mode Decision (EIMD), which is used the edge information to decide the best block mode of the seven modes and combining with the proposed Predict Hexagon Search (PHS). By using the proposed ME algorithm, the computational complexity has a huge reduction and thus it is suitable for high resolution applications such as HDTV (1920×1080) or QFHD (3840×2160). For the tested three real movies, the proposed algorithm can speedup about 300~405 times comparing with the full search of JM10.2. Compared with other popular fast algorithms, the proposed algorithm can has about 3~247 times of speedup ratio. After the ME algorithm is developed, an architecture for a combined fast motion estimation algorithm with the PHS and the EIMD is proposed. The proposed architecture applies a large search range and low operation frequency as compared with other popular ME architectures. The proposed architecture only needs 19.4 MHz operating frequency to achieve real time execution for the general specification of the SDTV (720×480) used with four reference frames and the search range of 256×256. The proposed architecture only requires 116.6 MHz operating frequency to achieve real time execution for the ultra high specification of the QFHD (3840×2160) used with one reference frame and the search range of 256×256. The gate count of the proposed architecture is 300K, and the memory usage is 12.6KB. Second, we propose a new processing order and the architecture design for deblocking filter. The proposed processing order, double-cross processing order, is effectively constructed by a parallel flow to improve processing speed and reduce memory access. Moreover, the proposed architecture can save about 38-80% of memory access as compared with other designs. Based on this high efficient architecture, the processing performance can be enhanced, and the operation frequency for standardized video specifications can be reduced. For the general video specification HDTV1080p (1920?1080 @30fps), the operation frequency of the proposed architecture is only 11.5 MHz. For the high resolution QFHD specification (3840?2160 @30fps), the operation frequency of the proposed architecture is only 46.6 MHz. The implementation result is about 20.14K gates, and the memory requirement is 64?32 bits. The power dissipation for QFHD specification is 7.7 mW at 46.6 MHz operating frequency. For the whole H.264 encoder, we propose a HW/SW co-design scheme which uses our pervious proposed ME and deblocking filter machines. At final, we propose a power aware scheme for the whole H.264 encoder. The proposed power aware design can save about 9%~87% of power consumption while the power budget is used.
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Cheng, Chao-Chung, and 鄭朝鐘. "Algorithm and Architecture Design for H.264/AVC Deblocking Filter and Intra Coding." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/69750157922721217505.
Full textAbstract:
碩士國立交通大學
電子工程系所
93
Digital video technology has played an important role in our daily life. With the evolution of video technology coding efficiency has been greatly improved. H.264/AVC is the latest international video coding standard that can save 39%, 49%, and 64% of bit-rates in comparison with MPEG-4, H.263, and MPEG-2, respectively. However, this efficiency comes with the cost of much higher computational complexity than previous standards due to the complex coding approaches and mode decision techniques. Thus, how to design high performance functional units and reduce computational complexity without too much degradation in coding efficiency are very important topics. In this thesis, we have three contributions for the H.264/AVC design, architecture design of the deblocking filter, a fast intra prediction algorithm, and an architecture design of intra coding in H.264/AVC. Deblocking filter is an important component of H.264/AVC to reduce the blocking effect and to improve the video quality. It is both computational and memory extensive. In this thesis, two different architecture of deblocking filter are proposed. The computing flow is reordered for efficient data reusability and high throughput while maintain standard compatibility. In the first version, gate count is greatly reduced by simple control unit, and internal memory is also reduced to 50% of that in the previous design. In the second version, the proposed architecture can reduce 90% of internal memory and achieve higher throughput than others. Intra prediction, which uses the information of spatial correlation to prediction the data to be encoded, is an important tool of intra frame coding. In this thesis, we propose a simple fast three step algorithm. The algorithm uses the directional relationship of prediction modes to skip the modes with less probability. Thus, the proposed algorithm can complete the 4x4 intra prediction by only examining six modes instead of nine modes in the full search algorithm. The simulation result shows that the proposed algorithm can maintain similar PSNR quality to that in the full search algorithm with 33% of computation reduction of intra prediction process and only 1% of bit-rate increase. Finally, a hardware oriented algorithm of intra coding and its architecture are proposed. We save the complex and hardware costly plane mode, which occupies the biggest area in the intra prediction unit in the intra coding and improve the coding efficiency with the enhanced cost function. With well designed high performance functional unit and computing schedule, the proposed architecture can easily support real-time intra coding of HDTV 1280x720@30fps video application when clocked at 117.28MHz. In brief, our contribution to H.264/AVC video coding system is in three parts. The first contribution to the deblocking filter architecture can accelerate the deblocking process. The second contribution to the fast intra coding algorithm can reduce the computational complexity of intra prediction. The final contribution to the intra coding architecture can speed up the computation of intra frame coding.
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Καβρουλάκης, Νικόλαος. "Ανάπτυξη αρχιτεκτονικών διπλού φίλτρου και FPGA υλοποιήσεις για το H.264 / AVC deblocking filter." Thesis, 2013. http://hdl.handle.net/10889/6033.
Full textAbstract:
Αντικείμενο της παρούσας διπλωματικής εργασίας είναι η παρουσίαση και η μελέτη ενος εναλλακτικού σχεδιασμού του deblocking φίλτρου του προτύπου κωδικοποίησης βίντεο Η.264. Αρχικά επεξηγείται αναλυτικά ο τρόπος λειτουργίας του φίλτρου και στη συνέχεια προτείνεται ένας πρωτοποριακός σχεδιασμός με χρήση pipeline πέντε σταδίων. Ο σχεδιασμός παρουσιάζει σημαντικά πλεονεκτήματα στον τομέα της ταχύτητας (ενδεικτικά εμφανίζεται βελτιωμένη απόδοση στην συχνότητα λειτουργίας και στο throughput). Αυτό πιστοποιήθηκε από μετρήσεις που έγιναν σε συγκεκριμένα fpga και επαλήθευσαν τα θεωρητικά συμπεράσματα που είχαν εξαχθεί.The standard H.264 (or else MPEG-4 part 10) is nowadays the most widely used standard in the area of video coding as it is supported by the largest enterprises in the internet (including Google, Apple and Youtube). Its most important advantage over the previous standards is that it achieves better bitrate without falling in terms of quality. A crucial part of the standard is the deblocking filter which is applied in each macroblock of a frame so that it reduces the blocking distortion. The filter accounts for about one third of the computational requirements of the standard, something which makes it a really important part of the filtering process. The current diploma thesis presents an alternative design of the filter which achieves better performance than the existing ones. The design is based in the use of two filters (instead of one used in current technology) and moreover, in the application of a pipelined design in each filter. By using a double filter, exploitation of the independence which exists in many parts of the macroblock is achieved. That is to say, it is feasible that different parts of it can be filtered at the same time without facing any problems. Furthermore, the use of the pipeline technique importantly increases the throughput. Needless to say, in order for the desired result to be achieved, the design has to be made really carefully so that the restrictions imposed by the standard will not be failed. The use of this alternative filter design will result in an important raise in the performance. Amongst all, the operating frequency, the throughput and the quality of the produced video will all appear to be considerably risen. It also needs to be mentioned that the inevitable increase of the area used (because of the fact that two filters are used instead of one) is not really important in terms of cost. The structure of the thesis is described in this paragraph. In chapter 1 there is a rather synoptic description of the H.264 standard and the exact position of the deblocking filter in the whole design is clarified. After that, the algorithmic description of the filter follows (Chapter 2). In this chapter, all the parameters participating in the filter are presented in full detail as well as the equations used during the process. In the next chapter (chapter 3), the architecture chosen for the design is presented. That is to say, the block diagram is presented and explained, as well as the table of timings which explains completely how the filter works. The pipelining technique applied in the filter is also analyzed and justified in this chapter. In the next chapter (chapter 4), every structural unit used in the current architecture is analyzed completely and its role in the whole structure is presented. Finally, in chapter 5, the results of the measurements made in typical fpgas of Altera and Xilinx are presented. The results are shown in table format whereas for specific parameters diagrams were used so that the improved performance of the current design compared to the older ones that are widely used, becomes evident.
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Lin, Yuan-Chun, and 林元淳. "A Two-Result-Per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96885405309303306342.
Full textAbstract:
碩士國立清華大學
資訊工程學系
95
We propose a high-performance hardwired Deblocking Filter (DF) for H.264/AVC video decoding. To fulfill the demand of ultra high throughput for QFHD (4x Full 1080HD), we optimize processing cycle, external memory access and working frequency of our architecture. Our Two-Result-Per-Cycle edge filter achieves near optimal processing cycle. It takes only 48 clock cycles to filter a macroblock in best case and 100 in worst case. Furthermore, it can save most unnecessary off-chip memory traffic with efficient on-chip memory. Our circuit supports skip mode to further reduce processing cycles and off-chip memory access in inter-predicted frame. Also it employs a 5-stage pipelined, and hardware-shared dual-edge-filter to generate two filtering results every cycle. Running at 195 MHz, it can support QFHD @ 60fps application.
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Tsai, Ming-Chih, and 蔡明志. "A Parameterized In-loop Deblocking Filter IP for H.264 BP/MP Video Coding." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/90905793227718476134.
Full textAbstract:
碩士國立中正大學
資訊工程所
93
The demands on applications of multimedia video coding are getting widespread, such that the output image qualities after decoding are becoming higher. MPEG-4 AVC/H.264 is the latest video coding standard, and the performance is far higher than the previous video coding standards. However, due to complex encoding technology and mode selection, the operation complexity is also far higher than the previous standards. In this thesis, we propose a key technology to maintain good image quality for H.264 high compression ratio, which is called In-loop Deblocking Filter IP (ILDF IP), and according to its complex algorithm and filter flow to optimize it further. Different from MPEG-4 and H.263 standards, deblocking filter has become the essential module of the H.264 encoder/decoder flow for H.264 specification. Therefore, how to eliminate blocking signal has become an indispensable link to maintain image quality for future high compression ratio of video decoding. High operation complexity and high memory bandwidth of deblocking filter occupies one-third of total operation amount. However, the proposed IDLE IP design can speedup the operation rate of In-loop Daglocking Filter efficiently, and can reduce the memory usage and save unnecessary bandwidth waste efficiently. We adopt pipeline hardware architecture design to speedup filter performance efficiently which is different from H.264 JM. We adopt special raster scan order of horizontal and vertical filter interleave to save memory efficiently up to 60%, and thus reduce hardware cost. Moreover, this IP can support ILF function needed by H.264 baseline profile and main profile, and support filter process of progressive and interlaced video image at the same time. In IP verification, this IDLE IP has been integrated into our own developed H.264 video decoder system for system functionality verification. In this thesis, we develop an In-loop Deblocking Filter IP to maintain image quality efficiently after decoding and provide a better choice for speeding up multimedia video high quality demands.
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葉再傳. "A Power-efficient and High-throughput Deblocking Filter Hardware Architecture for H.264/AVC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22102656835675699880.
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Huang, Yu-Sheng, and 黃毓生. "High-Performance Deblocking Filter Realization Using Fast Boundary-Strength Technique for H.264 Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/95384090459376261487.
Full textAbstract:
碩士國立東華大學
電機工程學系
94
Recently, digital video technology has played an important role in our daily life. With the evolution of video technology coding efficiency has been greatly improved. In various video coding standards, the block-based video coding cooperating with block transform and block motion compensation are the most widely adopted way to reduce the data redundancy, where H.264/AVC is one of the most important and popular video standards. The purpose of video coding standards is to reduce the data correlations for achieving higher compression efficiency by using the block transform and block motion compensation approaches. However, the most annoying artifact known as the blocking artifact also comes into existence. In order to remove the blocking artifact and improve the coding performance simultaneously, deblocking filter acts an important component of H.264/AVC to reduce the blocking artifact and improve the video quality. This thesis proposes a fast deblocking boundary-strength (FDBS) algorithm to effectively realize the high-performance deblocking filter. Simulation results show that about 0.21 dB PSNR improvement and 3.78 % bit-rat saving can be achieved. Also, the hardware design of the deblocking filter based on the proposed FDBS algorithm using the Verilog HDL coding is presented here. HDL realization and FPGA verification reveal that only 12.5 % gate counts are needed for saving about 25.6 % filtering-clock/macro-block. The physical chip design and comparisons with other studies really express the excellent performance of the proposed deblocking filter design.
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Chung, Hua-chang, and 鍾華倉. "Low Power Architecture Design and Hardware Implementations of Deblocking Filter in H.264/AVC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/74342801180983599219.
Full textAbstract:
碩士國立中央大學
通訊工程研究所碩士在職專班
98
An adaptive in-loop deblocking filter (DF) is standardized in H.264/AVC in order to reduce blocking artifacts and improve compression efficiency. This thesis proposes the low power DF architecture with the hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism in filtering the horizontal edges that not only reduces power consumptions but also saves the filtering orders up to 100 clock cycles per macroblock. In addition, our architecture utilizes extra buffers to store the temporary data without affecting the standard-defined data dependency by adjusting a reasonable strategy of edge filter order to enhance the reusability of intermediate data. Then, the system throughput can be improved, and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved while comparing with Parlak’s design ([19]). Furthermore, the proposed architecture is implemented on 0.18μm standardized cell library, which consumes 19.8 K gates at a clock frequency of 200 MHz which is competitive in the hardware cost comparing with other state-of art literatures.
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Lin, Yan-Cheng, and 林彥呈. "A Speed up Deblocking Filter for H.264/AVC BP/MP/HP Video Coding." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/43182659601434026851.
Full textAbstract:
碩士逢甲大學
資訊工程所
98
H.264/AVC is the next generation video compression standard, although it exhibits the high quality video, but it made another serious problem about high computation complexity. Because of the deblocking filter need to filter almost whole picture in the video, the deblocking filter occupies nearly one-third computation in the H2.64/AVC codec. So how to improve the performance of deblocking filter is a topic in H.264/AVC. We proposed two methods to speed up the deblocking filter. In order to reduce computation complexity in the Bs threshold decision of deblocking filter and easier to implement in hardware, it is necessary to amend the algorithm of deblocking filter, then using the FPGA and HDL language to accomplish the method we proposed. Through the result verification, it can improve the performance of debloking filter and support the H.264/AVC BP/MP/HP
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Yeh, Chun-Hsien, and 葉俊顯. "A High-Performance Adaptive Deblocking Filter SIP Design for 6k×4k H.264/SVC Decoder." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22964529949680845915.
Full textAbstract:
碩士逢甲大學
電子工程所
97
Deblocking filter (DBF) is one of the most significant module of an H.264 decoder. The literature shows that more than 1/3 of computation complexity and power consumption is occupied by the DBF. Besides, achieving real-time performance requirement of high-end application is challenging. Hence, we propose a novel high throughput rate quadruple-edge filter (QEF) SIP core for H.264 decoding/SVC targeting at 6k (6000×4000) applications. This proposed work was only 48 cycles to process one macroblock (MB) of deblocking filtering. The processing performance significantly outperforms the previous design from 2 times to 16 times. Interleaved memory is adopted to avoid data hazards and improved data traffic. For application level evaluation using application target index outperforms the previous works from 3 times to 26 times. As for evaluating the hardware efficiency, this work outperforms the previous works from 42% to 87% base on the index of Cycle and Area Product (CAP). The proposed design has been implemented with the TSMC 0.18μm 1P6M CMOS technology. The total number of logic gate counts is 40k, and maximum frequency is 166MHz. This design can achieve real-time processing requirement of 6k (6000×4000 pixels/frame)@30fps high resolution video applications at 135 MHz operation frequency. The proposed design has been passed the nLint procedure check (Check coding style) and offer the chooses to the users which HDL code can be synthesized and six application target arguments (720p, 1080HD, 4kx2k, 2540p, 5k, 6k), so that the design of the SIP system is more conducive to the integration and the portability of IPs.
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Chien, Cheng-an, and 簡呈安. "An H.264/VC-1/AVS In-Loop Deblocking Filter supporting High-Resolution Video Decoding." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/29679202029944325399.
Full textAbstract:
碩士國立中正大學
資訊工程所
96
This thesis presents a high throughput VLSI architecture for multi-standard in-loop deblocking filter (ILF) supporting to H.264 baseline/main/high profile (BP/MP/HP), AVS, and VC-1 simple/main/advanced profile (BP/MP/AP) video decoding targeted at HDTV applications. We develop a buffer management scheme, and an integrated 4x4/8x8 1-D filter to process the various coding tools in multi-standard deblocking filter for supporting H.264 MP/HP, AVS, and VC-1 AP, such as interlace frame (frame/field) coding, Picture Adaptive Frame/Field (PAFF) coding, MacroBlock Adaptive Frame/Field (MBAFF) coding, and 8x8 transform coding. In particular, we adopt two local buffers to store the reference MB pair data and reschedule the internal pixels when switching the filtering operations on the horizontal and vertical edges without writing them out to the external memory. Adopting TSMC 0.13μm CMOS technology, we implement the proposed design at the cost of 38.4K gates and 672 bytes of local memory when operating at 225 MHz. Moreover, the proposed design achieves the data throughput rate of 260 cycles per MB in average, which meets the real-time processing requirement for 3672x1536(2.39:1) (3680x1536@30fps) video decoding.
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Chen, Yen-Jen, and 陳延任. "Efficient VLSI architecture with Low-memory cost for Deblocking Filter used in H.264/AVC." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/01776360124450825893.
Full textAbstract:
碩士淡江大學
電機工程學系碩士班
94
In video coding systems such as MPEG-1, MPEG-2, MPEG-4, H.261, H.263 and H.264, the Block-based Discrete Cosine Transform (BDCT) is widely used. The drawback of BDCT is the coarse quantization of the transform coefficients that can cause visually disturbing discontinuities. In H.264/MPEG-4 AVC video coding standard, the deblocking filter has been integrated into the video CODEC. The filtered frames are used as reference frames for motion compensation. Compared with the post-deblocking-filter, the in-loop deblocking filter provides a certain level of quality, without an extra frame buffer, and can improve both objective and subjective qualities of the video stream. The deblocking filtering process needs complex operation, and it may take of the decoding time. In order to increase the efficiency a hardwareized deblocking filter is necessary. We proposed an efficient deblocking filter in the thesis. Compared with the previous deblocking filters, the proposed architecture based on skewed memory adopts a 2-dementional parallel memory access without transforming the register memory. The new scheme can increase the throughput of deblocking filtering, and reduce the hardware cost.
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Chou, Yu-Lin, and 周育霖. "A Hardware Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC Video Coding." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/57046299370446132735.
Full textAbstract:
碩士國立中興大學
電機工程學系所
100
In this thesis, a hardware sharing architecture to perform the multi-standard deblocking filter that support VP8 and H.264/AVC is proposed. First, a reorganization of deblocking filter is used to derive a common architecture which is suitable for H.264/AVC and VP8. The proposed design is then reused for the whole filtering. To further reduce the computational complexity, highly sharing architecture is also presented. In order to save the size of the on-chip memory, a memory sharing architecture of the deblocking filter and motion compensation is introduced. We also reorganize the processing order of filtering to reduce the total on-chip memory size. According to the experimental results, the adopted hardware sharing architecture saves 63.3% of shifters, 77.4% of adders and 100% of multipliers totally. The overall PSNR drops less than 1% on the VP8 decoder for low complexity applications. Finally, a hardware implementation using TSMC 0.18 μm cell library is performed. The clock frequency of the proposed hardware is working at 130 MHz to perform deblocking filter for supporting Full HD 1080P@30fps. The implementation results show that the gate count of this architecture adopted on VP8 and H.264/AVC video codec system is 43.2K.
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Chang, Shihchien, and 張世騫. "ARM-based Platform Design for H.264/MPEG-4 AVC Decoder and Accelerator for Deblocking Filter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/24560708128016922471.
Full textAbstract:
碩士國立交通大學
電子工程系所
93
In this thesis, we present a baseline H264/MPEG-4 AVC decoder based on an optimized platform-based design methodology. In our platform, we employ the ARM microprocessor as the CPU core due to its high performance, low cost, and wide application. Besides, the Advanced Microcontroller Bus Architecture (AMBA) is integrated into our system as the on-chip bus due to its high performance and flexibility. To improve our system, we jointly optimize the software and hardware in the decoder. Also, we propose a macroblock-level pipelining architecture to achieve the synchronization of the software and the dedicated hardware co-processors. In our hardware design, three dedicated accelerators of deblocking filter, motion compensation and inverse transform, which are the most computationally intensive modules, are realized. Specifically, in the architecture design of deblocking filter, we proposed an adaptive transfer scheme and a platform-based bus-interleaved architecture. As considering the high bandwidth usage of bus for deblocking filter, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfers so as to efficiently use the bus bandwidth. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transfer and filtering operation in parallel. As compared to the state-of-the-art designs of deblocking filter, our scheme offers up to 7x performance improvement. To compare the overall decoding performance, our experiments show that the throughput of H.264 reference software of JM6.0 decoder can be improved by 9 to 16 times. Finally, our proposed platform system can be easily applied in the system-on-chip design. Also, our proposed hardware architectures are suitable for low-cost and real-time applications.
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Wei-Che, Chiou. "A High Performance and Cost Effective Deblocking Filter Architecture with Memory Interleaving Organization for H.264/AVC Applications." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0005-0308200617104000.
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Chiou, Wei-Che, and 邱偉哲. "A High Performance and Cost Effective Deblocking Filter Architecture with Memory Interleaving Organization for H.264/AVC Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/18937900383489686157.
Full textAbstract:
碩士國立中興大學
電機工程學系所
94
Traditional block-based video coders such as H.261, H.263, H.264/AVC and MPEG-1/2/4 suffer from annoying blocking artifacts when they are applied in low bit-rate coding because inter block correlation is lost by block-based prediction, transformation, and quantization. In order to overcome the blocking artifact problem, a filter is applied to each decoded macroblock to reduce blocking distortion. This thesis presents a high performance and cost effective deblocking filter architecture with memory interleaving organization for MPEG-4 AVC/H.264 video standard. Many literatures and the results of the chip implementation show that the memory organization dominates the hardware cost and the throughput rate of the deblocking filter. In order to increase the throughput, we propose the memory interleaving techniques to easily arrange data in the on-chip memory. We also utilize the hybrid scheduling data flow for 2-D processing order to reduce the total on-chip memory size. According to proposed memory interleaving organization and hybrid scheduling data flow, our architecture only utilizes the 55% of the traditional memory size to speed up the throughput and to reduce the bus memory bandwidth. The experimental results show that the hardware cost and memory size of the proposed architecture is smaller than other existing architectures, and the proposed architecture has greater throughput than other familiar architectures. We implement the architecture with TSMC 0.18 μm cell library, and the maximum clock frequency we can achieve is 100 MHz. In other words, we can achieve 4XGA (2048×1536) @30 frames/sec when we set the clock frequency to be 83 MHz.
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Chen, Chein-Ting, and 陳建廷. "Design and implementation of overlap smoothing and dual-mode deblocking filter for H.264/AVC and VC-1 applications." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/08762638077387908928.
Full textAbstract:
碩士國立中興大學
電機工程學系所
97
In this thesis, a VLSI architecture of the overlap transform and duel-mode deblocking filter is proposed for HD1080p applications. This deblocking filter architecture can support both H.264/AVC and VC-1 video standards. In addition, the overlap smoothing transform also combines with the deblocking filter while VC-1 standard is performed. Many literatures and the results of the chip implementation show that the memory organization dominates the hardware cost and the throughput rate of the deblocking filter. In order to increase throughput and to reduce on-chip memory and memory bandwidth, we propose the memory interleaving techniques to arrange data in the on-chip memory and to efficiently access the data in both horizontal and vertical filters. We also utilize the hybrid schedule for the two-dimensional (2-D) processing order to reduce the total on-chip memory size. According to our proposed memory interleaving organization, the memory interlacing configuration and the hybrid schedule of the 2-D processing order can speed up the throughput and reduce the memory bandwidth efficiently. Finally, we implement our architecture by using TSMC Artisan 0.18µm cell library, and the clock frequency of the proposed architecture is 62.5-MHz. The implementation result shows that the core size is 880X880 um2. Because of the duel-mode character, our architecture can be applied to multiple encoders and decoders.
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Wu, Jun-xiong, and 吳俊雄. "ASIP on Multi-Processor Architectures for Deblocking Filters." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/12541925851465488436.
Full textAbstract:
碩士逢甲大學
資訊工程所
100
The deblocking filters are used to remove the discontinuous phenomenon in the H.264/AVC technology so that the image quality may be improved in a high compression rate. However, the deblocking filter occupies the one-third computation overhead of the H.264/AVC codec. This thesis proposes application-specific instruction-set multi-processor architectures to improve the deblocking filter performance with slight design and hardware overheads. Firstly, we partition the input data of the deblocking algorithm, and then assign each partition to individual processor to get parallel computing benefits. The application-specific instructions are selected for each partition of codes to increase performance.
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Chao, Yi-Chih, and 趙億智. "A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filters." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/78100923569587828532.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
94
In this thesis, we propose a high throughput and data reuse architecture of de-blocking filters for H.264/AVC. We modify the filtering order to speed up the deblocking filter processes. With this filtering order, there are two 4×4 register arrays needed for data reuse. In the arrangement of pixels in SRAMs, the GOP format is designed to achieve the fast access pixels instead of COP or ROP methods. Further, the two pipelined stages are realized in 1-D filter, and the fewer logic gate counts are implemented according to the characteristics of de-blocking filter processes. There are two SRAMs, 144×32 bits single-port SRAM and 16×32 bits two-port SRAM, exploited in this design. The simulation results show the total number of logic gate counts is 16.6k, and the core size of layout is 184,900 μm2. However, it needs 228 clock cycles to de-block one macroblock. This proposed architecture can be achieved with the clock frequency at 100 MHz. In other words, it can process the real-time deblocking of 4XGA (2048×1536) picture with 30 frames per second when the clock frequency is set to 85 MHz.
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Sheng-Ho, Wang. "H.264/AVC coding performance enhancement via incorporating pre-process with perceptual-based in-loop deblocking filters." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2007200515230800.
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Wang, Sheng-Ho, and 王盛禾. "H.264/AVC coding performance enhancement via incorporating pre-process with perceptual-based in-loop deblocking filters." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/58724374642745736067.
Full textAbstract:
碩士國立臺灣大學
資訊工程學研究所
93
Block-based video coding cooperating with block transform and block motion compensation is the most widely adopted way to reduce the data redundancy in various video coding standards. Although the goal of de-correlations is achieved effectively by this way, the most annoying artifact known as the blocking effect also comes into existence. To both remove this artifact and improve the coding performance simultaneously, the latest video coding standard, H.264/AVC, enforces the deblocking filters inside its coding loop. In the design of deblocking filters of H.264/AVC, one pair of parameters, OffsetA and OffsetB, are provided, which allow the adaptive control of the deblocking strength in slice level. Thus, finding out better parameters for conducting the deblocking process of H.264/AVC is capable of improving visual quality of reconstructed video. Identifying which edges belong to blocking effect relies on perceptual judgment of human beings. In fact, this subjective assessment may not exactly match existing objective measurements and high PSNR does not always stand for less blocking artifacts. In this thesis, we introduce two new criteria for measuring the blocking distortion by analyzing the perceptual difference between the source and the reconstruction. The experimental results validate the proposed approaches, especially in subjective issues. On the other hand, another implicit advantage of deblocking is ignored by most encoders. It is observed that different coded images may have the same output after applying the mandatory deblocking process. Based on this observation, we integrate this concept into H.264/AVC. For eight different deblocking modes, we first derive the equations to change the input image but do not affect the final output reconstruction. By choosing those of less bitrate consumption, the proposed pre-processing approach successfully improves video coding performance. Combing advantages of both pre-process and post-process, an enhanced H.264/AVC coding system is implemented which maximizes the effect of deblocking filters. The experimental results demonstrate its improvements for H.264/AVC codec both in objective and subjective evaluations