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Dissertations / Theses on the topic 'Debugger'

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Published: 4 June 2021
Last updated: 26 April 2022

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1

Pope, Bernard James. "A declarative debugger for Haskell /." Connect to thesis, 2006. http://eprints.unimelb.edu.au/archive/00003290.

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2

Johnson, Stephen Lee. "TeaBag: A Debugger for Curry." PDXScholar, 2004. https://pdxscholar.library.pdx.edu/open_access_etds/2663.

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This thesis describes TeaBag, which is a debugger for functional logic computations. TeaBag is an accessory of a virtual machine currently under development. A distinctive feature of this machine is its operational completeness of computations, which places novel demands on a debugger. This thesis describes the features of TeaBag, in particular the handling of non-determinism, the ability to control nondeterministic steps, to remove context information, to toggle eager evaluation, and to set breakpoints on both functions and terms. This thesis also describes TeaBag's architecture and its interaction with the associated virtual machine. Finally, some debugging sessions of defective programs are presented to demonstrate TeaBag's ability to locate bugs. A distinctive feature of TeaBag is how it presents non-deterministic trace steps of an expression evaluation trace to the user. In the past expression evaluation traces were linearized via backtracking. However, the presence of backtracking makes linear traces difficult to follow. TeaBag does not present backtracking to the user. Rather TeaBag presents the trace in two parts. One part is the search space which has a tree structure and the other part is a linear sequence of steps for one path through the search space.
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3

Schütze, Lars. "Implementing a Debugger for Dresden OCL." Bachelor's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-118599.

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Although originally designed as an extension for the Unifi ed Modeling Language (UML), today, the Object Constraint Language (OCL) has been broadly adopted in the context of both UML and other modeling and domain-specifi c languages. However, appropriate tooling, supporting modelers and software developers on using OCL is still scarce and lacks important features such as debugging support. As OCL constraints are likely to become rather complex for real world examples, it is hard to comprehend the in uence of single OCL expressions and subexpressions on the result of a completely evaluated OCL constraint in the context of speci fic constrained objects. Therefore, debugging is of topmost importance for both constraint comprehension and maintenance. Thus, the major task of this work is to develop a graphical debugger integrated into Dresden OCL and the Eclipse Integrated Development Environment (IDE) to fill this gap.
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4

Wagner, Christina. "Anforderungen an einen Debugger für Softwaregeneratoren." Bachelor's thesis, Universitätsbibliothek Leipzig, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:15-qucosa-202633.

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Eine wichtige Aufgabe bei der Softwareentwicklung ist das Auffinden von Fehlern und das Verstehen ihrer Ursachen. Zur Unterstützung dieser Aufgabe gibt es zahlreiche De-bugger. Bei der Nutzung von Softwaregeneratoren benötigt man zum Debuggen spezielle Informationen. In dieser Arbeit werden Anforderungen an einen Debugger für Software-generatoren definiert. Dazu werden zunächst strukturell ähnliche Softwaregeneratoren auf ihre Debugger untersucht und grundsätzliche Debuggertypen identifiziert. Aus diesen werden 15 Anforderungen formuliert, die der hier beispielhaft betrachtete Softwaregener-ator erfüllen soll. Anschließend erfolgen eine Verallgemeinerung der Ergebnisse und eine kurze Diskussion der Umsetzung auf der Plattform JetBrains MPS.
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5

Chelliah, M. "A Compiler and Symbolic Debugger for Occam." Thesis, Indian Institute of Science, 1989. http://hdl.handle.net/2005/77.

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We have implemented Occam, a parallel programming language, on a uniprocessor machine (MC-68020 based HORIZON I11 running on UNIX system V.2) with simulated concurrency. Occam is a descendant of CSP with a few convenient modifications like channels used for communication and procedures. Two additions to the original language, i.e., output guards and recursion have been proposed. Front end of the compiler was developed using LEX and YACC. An innovative code generator, generator based on tree pattern matching has been used to generate the back end of the compiler, which generates efficient MC-68020 assembly code. A kernel for process administration is the runtime support provided. It has been developed entirely in ' C ' and made available as a library. This is linked with the assembly module to generate the executable version of the input Occam program. We have also interfaced our Occam compiler with Unix system V.2 source level debugger 'Sdb' so as to provide debugging support for Occam programmers. Issues involved in parallel debugging have been investigated and those demanding minimum effort have been incorporated in Occam debugger by modifying the runtime support of the uniprocessor implementation. Modifications to the uniprocessor implementation so as to make it run on a shared memory multiprocessor machine(HCL MAGNUM-P with four MC-68030 processors) are also discussed. The support provided by MAGNUM-P at the architecture and operating system levels is explained in detail. Our Occam compiler for the multiprocessor generates code, but the generated code has not been tested since the machine is not yet ready.
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6

Ni, Wayland 1982. "WSIM configurable digital signal processor simulator/debugger." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/16683.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaf 53).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
This M.Eng. Thesis presents a design and implementation of a full-featured configurable Digital Signal Processor (DSP) simulator/debugger. The user will be able to set configurations in order to model a specific architecture design. The simulator will have a command interpreter to listen to and process commands given by the user. When supplied with an assembly program, the simulator will allow the user to step through the execution of the program cycle by cycle, as well as calculate statistics like instruction, resource, and cache profiling. Some of the main features of the simulator are a multiply-accumulate unit, memory with direct and indirect offset addressing, and loop instructions.
by Wayland Ni.
M.Eng.
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7

Markusson, Christoffer. "Implementation of an application debugger for software in embedded systems." Thesis, Linköping University, Department of Computer and Information Science, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15539.

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Debugging applications that are running in embedded systems is becoming harder and harder due to the growing complexity of the systems. This is especially true for embedded systems that are developed for the automotive market.

To aid the debugging there are tools called debuggers. Historically, debuggers have been implemented by using a debug port to connect a software debugger running at the developer machine to dedicated on-chip debugging hardware. The problem with this approach is that it is expensive and that it is not possible to use it if the debug port on the system is not available.Therefore there is a demand for user-friendly debuggers that are not as expensive and require no extra hardware.

This report presents alternatives to debugging embedded systems. From these alternatives a completely software based debugger solution called monitor-based debugging is selected and acts as a foundation for an implementation that is described in the report. The implementation uses GNU Debugger (GDB) and its remote debugging capabilities to perform debugging.

The implemented debugger is evaluated by using it to debug applications that are running in a powertrain control unit in a modern truck. It is also compared to two commercial hardware based debuggers. In the evaluation it is found that the debugger functionalities and user-friendliness are on par with the commercial alternatives, but that it lacks some in its non-intrusive capabilities when comparing it with the high-end alternatives on the market.

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8

Nilsson, Sverker. "Heapy: A Memory Profiler and Debugger for Python." Thesis, Linköping University, Department of Computer and Information Science, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7247.

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Excessive memory use may cause severe performance problems and system crashes. Without appropriate tools, it may be difficult or impossible to determine why a program is using too much memory. This applies even though Python provides automatic memory management --- garbage collection can help avoid many memory allocation bugs, but only to a certain extent due to the lack of information during program execution. There is still a need for tools helping the programmer to understand the memory behaviour of programs, especially in complicated situations. The primary motivation for Heapy is that there has been a lack of such tools for Python.

The main questions addressed by Heapy are how much memory is used by objects, what are the objects of most interest for optimization purposes, and why are objects kept in memory. Memory leaks are often of special interest and may be found by comparing snapshots of the heap population taken at different times. Memory profiles, using different kinds of classifiers that may include retainer information, can provide quick overviews revealing optimization possibilities not thought of beforehand. Reference patterns and shortest reference paths provide different perspectives of object access patterns to help explain why objects are kept in memory.

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9

Manoh, Nadia, and Hamoud Abdullah. "Software debugging using the debugger SAM4E Xplained Pro." Thesis, Malmö universitet, Fakulteten för teknik och samhälle (TS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20090.

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Inbyggda system finns i nästan alla enheter som används i vårt dagliga liv, som exempelvis mobiltelefoner, kylskåp och bilar. En del enheter kan vara betydligt känsligare än andra, vilket innebär att en bugg som existerar i ett system kan orsaka skada, till och med förlust av människoliv, eller orsakar ingen skada alls. Mjukvarutestning och mjukvarufelsökning genomförs för att reducera buggar i ett system.Utbildningsprogrammet Datateknik och Mobil IT på Malmö universitet fokuserar inte på att undervisa mjukvarufelsökning med hjälp av felsökningsverktyg. Således presenterar denna forskning en felsökningslaboration skapat för studenter som går Datateknik och Mobil IT, som anses hjälpa studenterna att få kunskap i hur man använder felsökningsverktyget SAM4E Xplained Pro för att lokalisera buggar. Som ett resultat, utfördes felsökningslaborationen av fyra studenter varav 75 procent av buggarna hittades och åtgärdades.
Embedded systems are found in almost every device used in our daily lives, including cell phones, refrigerators, and cars. Some devices may be significantly more sensitive than others, meaning a bug appearing in a system could cause harm, even loss of human lives or cause no harm at all. To reduce bugs in a system, software testing and software debugging are performed.The Computer Science program at Malmö University does not focus on teaching software debugging using a debugger. Thus, this thesis presents a debugging lab created for Computer Science students, considered to help them gain knowledge in how to use the debugger SAM4E Xplained Pro to locate bugs. As a result, four students performed the debugging lab of which 75 percent of the bugs were found and remedied.
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10

Watson, Gregory R. (Gregory Richard). "The design and implementation of a parallel relative debugger." Monash University, School of Computer Science and Software Engineering, 2000. http://arrow.monash.edu.au/hdl/1959.1/8772.

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11

Zhang, Jing. "A visual performance debugger for Concordia Parallel Programming Environment." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape3/PQDD_0019/MQ47859.pdf.

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12

Wright, Jeremy Theard. "Python Semantic Investigator : an interactive debugger with reversible state." Thesis, Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/123012.

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This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis: M. Eng. in Computer Science and Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (page 43).
This thesis describes PSI (Python Semantic Investigator), a program designed to help students explore their code by allowing them to see the state of their program at any step along its execution. PSI enables them to move forwards or backwards freely along the timeline of their program. It also enables them to designate variable names or object IDs and jump back to the last time such a variable or object was modified. Doing so is intended to help novice students learn to debug more effectively.
by Jeremy Theard Wright.
M. Eng. in Computer Science and Engineering
M.Eng.inComputerScienceandEngineering Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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13

Fainter, Robert Gaffney. "AdaTAD - a debugger for the Ada multi-task environment." Diss., Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/54289.

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In a society that is increasingly dependent upon computing machinery, the issues associated with the correct functioning of that machinery are of crucial interest. The consequences of erroneous behavior of computers are dire with the worst case scenario being, conceivably, global thermonuclear war. Therefore, development of procedures and tools which can be used to increase the confidence of the correctness of the software that controls the world's computers is of vital importance. The Department of Defense (DoD) is in the process of adopting a standard computer language for the development of software. This language is called Ada¹. One of the major features of Ada is that it supports concurrent programming via its "task" compilation unit. There are not, however, any automated tools to aid in locating errors in the tasks. The design for such a tool is presented. The tool is named AdaTAD and is a debugger for programs written in Ada. The features of AdaTAD are specific to the problems of concurrent programming. The requirements of AdaTAD are derived from the literature. AdaTAD is, however, a unique tool designed using Ada as a program description language. When AdaTAD is implemented in Ada it becomes portable among all environments which support the Ada language. This offers the advantage that a single debugger is portable to many different machine architectures. Therefore, separate debuggers are not necessary for each implementation of Ada. Moreover, since AdaTAD is designed to allow debugging of tasks, AdaTAD will also support debugging in a distributed environment. That means that, if the tasks of a user's program are running on different computers in a distributed environment, the user is still able to use AdaTAD to debug the tasks as a single program. This feature is unique among automated debuggers. After the design is presented, several examples are offered to explain the operation of AdaTAD and to show that AdaTAD is useful in revealing the location of errors specific to concurrent programming.
Ph. D.
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14

Lami, Pietro. "Estensione di un debugger reversibile per Erlang con feature imperative." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/22157/.

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In un linguaggio reversibile, qualsiasi calcolo in avanti può essere annullato da una sequenza finita di passaggi all'indietro. Il calcolo reversibile è stato studiato nel contesto di diversi linguaggi di programmazione e formalismi. In questa tesi si estende il lavoro fatto nell'articolo "A Theory of Reversibility for Erlang". Inizialmente si presentata l'estensione della semantica formale dell'articolo con delle feature imperative. Dopo di che viene mostrata la semantica per il calcolo reversibile e vengono dimostrate le sue proprietà principali, inclusa la coerenza causale. Infine, viene aggiunto un operatore di rollback che può essere utilizzato per annullare le azioni di un processo fino a un determinato punto di controllo.
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15

Xin, Guang Greg. "Design and implementation of an ATM network card debugger, ATMNCD." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0006/MQ37670.pdf.

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16

MacDonald, Craig Lindsey Carleton University Dissertation Computer Science. "NodeView: a profiler/debugger for parallel computers using message passing." Ottawa, 1996.

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17

Špaček, Michal. "Ladicí nástroj pro víceprocesorový systém na čipu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2011. http://www.nusl.cz/ntk/nusl-412840.

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The Lissom project deals with the hardware-software co-design methodology. In this project, an integrated desktop environment for a design of multiprocessor systems on chip was developed. This environment can be used also for developing applications for multiprocessor systems. One part of the environment is a debugger that can be used to debug single core systems. In this thesis, a single processor debugger tool is described in detail and an extension to this tool is proposed and implemented based on the Nexus standard. The extended debugger allows debugging of multiprocessor systems.
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Lin, Chu-chung. "The design of a distributed debugger for action-based object-oriented programs." Diss., Georgia Institute of Technology, 1987. http://hdl.handle.net/1853/8205.

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19

Uzunsokakli, Mustafa Yavuz. "Design and impementation of a debugger for MC68020 based Educational Computer Board." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/25821.

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20

Chunawala, Shakil A. (Shakil Ahmed). "Creatr, a genergtic graphical distributed debugger with language support for application interfacing." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/34094.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 84-86).
by Shakil A. Chunawala.
M.S.
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21

Bricault, Gary S. "GSD : an interactive window-oriented debugger for the AT & T UNIX-PC /." Online version of thesis, 1989. http://hdl.handle.net/1850/10549.

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22

Hanono, Silvina Zimi. "InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11855.

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23

Scerpa, Daniel. "Debugging Reversibile." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2018. http://amslaurea.unibo.it/15470/.

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Per migliorare l'efficienza del processo di debug, nel corso degli anni, è cresciuta sempre di più l’idea di mettere, a disposizione del programmatore, un debugger che consentisse non solo, di fare un passo avanti nel codice, ma anche la possibilità di ripercorrerre all’indietro l’esecuzione del programma per ridurre i costi e i tempi nel sviluppare software.
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Hsu, Irving Shang-Yi 1967. "DEVS Monitor: An X Window system-based debugger for the DEVS-scheme simulation environment." Thesis, The University of Arizona, 1992. http://hdl.handle.net/10150/292071.

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An effective testing and debugging tool for simulation modeling must be able to extract the salient characteristics of simulation dynamics and present them in a clear and coherent manner, provide fine-grained control over the execution of simulation, and allow direct manipulation of model state to facilitate hypothesis construction and confirmation. We have designed DEVS Monitor to meet these goals. DEVS Monitor is designed around its graphical display of the dynamic behavior of simulation models. Because models in DEVS-Scheme are object-oriented and hierarchical in nature, DEVS Monitor is able to extrapolate from the structure and behavior of the computer model to the structure and behavior of the conceptual model. Specifically, DEVS Monitor represents a model graphically as a tree, and provides visual feedback to state changes and interaction between model components. We will also discuss other program visualization issues, and evaluate DEVS Monitor's performance.
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Roncuzzi, Davide. "Debugging reversibile di un frammento del linguaggio C." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/22804/.

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Questo elaborato descrive lo sviluppo di un debugger reversibile per un frammento del linguaggio C, mostrando come la funzione di reversibilità migliori l'efficienza della fase di debugging. Particolare enfasi è data alle strutture dati utilizzate sia per il debugger sia per il riconoscimento del linguaggio C. Infine, dopo aver spiegato brevemente la storia dell'applicazione della reversibilità ai debugger, ne viene spiegata nel dettaglio l'implementazione.
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Misra, Supratik Kumar. "Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/31153.

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Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test have gained more importance and 70 % of the design expenditure in on validation processes. Electronic Design Automation (EDA) tools play a huge role in the validation process with various verification and test tools. Their efficiency have a high impact in saving time and money in this competitive market. Direct Acyclic Graphs (DAGs) are the backbone for most of the EDA tools. DAG is the most efficient data structure to store circuit information and also have efficient backt traversing structure which help in developing reasoning/ debugging tools. In this thesis, we focus on two such EDA tools using graphs as their underlying structure for circuit information storage • Scan pattern Debugger for Partial Scan Designs • Circuit SAT Bounded Model Checkers We developed a complete Interactive Scan Pattern Debugger Suite currently being used in the industry for next generation microprocessor design. The back end is an implication graph based sequential logic simulator which creates a Debug Implication Graph during the logic simulation of the failing patterns. An efficient node traversal mechanism across time frames, in the DIG, is used to perform the root-cause analysis for the failing scan-cells. In addition, the debugger provides visibility into the circuit internals to understand and fix the root-cause. We integrated the proposed technique into the scan ATPG flow for industrial microprocessor designs. We were able to resolve the First Silicon logical pattern failures within hours, which would have otherwise taken a few days of manual effort for root-causing the failure, understanding the root-cause and fixing it. For our circuit SAT implementation, we replace the internal implication graph used by the SAT solver with our debug implication graph (DIG). There is a high amount of circuit unrolling in circuit SAT/ BMC (Bounded Model Checking) problems which creates copies of the same combinational blocks in multiple time frames. This allows us to use the repetitive circuit structure and club it with the CNF database in the SAT solver. We propose a new data structure to store data in a circuit SAT solver which results up to 90% reduction in number of nodes.
Master of Science
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Pavelka, Jan. "Nástroj pro usnadnění vývoje a testování PHP aplikací." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2009. http://www.nusl.cz/ntk/nusl-237475.

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The goal of this master's thesis is an introducing with tools for easy coding and debugging of PHP applications and to implement such tool on the basis of analysis of common requirements and specific requirements of IS VUT designers. The project includes an introduction with important ideas and terms referring to tool, analysis and specifications of requirements and design and implementation of final tool.
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Hons, Petr. "Rozšíření generického ladicího nástroje v projektu Lissom." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236020.

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This thesis deals with an introduction to debugging and debuggers. The thesis describes principles of the debugging information, especially the DWARF format and its Call Frame Information (CFI), that enables a debugger to visualize the call stack. Furthermore, extensions of the debugger used in the Lissom project were designed and implemented. These extensions added support for call stack visualization, history value storage and step return and step over commands.
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Wilczák, Milan. "Ladicí nástroj generických simulátorů mikroprocesorů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237257.

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Application specific instruction set processors become part of every day life although it's not always visible at first sight. During their development it's needed to somehow describe their architecture, instruction set and behavior. To make their developement worth, it's necessary to be able to create applications for these processors and during application development errors are always made. Debuggers serve to discover and help fixing them. This paper summarises some basic information to debugger development and describes implementation for processors created using the Lissom project.
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Thimmapuram, Sunethra. "Web-Delivered Assembly Language Interactive Training and its Sequence Identification for Software Reverse Engineering." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright151551307959276.

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Korvas, Pavol. "Rekonfigurovatelný ladicí nástroj na úrovni zdrojového kódu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236219.

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This mater's thesis deals with introducing principles of debugging and debuggers. The thesis examines in detail format of debugging information and it describes the design of debugger created within the project Lissom. Furthermore, the thesis also contains implementation of each designed part, which the debugger consists of. Last part of this thesis deals with testing of the implemented solution with two types of processor architectures and it also contains the conclusion of the results.
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Končický, Jaromír. "Využití dynamické analýzy kódu při zpětném překladu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236118.

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As a part of the Lissom project, a retargetable decompiler is being developed. Its main purpose is to decompile programs for a particular microprocessor architecture into a high-level programming language. In present, methods of dynamic code analysis are not used during decompilation. However, we can significantly improve the decompilation results by using these methods. Design of dynamic-analysis methods is the main task of this thesis. In this thesis, reverse engineering and Lissom decompiler are described. Furthermore, general dynamic analysis methods, such as instrumentation and emulation, are described. The information we can obtain by using dynamic analysis and its usage during decompilation is proposed.
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Šváb, Martin. "Virová analýza a reverzní inženýrství." Master's thesis, Vysoká škola ekonomická v Praze, 2014. http://www.nusl.cz/ntk/nusl-193214.

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Focus of this thesis is reverse engineering in information technology closely linked with the malware analysis. It explains fundamentals of IA-32 processors architecture and basics of operating system Microsoft Windows. Main part of this thesis is dedicated to the malware analysis, including description of creating a tool for simplification of static part of the analysis. In Conclusion various approaches to the malware analysis, which were described in previous part of the thesis, are practically demonstrated on unknown malware sample.
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Vogelsang, Stefan, Steffen Köhler, and Rainer G. Spallek. "Analyse von Test-Pattern für SoC Multiprozessortest und -debugging mittels Test Access Port (JTAG)." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200701007.

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Bei der Entwickelung von System-on-Chip (SoC) Debuggern ist es leider hinreichend oft erforderlich den Debugger selbst auf mögliche Fehler zu untersuchen. Da alle ernstzunehmenden Debugger konstruktionsbedingt selbst ein eingebettetes System darstellen, erwächst die Notwendigkeit eine einfache und sicher kontrollierbare Diagnose-Hardware zu entwerfen, welche den Zugang zur Funktionsweise des Debuggers über seine Ausgänge erschließt. Derzeitig ist der Test Access Port (TAP nach IEEE 1149.1-Standard) für viele Integratoren die Grundlage für den Zugriff auf ihre instanzierte Hardware. Selbst in forschungsorientierten Multi- Core System-on-Chip Architekturen wie dem ARM11MP der Firma ARM wird dieses Verfahren noch immer eingesetzt. In unserem Beitrag möchten wir ein Spezialwerkzeug zur Analyse des TAPKommunikationsprotokolles vorstellen, welches den Einsatz teurer Analysetechnik (Logik- Analysatoren) unnötig werden lässt und darüber hinaus eine komfortable, weitergehende Unterstützung für Multi-Core-Systeme bietet. Aufbauend auf der Problematik der Abtastung und Erfassung der Signalzustände am TAP mittels FPGA wird auf die verschiedenen Visualisierungs- und Analyseaspekte der TAPProtokollphasen in einer Multi-Core-Prozessor-Zielsystemumgebung eingegangen. Die hier vorgestellte Lösung ist im Rahmen eines FuE-Verbundprojektes enstanden. Das Vorhaben wird im Rahmen der Technologieförderung mit Mitteln des Europäischen Fonds für regionale Entwicklung (EFRE) 2000-2006 und mit Mitteln des Freistaates Sachsen gefördert.
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35

Geiger, Leif [Verfasser]. "Fehlersuche im Modell : modellbasiertes Testen und Debuggen / Leif Geiger." Kassel : Universitätsbibliothek Kassel, 2011. http://d-nb.info/101373873X/34.

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Hermanns, Christian [Verfasser]. "Entwicklung und Implementierung eines hybriden Debuggers für Java / Christian Hermanns." Münster : Verl.-Haus Monsenstein und Vannerdat, 2010. http://d-nb.info/101104448X/34.

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37

Ludewig, Ralf. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips /." Aachen : Shaker, 2006. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=014632870&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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38

Ludewig, Ralf [Verfasser]. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips / Ralf Ludewig." Aachen : Shaker, 2006. http://d-nb.info/118658789X/34.

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39

Da, Silva Fabio. "Correctness proofs of compilers and debuggers : an approach based on structural operational semantics." Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/13542.

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In this thesis we study the use of semantics-based formal methods in the specification and proof of correctness of compilers and debuggers. We use a Structural Operational Semantics as the basis for the specification of compilers and propose a notion of correctness based on an observational equivalence relation. We define program evaluation and a notion of evaluation step based on a Structural Operational Semantics and use these definitions as the basis for the specification of debuggers. Debugger correctness is then defined by an equivalence relation between a specification and an implementation of the debugger based on the bisimulation concept. The main results of this thesis are: a definition of a variant of Structural Operational Semantics, called Relational Semantics, which is the underlying formalism of this thesis; the definition of a notion of Observational Equivalence between Relational Semantics Specifications; a formulation of the problem of compiler correctness using Observational Equivalence; an evaluation model for programming languages and a definition of an evaluation step; an abstract definition of Interpreter-debuggers; a specification notation for the formal specification of debuggers, called DSL; a notion of equivalence between debuggers using bisimulation; a study on Compiler-debuggers and the problems involved in their definition. These results form a theory for the formal specification and proofs of correctness of compilers and debuggers. Our starting point is that the use of this theory helps in building better compilers and debuggers. It is our goal to provide theoretical foundations and tools to show that our methods are achievable.
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40

Křoustek, Jakub. "Rekonfigurovatelná analýza strojového kódu." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-261276.

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Analýza softwaru je metodologie, jejímž účelem je analyzovat chování daného programu. Jednotlivé metody této analýzy je možné využít i v dalších oborech, jako je zpětné inženýrství, migrace kódu apod. V této práci se zaměříme na analýzu strojového kódu, na zjištění nedostatků existujících metod a na návrh metod nových, které umožní rychlou a přesnou rekonfigurovatelnou analýzu kódu (tj. budou nezávislé na konkrétní cílové platformě). Zkoumány budou dva typy analýz - dynamická (tj. analýza za běhu aplikace) a statická (tj. analýza aplikace bez jejího spuštění). Přínos této práce v rámci dynamické analýzy je realizován jako rekonfigurovatelný ladicí nástroj a dále jako dva typy tzv. rekonfigurovatelného translátovaného simulátoru. Přínos v rámci statické analýzy spočívá v navržení a implementování rekonfigurovatelného zpětného překladače, který slouží pro transformaci strojového kódu zpět do vysokoúrovňové reprezentace. Všechny tyto nástroje jsou založeny na nových metodách navržených autorem této práce. Na základě experimentálních výsledků a ohlasů od uživatelů je možné usuzovat, že tyto nástroje jsou plně srovnatelné s existujícími (komerčními) nástroji a nezřídka dosahují i lepších výsledků.
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Weiss, Alexander. "Effiziente externe Beobachtung von CPU-Aktivitäten auf SoCs." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-184227.

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Die umfassende Beobachtbarkeit von System‐on‐Chips (SoCs) ist eine wichtige Voraussetzung für das effiziente Testen und Debuggen eingebetteter Systeme. Ausgehend von einer Analyse verschiedener Anwendungsfälle ergibt sich ein Katalog von Anforderungen an die Beobachtbarkeit von SoCs. Ein wichtiges Kriterium ist hier die Vollständigkeit der Beobachtung und umfasst die Aktivitäten der CPU (ausgeführte Instruktionen, gelesene und geschriebene Daten, Verhalten des Caches, Ausführungszeiten), des Bussystems und von Umgebungsbedingungen. Weitere Kriterien sind die Echtzeitfähigkeit und die Kontinuität der Beobachtung sowie die gleichzeitige Durchführung verschiedener Beobachtungsaufgaben. Dabei soll es zu einer möglichst geringen Beeinflussung des SoCs kommen. Weitere wichtige Aspekt sind die Kosten der Lösung, die Universalität, die Skalierbarkeit sowie die Latenz der Verfügbarkeit der Beobachtungsergebnisse. Für viele Anwendungen, besonders in sicherheitskritischen Bereichen, muss zudem nachgewiesen werden, dass das Beobachtungsverfahren kein Fehlverhalten des SoCs bewirkt bzw. ein solches maskiert. Eine besondere Herausforderung stellen Multiprozessor‐SoCs (MPSoCs) dar, da hier die Kommunikation zwischen den einzelnen CPUs im Inneren des SoC stattfindet und entsprechend schwierig für einen externen Bobachter sichtbar zu machen ist. Der Stand der Technik zur Beobachtung von SoCs wird im Wesentlichen durch zwei Verfahren dargestellt. Bei der Software‐Instrumentierung wird zum funktionalen Programmcode zusätzlicher Code hinzugefügt, welcher zur Beobachtung des Programms dient. Diese Methode ist einfach und universell anwendbar, erfüllt aber die genannten Kriterien nur sehr eingeschränkt. Nachteilig ist hier der Ressourcenverbrauch im Falle des Verbleibs der Instrumentierung im fertigen Produkt. Wird die Instrumentierung nur temporär dem Code hinzugefügt, muss sichergestellt werden, dass das Beobachtungsergebnis auch für den finalen Code anwendbar ist – was besonders bei ressourcen‐abhängigen Integrationstests nur schwierig erfüllbar ist. Eine alternative Lösung stellt eine spezielle Hardware‐Unterstützung in SoCs („embedded Trace“) dar. Hier werden im SoC Zustandsinformationen (z.B. Taskwechsel, ausgeführte Instruktionen, Datentransfers) gesammelt und mittels Trace‐Nachrichten an den Beobachter übermittelt. Dabei stellt die Bandbreite, die zur Ausgabe der Trace‐Nachrichten vom SoC verfügbar ist, ein entscheidendes Nadelöhr dar ‐ im SoC sind viel mehr den Beobachter interessierende Informationen verfügbar als nach außen transferiert werden können. Damit haben beide dem gegenwärtige Stand der Technik entsprechende Beobachtungsverfahren eine Reihe von Einschränkungen, die sich besonders bei der Vollständigkeit der Beobachtung, der Flexibilität, der Kontinuität und der Unterstützung von MPSoCs zeigen. In dieser Arbeit wird nun ein neuer Ansatz vorgestellt, welcher gegenüber dem Stand der Technik in einigen Bereichen deutliche Verbesserungen bietet. Dabei werden die Trace‐Daten nicht vom zu beobachtenden SoC direkt, sondern aus einer parallel mitlaufenden Emulation gewonnen. Die Bandbreite der für die Synchronisation der Emulation erforderlichen Daten ist in vielen Fällen deutlich geringer als bei der Ausgabe von umfassenden Trace‐Nachrichten mittels „embedded Trace“‐Lösungen. Gleichzeitig ist eine vollständige, äußerst detaillierte Beobachtung der Vorgänge innerhalb des SoC möglich. Das neue Beobachtungsverfahren wurde mittels verschiedener FPGA-basierter Implementierungen evaluiert, hier konnte auch die Anwendbarkeit für MPSoCs gezeigt werden.
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Krantz, Karl Johan. "Cross-Platform Post-Mortem Analysis in a Distributed Continuous Integration System." Thesis, Linköpings universitet, Medie- och Informationsteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-122912.

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This thesis aims to improve the cross-platform reliability of software components tested on distributed CI systems. More specifically, it is centered on extracting crash information from cross-platform crashes. Crash information was generated and parsed on Mac, Linux and Windows. The crash information proved to be valuable for developers in their day-to-day job, especially the raw crash information. However, the graph visualizations that were created out of this information proved to be less than satisfactory for developers.
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43

Chatelain, Yohan. "Outils de débogage et d'optimisation des calculs flottants dans le contexte HPC." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLV096.

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Le Calcul Haute Performance (HPC) est un écosystème dynamique où architectures et codes de calcul scientifiques sont en co-évolution permanente (parallélisme, accélérateurs spécialisés, nouvelles mémoires).Ce dynamisme impose aux développeurs d'adapter leur logiciel régulièrement pour exploiter au mieux tous les nouveaux ressorts technologiques.En cela, les approches de co-design consistant à développer simultanément le logiciel et le matériel sont une voie intéressante.Néanmoins, les efforts de co-design dans le HPC ont surtout été concentrés sur la performance des applications en laissant un peu de côté l'objectif de qualité numérique.Or celle ci est de plus en plus difficile à maintenir d'une génération de supercalculateur à l'autre en raison de la complexité croissante des architectures et des modèles de programmation parallèles. A cela s'ajoute de nouveaux formats de calcul flottants (bfloat16, binary16) qu'il faut réussir à exploiter lors du processus de modernisation.Ces constats posent deux problématiques :1) Comment vérifier la qualité numérique des codes lors du processus de modernisation ? Cela nécessite des outils qui permettent, à la fois d'identifier rapidement des sources d'erreurs numériques mais qui doivent également être simple d'utilisation pour des utilisateurs non-experts.2) Comment tirer parti des nouvelles possibilités qu'offre le matériel ?Les possibilités d'applications sont nombreuses et amènent donc à un espace considérable de solutions possibles. Les solutions trouvées sont le résultat d'un compromis entre performance de l'application et qualité numérique des calculs mais également reproductibilité des résultats.Dans cette thèse, nous avons contribué au logiciel Verificarlo qui aide à la détection d'erreurs numériques en injectant divers modèles de bruit dans les calculs flottants. Plus précisément, nous avons développé une approche permettant d'étudier l'évolution des erreurs numérique au cours du temps. Cet outil est basé sur la génération de traces numériques qui permettent de suivre la qualité numérique des variables au cours du temps. Ces traces sont enrichies par des informations de contexte récupérées lors de la compilation puis peuvent être ensuite visualisées de manière élégante.Nous avons également contribué à VPREC, un modèle de calcul simulant des formats de taille variable. Cet outil a été utilisé pour répondre au problème d'optimisation de formats dans les schémas itératifs. L'optimisation proposée est temporelle puisqu'elle optimise la précision de calcul pour chaque pas de temps.Enfin, une contrainte majeure dans l'élaboration d'outils pour le HPC est la mise à l'échelle. En effet, la taille des codes et la quantité de calcul mis en jeux accroissent drastiquement la complexité des analyses et limitent les approches conventionnelles. Nous avons démontré que les techniques développés dans cette thèse sont applicables sur des codes industriels puisqu'ils ont permis de, premièrement, détecter et corriger une erreur numérique dans le code ABINIT (code ab initio de chimie quantique développé par le CEA et al.). Secondement, ces outils ont permis de réduire la précision de calcul de YALES2 (code de mécanique des fluides développé par le CORIA) et améliorer les performance en réduisant le volumes des communications de 28% et accélérer jusqu'à 1,30 fois l’exécution
High Performance Computing (HPC) is a dynamic ecosystem where scientific computing architectures and codes are in permanent co-evolution (parallelism, specialized accelerators, new memories).This dynamism requires developers to adapt their software regularly to exploit all the new technological innovations.For this purpose, co-design approaches consisting of simultaneously developing software and hardware are an interesting approach.Nevertheless, co-design efforts have mainly focused on application performance without necessarily taking into account the numerical quality.However, this is becoming increasingly difficult to maintain from one generation of supercomputer to the next due to the increased complexity of the hardware and the parallel programming models. In addition, there are new floating point computation formats (bfloat16, binary16) that should be harnessed during the modernization process.These findings raise two issues:1) How to check the digital quality of codes during the modernization process? This requires tools that allow both to quickly identify sources of numerical errors and to be user-friendly for non-expert users.2) How can we take advantage of the new possibilities offered by the equipment?The applications possibilities are manifold and therefore lead to a considerable space of possible solutions. The solutions found are the result of a compromise between the performance of the application and the numerical quality of the computations, but also the reproducibility of the results.In this thesis, we contributed to the Verificarlo software that helps to detect numerical errors by injecting various noise models into floating computations. More precisely, we have developed an approach to study the evolution of numerical errors over time. This tool is based on the generation of numerical traces that allow the numerical quality of the variables to be tracked over time. These traces are enriched by context information retrieved during compilation and can then be viewed in an elegant way.We also contributed to VPREC, a computation model simulating formats of varying sizes. This tool has been used to address the problem of format optimization in iterative schemes. The proposed optimization is temporal since it optimizes the computation precision for each time step.Finally, a major constraint in the development of tools for HPC is the scaling up. Indeed, the size of the codes and the number of computations involved drastically increase the complexity of the analyses and limit conventional approaches. We have demonstrated that the techniques developed in this thesis are applicable to industrial codes since they have made it possible, first, to detect and correct a numerical error in the ABINIT code (ab initio code for quantum chemistry developed by the CEA et al.). Secondly, these tools have reduced the computation accuracy of YALES2 (fluid mechanics code developed by CORIA) and improved performance by reducing communication volumes by 28% and accelerating execution up to 1.30 times
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44

Demín, Michal. "Undetectable Debugger." Master's thesis, 2012. http://www.nusl.cz/ntk/nusl-305165.

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Using debuggers is a common mean for identifying and analyzing malware (such as viruses, worms, spyware, rootkits, etc.). However, debuggers can be detected by malware via observing of the behavior of operating system, changes in code (such as breakpoint instructions) and non-standard behavior of the CPU, making the analysis of the malware can be hard and tedious. In this thesis we are implementing a basic debugger based on the QEMU emulator that hides its presence from the debugged application. This is accomplished by using the QEMU as virtual machine and adding context awareness to the already existing primitive debugger. The context awareness is implemented using an embedded Python scripting engine. Such setup gives us a flexible way of implementing support for various operating systems. In this thesis, we have developed two examples. One example is for the RTEMS operating system, which serves as easy to understand reference implementation. Second example is for the Linux operating system, to show the abilities of the undetectable debugger in a more real scenario.
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45

Strite, David. "BACI debugger : a GUI debugger for the BACI system /." 2001. http://emp3.hbg.psu.edu/theses/available/etd-12202001-105107/.

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46

Li, Chang. "A MOON simulator and debugger." Thesis, 2002. http://spectrum.library.concordia.ca/1808/1/MQ72935.pdf.

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The goal of this project is to design a simulator and debugger which extends the capabilities of the current simulator called MOON simulator into a new modern debugger with a friendly and nice looking graphical user interface. MOON is a programming language for a simplified RISC processor. It was designed as a target language for compilers written in the Compiler Design courses (COMP442 and COMP 642 in Concordia University), moreover, it can be used as an aid to learning assembly language concepts. The MOON Debugger/Simulator can edit and assemble MOON programs into the "machine language" of the host processor, simulate the execution of programs on the processor, and provide some debugging facilities. The implementation is based on Java language with JDK1.3, and the system can run on any popular platforms. This report covers the system requirement, GUI design, object-oriented design and implementation in Java. The user's manual and some class source files are listed.
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Gou, Yi-Guan, and 郭逸冠. "An Interactive Parallel/Distributed Debugger." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/11107146657391748335.

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48

Riboira, André Daniel Moreira Pinto. "GZoltar: A graphical debugger interface." Dissertação, 2010. http://hdl.handle.net/10216/61658.

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Riboira, André Daniel Moreira Pinto. "GZoltar: A graphical debugger interface." Master's thesis, 2010. http://hdl.handle.net/10216/61658.

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Tsien, Christine L. "Maygen: A Symbolic Debugger Generation System." 1993. http://hdl.handle.net/1721.1/7054.

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With the development of high-level languages for new computer architectures comes the need for appropriate debugging tools as well. One method for meeting this need would be to develop, from scratch, a symbolic debugger with the introduction of each new language implementation for any given architecture. This, however, seems to require unnecessary duplication of effort among developers. This paper describes Maygen, a "debugger generation system," designed to efficiently provide the desired language-dependent and architecture-dependent debuggers. A prototype of the Maygen system has been implemented and is able to handle the semantically different languages of C and OPAL.
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