Dissertations / Theses: 'Decreasing length of channel'

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Torsello, Mauro. "Structural and dynamic modeling of molecular systems at different length scales." Doctoral thesis, Università degli studi di Padova, 2016. http://hdl.handle.net/11577/3424405.

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The continuous growth of computing power, both in terms of hardware and software resources, has made the computational (in-silico) approach to complex scientific problems a very profitable tool, which provides useful information to support, interpret or in some cases even reproduce the experimental datum from first principles. Methods have become cheaper and faster in the last two decades, thanks also to the development of more efficient algorithms, able to extract in full the computational power contained in novel hardware solutions (e.g. parallel computing and GPUs-based hardware), and to provide relatively easy-to-use software packages for diverse applications. Nowadays the computational approach is employed in several scientific areas, covering many different applied disciplines such as medicine, engineering, chemistry, physics, materials science and many others. In particular in this thesis work, some of the main approaches of computational chemistry, namely quantum mechanics, classical molecular dynamics and hybrid methods, are applied to the study of biomolecules and macromolecules, in order to investigate different aspects like structure, dynamics, energetics and in particular flexibility. In addition to the aforementioned methods we also explore a fluido-dynamic approach to describe and simulate microfluidic systems, focusing the attention on the reactivity of the systems studied. All these approaches are size-dependent and because they have different computational costs, their application should be limited to a reasonable size of the studied system. The profound difference in terms of cost/accuracy are discussed, providing a link between the different methodologies scales, in order to exemplify how information gathered at smaller length scale can be considered as an accurate starting point to perform simulations at larger spatial scales, in what is nowadays know popularly as multiscale modeling. The connection between the high accuracy/high cost and low accuracy/low cost methods is commented upon, to illustrate how a multiscale modeling approach can allow, in specific cases, to augment at the same time the accuracy of the data calculated and the size of the system simulated. La continua crescita della potenza di calcolo, in termini di risorse hardware e software, ha reso l'approccio computazionale (in-silico) ai complessi problemi scientifici, uno strumento molto conveniente che permette di ottenere informazioni utili al fine di affiancare, interpretare ed, in alcuni casi, addirittura riprodurre i dati sperimentali a partire da principi primi. I metodi sono stati resi più veloci ed efficienti negli ultimi vent'anni, grazie anche allo sviluppo di algoritmi sempre più efficienti, in grado di sfruttare al meglio la potenza computazionale racchiusa nelle nuove soluzioni hardware (ad esempio architetture parallele basate sulle GPU), e di fornire pacchetti software di semplice utilizzo per molteplici applicazioni. Al giorno d'oggi l'approccio computazionale è impiegato in numerose aree scientifiche, che spaziano tra le più disparate discipline applicate come medicina, ingegneria, chimica, fisica, scienze dei materiali e molte altre. In particolare in questo lavoro di tesi, alcuni degli approcci della chimica computazionale quali meccanica quantistica, dinamica molecolare classica e metodi ibridi, sono applicati allo studio di biomolecole e macromolecole, al fine di investigare differenti aspetti come struttura, dinamica, energetica e in particolare la flessibilità. In aggiunta ai metodi su menzionati è stato anche esplorato un approccio fluido-dinamico al fine di descrivere e simulare sistemi microfluidici, focalizzando l'attenzione sulla reattività dei sistemi presi in esame. Tutti questi approcci sono dipendenti dall'estensione del sistema e, poiché hanno un differente costo computazionale, la loro applicazione dovrebbe essere limitata ad una ragionevole dimensione dei sistemi studiati. Le profonde differenze in termini di costo/accuratezza sono discusse, fornendo un collegamento tra le scale spaziali delle diverse metodologie, al fine di esplicare come le informazioni ottenute a scale spaziali inferiori possano essere considerate come punto di partenza accurato per effettuare simulazioni a scale spaziali maggiori, in un approccio che è oggi comunemente noto come modellazione multiscala. La connessione tra i metodi ad alta accuratezza/alto costo e quelli a bassa accuratezza/basso costo è commentata, illustrando così come un approccio multiscala possa permettere, in casi specifici, di incrementare al contempo l'accuratezza del dato calcolato e la dimensione del sistema simulato.

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Senior, A. K. "A Numerical study of resistance in a rough walled channel flow where the ratio of roughness length scale to the depth of flow varies over a wide range." Thesis, School of Engineering and Applied Science, 2009. http://hdl.handle.net/1826/3892.

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Numerical calculations were performed over a variety of two-dimensional rib roughness configurations in which the ratio of flow depth to roughness height was varied from 1.1 to 40. Periodically fully developed flow was achieved by employing periodic boundary conditions and the effect of turbulence was accounted for by a two-layer model. These calculations were used to test the hypothesis that any rough wall resistance may be reduced to an equivalent wall shear stress located on a plane wall. The position of the plane wall is determined by a novel method of prediction obtained by consideration of strearnwise force moments. The resistance is then determined by three dynamically significant length scales: the first (yo) specifies the position of the equivalent plane wall, the second is the depth of flow h and the third is similar to Nikuradse's sand grain roughness k,,. The latter length scale is however depth dependent and a universal relationship is postulated: ks y,, -,= F(Tkwhere ksw is the asymptotic value of ks at very large flow depths. For the calculation of friction factor, a resistance equation is proposed of the form typical of fully rough flows. These postulates are supported by the numerical model results though further work including physical experiments is required to confirm them. Before applying the two-layer model to this problem it was tested on smooth rectangular duct flows and Schlichting's (1936) long angle roughness experiments. The opportunity was taken to further explore these flows, and in addition calculations were carried out for Grass et al's ( 199 1) open channel rib roughness experiments. The periodic boundary conditions were also applied to a larninar counter-flow plate-fin heat exchanger.A novel source-sinka rrangemenfto r heat flux was developedi n order to implement these boundary conditions.

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Van, der Tak Laurens Daniel. "Part I--Stream length distributions, hillslope effects and other refinements of the geomorphologic IUH ; part II--Topologically random channel networks and Horton's laws : the Howard network simulation model revisited." Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/14581.

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Thesis (Civ. E.)--Massachusetts Institute of Technology, Dept. of Civil Engineering, 1988. Title page reads: Part I: Stream length ... IUH. -- Part II: Topologically random ... revisited. Title as it appeared in MIT Graduate list, June, 1988: Part I: Refinements of the geomorphologic IUH. -- Part II: The Howard topological channel network simulation model revisited. Includes bibliographical references. by Laurens Daniel Van der Tak. Civ.E.

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Cross, Jaimie. "The dynamics of suspended particles in a seasonally stratified coastal sea." Thesis, University of Plymouth, 2013. http://hdl.handle.net/10026.1/1461.

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A comprehensive investigation into the relationship between physical forcing and sus- pended particles in the shallow shelf region of the Western English Channel has been conducted, in order to evaluate the temporal dynamics of suspended particle populations. Measurements were taken across tidal cycles and seasons at station L4, part of the Western Channel Observatory (WCO), using the combination of a free-fall microstructure profiler and holographic imaging. Confirmation that L4 is weakly stratified is given, and that the formation of the seasonal thermocline is substantially altered by the spring-neap cy- cle. Stratification is variable and prone to periodic and partial erosion from atmospheric forcing during any point in any season. L4 undergoes moderate turbulent dissipation, principally as a result of tidal forcing. Typically, values of ε do not exceed 10−4 W kg−1 . L4 also exhibits tidal asymmetry, chiefly in response to stratification which, albeit weak, is frequently able to suppress turbulence when generated from the sea bed. The potential energy anomaly is small at L4, as expected for a weakly-stratified environment. Maxi- mum values in summer were shown to not exceed 50 J m−3 . Values of bed stress, τ0 , are rarely greater than around 0.18 N m−2 . Nonetheless, the critical erosion threshold falls below this, and is therefore smaller than that observed in similar locations around the UK. Seasonality in the amount of material resuspended from the seabed is important at L4. The presence of certain biological particles strongly influence particle size and may also determine if a given particle is lifted from the bed. Particles ≥ 200 μm are relatively rare, the site is dominated by particles smaller than this value in line with many other UK sites. Under certain conditions the theoretical maximum limit of particle size, the Kolmogorov length scale, does not hold and many examples of occasions when this threshold is exceeded are shown. This may generate important consequences in subsequent work undertaken at this site and other temperate shelf locations globally, particularly as these results indicate that maximum particle size appears to be governed less by the size of the local turbulent eddies and more by the presence of biological particles. This is another key seasonal component to particle dynamics in the Western English Channel. Phytoplankton populations are readily advected into and out of the L4 site, calling into question the current sampling strategy of the WCO to rely exclusively upon point measurements. Small increases in atmospheric forcing have the ability to rapidly disperse patches of phytoplankton, possibly to the point of cell mortality. Traditional sampling techniques for assessing zooplankton density have been shown to radically underestimate the number of animals present at L4, which will increase error estimates on current ecosystem models.

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YAMAMOTO, Kazuhiro, Hiroshi YAMASHITA, and Jilin HAN. "Numerical Study on Spark Ignition Characteristics of Methane-air Mixture Using Detailed Chemical Kinetics : Effect of Electrode Temperature and Energy Channel Length on Flame Propagation and Relationship between Minimum Ignition Energy and Equivalence Ratio." The Japan Society of Mechanical Engineers and The Heat Transfer Society of Japan, 2009. http://hdl.handle.net/2237/19812.

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Bali, Chadha [Verfasser], Arved Carl [Gutachter] Hübler, Arved Carl [Akademischer Betreuer] Hübler, Ulrich Sigmar [Gutachter] Schubert, and Axel [Akademischer Betreuer] Ganster. "Coffee-ring-effect based self-assembly mechanism for all-inkjet printed organic field effect transistors with micron-sized channel length / Chadha Bali ; Gutachter: Arved Carl Hübler, Ulrich Sigmar Schubert ; Arved Carl Hübler, Axel Ganster." Chemnitz : Technische Universität Chemnitz, 2020. http://d-nb.info/1219664316/34.

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Dubinskaitė, Jurgita. "Kooperatinės bendrovės "Daržovių centras" produktų paskirstymo valdymas." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050530_113650-29481.

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Object of the work: cooperative "Daržovių centras". Subject of the work: distribution of goods. Work purpose: to prepare distribution strategy for organization and to provide for perfection of channel management. Tasks of the work: 1. To analyse goods distribution system; 2. To establish basic variants of formation for distribution channels; 3. To analyse elements of channel management; 4. To analyse channels of distribution for organization and formulate methodical substantiation; 5. To prepare distribution strategy; 6. To provide for perfection of channel management. Methods of the research - questionnaire poll, half-structural interview, analyses and synthesis of literature, SWOT analyse and graphic method.

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Mello, Micael Oliveira Massula Carvalho de. "Roteamento em redes em malha sem fio com balanceamento de carga e caminhos mais curtos." Universidade Federal de Goiás, 2014. http://repositorio.bc.ufg.br/tede/handle/tede/4250.

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Submitted by Luciana Ferreira (lucgeral@gmail.com) on 2015-03-05T15:35:28Z No. of bitstreams: 2 Dissertação - Micael Oliveira Massula Carvalho de Mello - 2014.pdf: 489311 bytes, checksum: 15900b2c2d82201091cb1f73eeb459f4 (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) Approved for entry into archive by Luciana Ferreira (lucgeral@gmail.com) on 2015-03-06T10:37:11Z (GMT) No. of bitstreams: 2 Dissertação - Micael Oliveira Massula Carvalho de Mello - 2014.pdf: 489311 bytes, checksum: 15900b2c2d82201091cb1f73eeb459f4 (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) Made available in DSpace on 2015-03-06T10:37:11Z (GMT). No. of bitstreams: 2 Dissertação - Micael Oliveira Massula Carvalho de Mello - 2014.pdf: 489311 bytes, checksum: 15900b2c2d82201091cb1f73eeb459f4 (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) Previous issue date: 2014-12-19 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES Wireless Mesh Networks (WMNs) are infrastructures with autonomic properties, such as self-organization and self-recovery, which can be developed with widely available technologies and low cost solutions. Besides their current applications, such as community networks and broad-band Internet access, WMNs can offer contributions in the context of the Internet of Things and help to build robust infrastructures to smart energy networks, among other uses. However, WMNs usually have performance issues due to overload in certain parts of the network and interference in wireless links. In this context, it is important that solutions are used to promote load-balancing and to mitigate interference between wireless links. Research in this area shows that one of the most promising approaches are in the subject of the joint routing and channel assignment. However, most of the previous works depends on the knowledge of the network traffic and handle flows with low granularity. In this thesis, we handle the performance problem in WMNs, in particular those having multiple radios and multiple available channels, using a joint approach, but without the mentioned restrictions. Our proposal is a joint heuristic, whose main contribution is the routing, which pursues the compromise between load-balancing and the path length of the network flows. We have developed our proposal in the Network Simulator 3 (ns-3) and have compared it with other works in literature. We found that our heuristic provides throughput improvements in most of the analyzed scenarios, besides promote greater justice between the flows that compete for resources. Redes em Malha Sem Fio - Wireless Mesh Networks (WMNs) são infraestruturas com propriedades autonômicas, como auto-organização e autorrecuperação, que podem ser implementadas com tecnologias amplamente disponíveis e de custo acessível. Além de suas aplicações atuais, como redes comunitárias e redes de acesso à Internet, as WMNs podem auxiliar na comunicação de Internet das Coisas e constituir infraestruturas robustas para redes inteligentes de energia, dentre outros usos. No entanto, WMNs geralmente apresentam questões relativas a desempenho devido a fatores como sobrecarga em determinadas partes da rede e interferências nos enlaces sem fio. Nesse contexto, é importante que sejam utilizadas soluções que promovam balanceamento de carga na rede e que minimizem as interferências entre os enlaces sem fio. A pesquisa nessa área tem mostrado que uma das abordagens mais promissoras consiste em tratar de maneira conjunta o roteamento e a atribuição de canais. Porém, a maior parte dos trabalhos dependem de conhecimento prévio do tráfego da rede e tratam fluxos com baixa granularidade. Nesta dissertação, tratamos o problema de desempenho em WMNs, em especial as que possuem múltiplos rádios e múltiplos canais disponíveis, utilizando uma abordagem conjunta, mas sem as restrições anteriores. Nossa proposta é uma heurística conjunta, cuja principal contribuição está no roteamento, o qual persegue um compromisso entre o balanceamento de carga e o comprimento dos caminhos seguidos pelos fluxos. Implementamos nossa proposta no Network Simulator 3 (ns-3) e a comparamos com outros trabalhos da literatura. Verificamos que nossa heurística apresenta ganhos de vazão na maior parte dos cenários avaliados, além de promover maior justiça entre os fluxos que concorrem pelos recursos.

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Tran, Anh-Tuan. "Modélisation et simulation des interfaces non classiques dans l’écoulement de Stokes et dans les composites élastiques fibreux." Thesis, Paris Est, 2014. http://www.theses.fr/2014PEST1071/document.

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Ce travail de thèse, constitué de deux parties apparemment très différentes, a pour objectif commun de modéliser et simuler certaines interfaces non classiques en mécanique des fluides et en mécanique des solides. Dans la première partie qu'est la partie principale du travail, l'écoulement de Stokes d'un fluide dans un canal encadré par deux parois solides parallèles est étudié. La surface d'une paroi étant supposée lisse, la condition d'adhérence parfaite classique est adoptée pour l'interface fluide-solide homogène correspondante. La surface de l'autre paroi étant supposée rugueuse et capable de piéger de petites poches d'air, l'interface liquide-solide correspondante est donc hétérogène. La première partie de ce travail consiste à homogénéiser l'interface liquide-solide hétérogène de façon à remplacer cette dernière par une interface fluide-solide homogène imparfaite caractérisée par une longueur de glissement effective. Le problème essentiel de déterminer la longueur de glissement effective est résolu par le développement : (i) d'une approche semi-analytique dans le cas où la surface rugueuse est périodique; (ii) d'une approche basée sur la méthode de solution fondamentale dans le cas où la surface rugueuse est aléatoire. Les résultats obtenus par les approches développées sont systématiquement comparés avec ceux délivrés par la méthode des éléments finis. La deuxième partie du travail est de déterminer les modules élastiques effectifs d'un composite fibreux dans lequel les interfaces entre la matrice et les fibres sont imparfaites et décrites par le modèle membranaire. Une méthode numérique efficace basée sur la transformée de Fourier est ainsi développée et implantée pour traiter le cas général où la section d'une fibre peut avoir une forme quelconque The present work, consisting of two seemingly very different parties, aims at modeling and simulating some non-classical interfaces in fluid mechanics and solid mechanics. In the first part which is the main part of the work, the Stokes flow of a fluid in a channel bounded by two parallel solid walls is studied. The surface of a solid wall being assumed to be smooth, the classic perfect adherence condition is adopted for the corresponding homogeneous fluid-solid interface. The surface of the other wall being taken to be rough and capable of trapping small pockets of air, the corresponding liquid-solid interface is heterogeneous. The first part of this work is to homogenize the heterogeneous liquid-solid interface so as to replace it by an imperfect homogeneous fluid-solid interface characterized by an effective slip length. The essential underlying problem of determining the effective slip length is achieved by developing: (i) a semi-analytical approach when the rough surface is periodic; (ii) an approach based on the fundamental solution method when the surface is randomly rough. The results obtained by the developed approaches are systematically compared with those issued from the finite element method. The second part of the work is to determine the effective elastic moduli of a fiber composite in which the interfaces between the matrix and fibers are imperfect and described by the membrane model. An efficient numerical method based on the fast Fourier transform is developed and implemented to treat the general case where the section of a fiber can be of any shape

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Diallo, Amadou Tidiane. "Caractérisation analytique et optimisation de codes source-canal conjoints." Phd thesis, Université Paris Sud - Paris XI, 2012. http://tel.archives-ouvertes.fr/tel-00748545.

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Les codes source-canal conjoints sont des codes réalisant simultanément une compression de données et une protection du train binaire généré par rapport à d'éventuelles erreurs de transmission. Ces codes sont non-linéaires, comme la plupart des codes de source. Leur intérêt potentiel est d'offrir de bonnes performances en termes de compression et de correction d'erreur pour des longueurs de codes réduites.La performance d'un code de source se mesure par la différence entre l'entropie de la source à compresser et le nombre moyen de bits nécessaire pour coder un symbole de cette source. La performance d'un code de canal se mesure par la distance minimale entre mots de codes ou entre suite de mots de codes, et plus généralement à l'aide du spectre des distances. Les codes classiques disposent d'outils pour évaluer efficacement ces critères de performance. Par ailleurs, la synthèse de bons codes de source ou de bons codes de canal est un domaine largement exploré depuis les travaux de Shannon. Par contre des outils analogues pour des codes source-canal conjoints, tant pour l'évaluation de performance que pour la synthèse de bons codes restaient à développer, même si certaines propositions ont déjà été faites dans le passé.Cette thèse s'intéresse à la famille des codes source-canal conjoints pouvant être décrits par des automates possédant un nombre fini d'états. Les codes quasi-arithmétiques correcteurs d'erreurs et les codes à longueurs variables correcteurs d'erreurs font partie de cette famille. La manière dont un automate peut être obtenu pour un code donné est rappelée.A partir d'un automate, il est possible de construire un graphe produit permettant de décrire toutes les paires de chemins divergeant d'un même état et convergeant vers un autre état. Nous avons montré que grâce à l'algorithme de Dijkstra, il est alors possible d'évaluer la distance libre d'un code conjoint avec une complexité polynomiale.Pour les codes à longueurs variables correcteurs d'erreurs, nous avons proposé des bornes supplémentaires, faciles à évaluer. Ces bornes constituent des extensions des bornes de Plotkin et de Heller aux codes à longueurs variables. Des bornes peuvent également être déduites du graphe produit associé à un code dont seule une partie des mots de codes a été spécifiée.Ces outils pour borner ou évaluer exactement la distance libre d'un code conjoint permettent de réaliser la synthèse de codes ayant des bonnes propriétés de distance pour une redondance donnée ou minimisant la redondance pour une distance libre donnée.Notre approche consiste à organiser la recherche de bons codes source-canal conjoints à l'aide d'arbres. La racine de l'arbre correspond à un code dont aucun bit n'est spécifié, les feuilles à des codes dont tous les bits sont spécifiés, et les nœuds intermédiaires à des codes partiellement spécifiés. Lors d'un déplacement de la racine vers les feuilles de l'arbre, les bornes supérieures sur la distance libre décroissent, tandis que les bornes inférieures croissent. Ceci permet d'appliquer un algorithme de type branch-and-prune pour trouver le code avec la plus grande distance libre, sans avoir à explorer tout l'arbre contenant les codes. L'approche proposée a permis la construction de codes conjoints pour les lettres de l'alphabet. Comparé à un schéma tandem équivalent (code de source suivi d'un code convolutif), les codes obtenus ont des performances comparables (taux de codage, distance libre) tout en étant moins complexes en termes de nombre d'état du décodeur.Plusieurs extensions de ces travaux sont en cours : 1) synthèse de codes à longueurs variables correcteurs d'erreurs formalisé comme un problème de programmation linéaire mixte sur les entiers ; 2) exploration à l'aide d'un algorithme de type A* de l'espace des codes de à longueurs variables correcteur d'erreurs.

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Nicoletti, Talitha. "Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.

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O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL. The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.

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Brut, Hugues. "Contribution à la modélisation et à l'extraction des paramètres de tension de seuil, de résistance série et de réduction de longueur dans les transistors MOS submicroniques." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0192.

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La conception des circuits integres a l'aide de simulateurs de type spice, necessite l'elaboration de modeles physiques, precis et simples. Pour cela, une bonne comprehension du comportement des dispositifs est indispensable. Par ailleurs la reduction constante des dimensions de ces dispositifs entraine l'apparition de nouveaux phenomenes physiques qu'il est primordial d'isoler et de caracteriser d'un point de vue experimental, afin d'en faire une modelisation aussi proche que possible de la realite. C'est dans ce cadre de recherche que s'inscrit ce memoire. Les dispositifs etudies ici sont les transistors metal oxyde semiconducteur, largement utilises dans les circuits integres de type numerique. Les modeles et les procedures d'extraction directes developpes sont appliques sur un large panel de technologies allant de 1. 2 m a 0. 1 m. Apres un bref rappel du fonctionnement des transistors mos et des problemes technologiques et de modelisation lies aux dimensions reduites des dispositifs (chapitre 1), trois parametres fondamentaux sont traites: la tension de seuil, la resistance serie et la longueur de canal effective. Dans le chapitre 2, la modelisation de la tension de seuil et l'extraction des profils de dopage transverses sur les transistors a canaux longs sont abordes. Le chapitre 3 est ensuite consacre a la modelisation de la tension de seuil et a l'extraction des profils de dopage lateraux dans les transistors a canaux courts. Dans cette partie, sont notamment decorreles l'effet canal court classique associe au partage de charge et l'effet canal court inverse relatif a une non homogeneite des profils de dopage lateraux. Enfin, le chapitre 4 est dedie a l'etude de la resistance serie et de la longueur de canal effective. En particulier, l'evolution de ces deux parametres avec la polarisation de grille, ainsi que sa modelisation, sont traites dans le cas de transistors ayant des regions source et drain a zone faiblement dopees (ldd)

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Hsieh, Chung-Han, and 謝宗翰. "Multi-Channel-Length Sub-Threshold CMOS Circuits." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/51703095557966187636.

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碩士 國立中正大學 電機工程研究所 99 There are more special process procedure in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct called reverse short-channel-effect (RSCE) which can improve the circuit performance is involved. This paper will explore the circuit performance by utilizing TSMC 65 nm process. At present, foundry didn’t provide the special model for sub-threshold circuit design application. It is difficult to design a sub-threshold circuit due to the leakage at the sub-threshold operation. This paper will focus on the nanometer technology circuit design at sub-threshold operation. And design the standard cell library and flip-flops with reverse short-channel-effect (RSCE). This paper is also describe a device size optimization which be considered for sub-threshold operation. Experiment results using ISCAS’2003 benchmarks and fabricated in TSMC 65nm CMOS technology show that the critical path delay, power consumption.

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Huang, Chi-Tsung, and 黃啟聰. "Channel Length Extraction Methods of Advanced CMOS Devices." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/08698864743452156423.

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碩士 國立臺北科技大學 機電整合研究所 90 MOSFET have become the dominant technology for integrated circuits in the semiconductor industry. Over the last few years, there are many people devoted to the study in scaling down the CMOS device size for the sake of increasing the packing density and improving the circuit performance. With the increased scaling down of MOSFET dimensions, it is important to take process device parameters into account. Especially, channel length plays an important role in CMOS technology used for device design and process monitoring. Although have many methods have been proposed for the extraction of effective channel length (Leff), include traditional I-V method and C-V method, they will degrade the extraction accuracy of the value of Leff for obtaining better short channel performance in advanced CMOS devices. In this thesis, we proposed a new method for extracting advanced CMOS device parameters by a modified Capacitance-Voltage method, called Capacitance-Ratio method (C-R method). Using the C-R method, we can electrically measure the exact Lpb and Lovlap numbers that can both be used as process monitor parameters. At the same, more consistent and reasonable Leff data can be extracted. On the other hand, we also used an alternative newly developed technique, Scanning Capacitance Microscopy (SCM), actually obtaining two-dimensional dopant profiles for cross section devices in semiconductor materials. Using the SCM, which different in other measurements, we can directly measure the image of channel length in advanced CMOS devices. Finally, according to the SCM measured results, we will know that the C-R method be more consistent and suitable in the future.

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Hsu, Tzu Fan, and 徐子凡. "Iterative Source-Channel Decoding for Variable-Length Codes." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/91454503820931444386.

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碩士 國立交通大學 電信工程研究所 99 Transmission of convolutionally encoded source codec parameters over noisy channels can benefit from the use of iterative source‐channel decoding (ISCD). This thesis focuses on the design of a symbol-based ISCD for variable‐length code (VLC). Our work starts with a sectionalized code trellis whose two-dimensional states are created by combing the symbol-based VLC trellis and the state transition of a channel encoder. We first derive a soft-output channel decoding algorithm that integrates the residual source into the ISCD algorithm. Based the turbo principle, ISCD exchanges the extrinsic information resulting from the source decoder and the channel decoder to improve the decoding performance. Simulation results are presented for Gauss-Markov sources and ECG signals which demonstrate the error-resilience capabilities of symbol-based iterative decoding.

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Lin, Yang-Jye, and 林揚傑. "A New Method to Determine Effective Channel Length, Source-and-Drain Series Resistance of MOSFET's and Temperature Effect on Effective Channel Length." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/92908825740732966641.

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碩士 國立清華大學 電子工程研究所 87 A new method of extracting effective channel length (Leff) and source-and-drain series resistance (RSD) is proposed. The method bases on I-V measurement and drain current equation. Since Leff and RSD were considered to be gate-voltage-dependent, this new method bases on this assumption and can be used to extract Leff and RSD at different gate-overdrive-voltages (Vgs - Vt). Extracting through our method, we find that Leff increases with the increase of gate-overdrive-voltage and RSD decreases with the increase of gate-overdrive-voltage. When comparing with "paired-Vg-method", our extracting results almost agree with that of paired-Vg-method, and we prove that it is always true. Furthermore, we get an error term through our method. The error term is included in our method and "paired-Vg-method", but only can be seen through our method. Finally, we use the error term to explain how the temperature affect the experiment result and show that the "real" Leff is almost independent of temperature, at least, from T=25℃ to 150℃.

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"Joint source-channel turbo techniques and variable length codes." Université catholique de Louvain, 2008. http://edoc.bib.ucl.ac.be:81/ETD-db/collection/available/BelnUcetd-04062008-165446/.

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Yeh, Ying-mao, and 葉英茂. "Blind SNR and Channel Length Estimation in OFDM Systems." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/50021075820721348209.

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碩士 國立中山大學 通訊工程研究所 97 In many algorithms for Orthogonal Frequency Division Multiplexing (OFDM) systems, the channel estimation is one of the most essential factors. In wireless environment, channel is change very fast, and the channel has multipath effect, the channel length is obtained by channel estimation. In this paper, we estimation the channel length and the SNR by virtual carriers (VC) and Singular value decomposition, when channel estimator known the information for channel length, then calculate complicated can be reduced. Besides, we proposed the estimated method at carriers frequency offset effect. Noise variance (or noise power) can improve performance of channel estimator, e.g. MMSE channel estimator, turbo code or power allocation. In this paper, we were estimate noise variance by using the blind method of property of orthogonality of matrix, which is differed from the traditional method of Pilots.

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Cheng, Wei-Chung, and 鄭惟中. "Effects of Path Delay Values and Channel Dispersion Length on LS Channel Estimate Performance." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/57008739987827608934.

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碩士 淡江大學 電機工程學系 92 We investigate effects of the multipath delay value (in units of integral and non-integral multiples of data symbol period) and channel dispersion length on the performance of least-square (LS) channel estimation for wireless OFDM systems. Square QAM transmission over frequency-selective slowly fading channels are considered. Several channel fading types, some purely theoretical, are modeled for analysis and simulation studies. They are channels with real Gaussian fading amplitudes, real Rayleigh fading amplitudes, and complex Gaussian amplitudes. Performance measures used are least-square errors of the channel estimate and symbol error rates. Block-type pilot arrangements are used for the LS channel estimation.

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Chang, Ting-Huan, and 張廷桓. "The Effective Channel Length and Source-Drain Series Resistance Extraction of Short Channel MOSFET." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/79240897943427255183.

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博士 中正理工學院 國防科學研究所 86 Abstract A new technique of determining the effective channel length by directly measuring source-drain series resistance of metal-oxide-semiconductor field-effect transistors (MOSFETs) was proposed. By using MOSFETs with scaled gate lengths, the source- drain series resistance can be obtained from a egenerate?device whose source and drain regions are connected. The gate length and the total resistance of the degenerate MOSFET are the lower limits of channel length reduction and source-drain series- resistance, respectively. In order to determine whether a MOSFET source and drain are connected, a quantitative ifference of total resistance?(DTR) method, which can also be used to electrically determine the gate length of a normal MOSFET after the fabrication process, was developed in this study. Also, we proposed qualitative methods to judge whether a MOSFET is degenerate. The effective channel length can then be extracted from the obtained series resistance and I-V of MOSFETs. In this study, the final result of the determined channel length reduction DL is the metallurgical DLmet and the source-drain series resistance is not a constant but clearly showed gate bias dependency. This technique, although requires very short-gate-length devices, is not affected by source-drain series-resistance gate bias dependence issue encountered in conventional I-V methods. Moreover, because of the simplicity of this technique, it can be used in process monitoring, device design and SPICE modeling.

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Lin, Zhi-Xian, and 林志賢. "Joint source-channel decoding for convolutionally encoded variable length codes." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/52681082637156508108.

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碩士 國立交通大學 電信工程研究所 100 Reliable transmission of convolutionally encoded source codec parameters over noisy channels can benefit from the use of joint source‐channel decoding (JSCD). This thesis focuses on the design of a symbol-based JSCD for convolutionally encoded variable‐length codes (VLC). We also investigate bidirectional decoding schemes by using reversible variable length code (RVLC). Our work starts with a sectionalized code trellis whose two-dimensional states are created by combing the symbol-based VLC trellis and the state transition of a channel encoder. Then, we derive the recursive implementation of JSCD algorithm according to the three-dimensional sectionalized code trellis. Simulation results on both Gauss-Markov sources and ECG signals demonstrate the error-resilience capabilities of symbol-based joint decoding by using the first-order source correlation.

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Wen, Ying-Zhi, and 溫英志. "Effective Channel Length Analysis of Proton-Exchange-Membrane Fuel Cell." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/92434313433742633244.

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碩士 國立臺灣大學 應用力學研究所 91 An effective channel length of proton-exchange-membrane fuel cell interests engineers and scientists. There are many studies on the domain of along-the-channel model considering every kind of theories inclusive of electrochemistry, mass transportation, thermodynamics, and fluid mechanics. Lots of papers discussing this issue hypothesize a constant velocity of gas flow in the whole channel. However, the variation of gas velocity is dramatic in the real situation. Its speeding up from inlet to outlet is huge and ought to be considered in a complete model. By the fundamental of fluid dynamics and electrochemistry, we provide a completely new along-the-channel model to successfully predict this dynamics and effects of different operating parameters such as inlet conditions, catalyst property, permeability of porous media, and channel height. Therefore, this model is able to be used for the optimization of proton-exchange-membrane fuel cell design and operation, and can serve as a building block for the modeling and understanding of proton-exchange-membrane fuel cell stacks and systems.

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Liu, Yao-Jen, and 劉耀仁. "Extraction of gate-bias-dependent effective channel length in MOSFETs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/37976529361895120853.

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碩士 雲林科技大學 光學電子工程研究所 98 The effective channel length and parasitic source/drain resistance of MOSFET’s are of utmost importance for circuit modeling, process monitoring and device design, and effective channel length and parasitic source/drain resistance are depended on gate-bias. Conventionally, the effective channel length is defined as the value of Lmask－ΔL (Lmask is the mask channel length and ΔL is the value of channel length modulation). In this thesis, the new extraction algorithms are presented to extract the effective channel length and parasitic source/drain resistance. It had been shown that effective channel length decreased and parasitic source/drain resistance increased with raising gate-bias.

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Lin, Chih-Hung, and 林志鴻. "Variable Length Encoding for Backward Channel Protection in RFID Systems." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/96214082991567831031.

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碩士 中華大學 資訊工程學系(所) 98 RFID (Radio Frequency Identification) is a kind of communication technology that reader utilizes the wireless technology to identify the Tag data. In the recent years, RFID technology has been adopted in many application systems, such as supply chain management system, healthcare system, entrance control system, etc. Nowadays, there are many resources have been invested in the RFID research, which makes the RFID technology becomes more mature. As the wireless technology is adopted in RFID system to transfer the data between tag and reader, hence, the tag data will be eavesdropped easily should there be no encoding mechanism used in the data transmission between tag and reader. Therefore, the security issue is an extremely important objective and worth for discussion in RFID research. Consequently, a variable length encoding method (VLE) is proposed in this paper to improve the RFID security control. The VLE method adopts a simple encoding rule to improve the RFID security and protect data from being eavesdropped without adding loading in data transfer. In the VLE method, a new bit expression rule is adopted to identify data. In the new expression rule, each bit can express three data statuses; hence, data can be expressed with a shorter data length. The data expressed using the new data expression rule is called VLE Code. The VLE Code is passed from the tag to the reader and the reader will use a memory address and memory offset concepts to decode the tag data. This encoding and decoding method can achieve the objective of data protection with an easy and achievable way.

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CHEN, FU, and 陳馥. "Electrokinetic Energy Conversion with Alumina Nanochannels: Influence of Channel Length." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/82qgq8.

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碩士 國立雲林科技大學 化學工程與材料工程系 106 Due to the impact of the energy crisis, research on renewable energy has been flourishing. In recent years, many study have used different nanofilm materials for electrokinetic energy conversion. However, in addition to the choice of film materials, the film thickness is also at issue. Most of the earliest related research uses semiconductor process to make a single nanochannel. Although this method can adjust the length of the nanochannel, the ion flux and the low power output are low. In laboratory scale, it is difficult to investigate the effect of the channel length; in recent studies, most of the polymer porous nanofilms are used, and it is difficult to regulate the channel length. In this study, we investigate both theoretically and experimentally the influence of channel length on electrokinetic energy conversion with alumina nanochannels. The alumina nanochannels with various channel lengths were fabricated by a standard anodization process with controlling the oxidation time in the standard process of anodized aluminum nanochannel, and to discuss the electrokinetic energy conversion by aluminum nanochannels under different salt concentration conditions. The results show that in the higher concentration condition, the shorter the channel length, the higher the power density of the electrokinetic energy conversion. In the case of the lower concentration, the shorter the length, the higher the power density will first rise, then reach the saturation region; and experimental data can be described well by our modeling results. This means that at low concentrations, it is not necessary to make the thin film, and it can have almost the same power output.

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Chen, Yenyu. "Extracting the Effective Channel Length and Series Resistance of 65nm pMOSFET." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709254404.

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Oh, Yuns. "Optimal decoding of run-length limited codes in a magnetic channel." 1988. http://hdl.handle.net/1993/16758.

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Su, Jiong-Guang, and 蘇炯光. "Optimizing Design and Analysis of Channel Length 0.18 um MOS Device." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/81384044315761332593.

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邱敬文. "An improved Shift-and-Ratio method for Effective-Channel-Length extraction." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/24896547755449014309.

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Chen, Yenyu, and 陳彥妤. "Extracting the Effective Channel Length and Series Resistance of 65nm pMOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/90127905584725285521.

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碩士 國立清華大學 電子工程研究所 94 A new, more accurate and more reasonable method of　determining the MOSFETs effective channel length and source-drain　series resistance is presented in this thesis. This method improves　shit-and-ratio method and develops a more accurate calculation　system. Comparing the extracted values from the Suciu-Johnston　method, De La Moneda method, shift-and-ratio method, gate leakage method, and our new method, we prove that our method is the most accurate and reasonable one. Besides, we use this newly developed method to observe the co-implant source/drain effect in a 65nm pMOSFET.

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Yiu, Yen-Chen, and 劉彥辰. "Short Length Code Design for Simultaneously Good for Source and Channel Code." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/8c7snn.

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碩士 國立臺灣科技大學 電子工程系 102 In this thesis, we focus on designing a simultaneously good for source and channel coding (SSC) with short codeword length. The main application of SSC is the Wyner-Ziv coding, which is the key technique for cloud network and distributed source coding. In Wei e.t. a.l., a long length SSC code was proposed based on low-density parity-check code (LDPC) as the source and channel code. However, a long codeword length code design prohibits real-time applications due to the intolerable latency. Aim for the short codeword length regime, a new parity check matrix, which reduces the short circles of the Tanner graph of LDPC code, is adopted. For the corresponding channel decoding algorithm, a new algorithm called as reinforced belief propagation (RBP) is proposed. By adding a reinforced term in the celebrated BP algorithm, the RBP can improve the channel decoding performance of BP significantly. As for the source encoding algorithm, the RBP also performs well with short codeword length. We also calculate the theoretical performance bounds in short length regimes. Compared with these bounds, the proposed LDPC code can serve as a good SSC in short length regime.

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Lee, Yi-chen, and 李義成. "Simulation and Comparison of MOSFETs with Different Gate Structure and Channel Length." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/67784326403871570677.

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碩士 逢甲大學 資訊電機工程碩士在職專班 94 It is known that planar bulk metal-oxide-semiconductor field effect transistors (MOSFETs) play a curcial role in modern microelectronics industry. The device channel nowadays entered sub-100 nanometer (nm) regions; therefore, device material, fabrication technology, and device structure have been of great interests. New device structures may have promising characteristics, and open an interesting research direction. In this thesis, we study MOSFETs with different gate structures for sub-32 nm technology. Four gate structures, the single-gate, the double-gate, the triple-gate, and the gate-all-around-gate MOSFETs are simulated and compared. We use device simulation software to numerically study the gate structure effect on the electrical characteristics of MOSFETs. The on and off currents, the threshold voltage roll-off, and the short-channel effects are explored and compared. Among device structures, due to perfect channel controbility, results show that the gate-all-around-gate MOSFETs posses fascinating characteristics; in particular, for sub-32 nm technology. We believe that this investigation is useful for MOSFET fabricatin with different gate structures.

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Yeh, Chun-Chia, and 葉俊佳. "Characterization of Gate Leakage Current and Channel Length of Nanometer-scaled MOSFETs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/79489110569213786088.

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博士 國立清華大學 電子工程研究所 96 This dissertation contains the DC characterization of nanometer-scaled metal-oxide-semiconductor field-effect-transistors. Two major achievements are obtained: the establishment of a gate leakage current model and accurate parameter extraction from the drain to source current-voltage relations. In first achievement, a mathematical method of modeling the gate leakage current IG is presented. Both the shallow trench isolation effect and the source drain extension effect on IG are included. With suitably chosen transistor dimensions the parameter extraction can be performed with the devices’ drawn size, the troublesome effective device length and width is not necessary in this model. The extracted parameters were used to predict IG of devices with other different dimensions. Transistors fabricated with 90nm and 65nm technologies were examined. The extracted parameters and their temperature dependence were used to predict IG of devices with other dimensions, excellent accuracy is verified. In second achievement, the concepts of shift-and-ratio (S&R) method are used. According to this foundation, we point out some different viewpoints that include a drain current corrected by gate leakage current, surface potential, velocity saturation model, and diffusion current portion of the drain current. After considering these factors which relate to the effective channel length (Leff) and source/drain series resistance (RSD) and we can get eight nonlinear equations. Then, iteration method is applied to solve these equations to obtain accurate RSD and Leff. Because RSD and Leff are two inseparable device parameters, therefore, the iterated steps can obtain more accurate parameters simultaneously. The results differ from that obtained from the original S&R method; both our outcomes are function of VGS. Furthermore, our algorithm only needs to measurement IDS-VGS curve before calculating the results. Therefore, this proposed method can be easily implemented in MOSFET’s modeling.

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Lin, Po-Han, and 林鉑涵. "Fixed-Length Joint Source-Channel Coding System for Generally Non-uniform Sources." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/67478478183797376280.

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碩士 國立交通大學 電信工程研究所 101 In this thesis, the design of fixed-length joint source-channel error-correcting codes (FLEC) for generally non-uniform source statistics is considered as contrary to the usual variable-length joint source-channel error-correcting coding system. Such a system has the advantage that the receiver can identify easily the codeword margin via a length counter. Two different approaches are attempted. We first derive the union bounds of decoding errors of the FLECs for generally non-uniform sources, and then find the FLECs that have acceptably good union bound values. Since the first approach is only suitable for FLECs of short block length, the second approach assumes the turbo code structure and modifies the turbo decoding metrics to adapt to the tranceiving of non-uniform information. Simulations show that the first pro-posed approach outperforms the traditional tandem scheme that concatenates the Huffman source code with a BCH code, while the second proposed approach beats the concatenation of the Huffman source code with a turbo code of similar rate.

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Lin, Yu-Sheng, and 林育生. "Performance Dependent on Width-to-Length Ratio of Strained SiGe Channel MOSFETs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/12612657054974364320.

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碩士 國立高雄大學 電機工程學系碩士班 101 This thesis measures the n- and p-MOSFETs fabricated through 65 nm high k/metal gate CMOSFET process flow. The channels of the Si cap on SiGe were compared with Si-only channels. We found that biaxial compressive strain effect on device performance depends on channel width and channel length. The results indicate that a high W-L ratio in the <110> p-channel and n-channel can degradation performance of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve performance; but the ratio should at least be below 2.5 in this thesis. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation.

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Wei, Liang Zih, and 梁秭瑋. "Effect of Width and Length of ZnO Channel on Field Effect Transistor." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/rau4bq.

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碩士 大葉大學 醫療器材設計與材料碩士學位學程 107 In this experiment, a ZnO film was deposited on a glass substrate (Corning Engle 2000) using a magnetron RF sputtering system with RF output of 100 W at 150 mtorr working pressure. According to the different devices of MESFET and MISFET, the ZnO thin film channel is fabricated by using different process of photolithography, and Au is used as the gate metal. A nitrogen-doped ZnO thin film was fabricated between the gate metal of the type 2 MESFET (MESFET2) and the ZnO thin film channel. In the type 1 and type 2 MISFET (MISFET1 and MISFET2), an aluminum oxide layer was grown between the gate metal and the ZnO thin film channel. A non-conductive polymer is applied as an insulating layer between the gate of the type 3 MISFET (MISFET3) and the ZnO thin film channel. The samples prepared by different processes were analyzed by HP4155A semiconductor characteristic measuring instrument to investigate the voltage modulation effects of different process FETs.

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Wang, Chung-Hsuan, and 王琮玄. "Studies of the mechanism of sieving DNA by length with nano-channel matrices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/84018672743346901326.

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博士 國立清華大學 物理系 101 The device with nano-channel matrices was fabricated and used to sieve DNA molecules. Channel matrices, which had been fabricated with the widths of individual nano-channel were 50, 200, and 450 nano-meters. The interval between two adjacent rows of nano-channels varies from 1 μm to 3 μm. Three different kinds of DNA molecules including Plasmid-2.8 kbps (~1 μm), λ-48.5 kbps (~16 μm) and T4-166 kbps (~55 μm) were used in these experiments. It was found that the mobility of shorter DNA molecules were not always greater than that of longer ones. Overall, we could divide the results into three parts. (1) In the width 50 nm channel matrices, the result of this is like the result of gel electrophoresis, which showed the mobility decreased monotonically with the length of DNA molecules. (2) In the width 200 nm channel matrices, the entropic trapping dominated, longer molecules have a higher probability to escape trapping regions due to high successful attacking frequency with the larger contact area, so the mobility increased monotonically with the length of DNA molecules and the result is reverse to the aforementioned result. (3) As different lengths of DNA molecules sieved in the width 450 nm channel matrices, the Ogston mechanism dominated, molecules could pass through the nanochannel without great deformation so the mobility decreased monotonically with the length of DNA molecules. Besides these results, compared with regular micro- and nano-trenches of previous authors' works, DNA molecules electrophoresis in these trenches was just one direction confined, but the motion of DNA molecules was confined in both directions perpendicular to the direction of drift of DNA molecules in our chip. Compared with time-consuming (1~24 hrs) and large sample consumption of conventional methods, gel DNA electrophoresis and Pulsed field gel electrophoresis, DNA molecules could be separated in 10 minutes and low sample consumption by this technique. Thus, this work not only provides a more helpful method for understanding separation processes in gel DNA electrophoresis, but also provides a more efficient method to sieve different lengths of DNA molecules.

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44

CHANG, CHIA-HSIEN, and 張家憲. "Channel length reduction and source/drain resistance of FinFETs under source/drain extensions." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ma7kc6.

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碩士 明新科技大學 電子工程系碩士班 106 The applications of FinFET device with advanced nano-node process are more and more adopted in the commercial electronic products, especially in high-performance and high-density products. In order to obtain the optimal electrical characteristics and controllable process window for the desired devices, the electrical parameters for devices must be strictly monitored and verified. In this work, one set of 90nm lithographical masks with hard masks were applied to form the FinFET devices with the adjustment of exposure energy in lithography and the control of parameters of dry etch process. Using these fabricated FinFET devices, we probe the channel length reduction (ΔL) and the source/drain resistance (RSD) related to the source/drain extension lengths (LSDE).Besides correlating the published literatures, we hope this work can provide some niche benefiting the IC designers and process teams in the optimization of device density and controllable process window. In this measurement experiment, there are two LSDE: 60 and 160nm. The tested devices with fixed channel length (W=0.11μm) were L=(0.12, 0.16, 0.24, 0.5, 2, 10)μm for p-type FinFETs and L=(0.12, 0.16, 0.24, 2, 10)μm for n-type FinFETs, respectively. The extracted consequences for p-type FinFETs show ΔL=5.51nm and RSD=44.1kΩ at LSDE=60nm and ΔL=126nm and RSD=102kΩ at LSDE=160nm. At the same time, the extracted for n-type FinFETs demonstrate ΔL=9.1nm and RSD=25.4kΩ at LSDE=60nm and ΔL=22.5nm and RSD=51.8kΩ at LSDE=160nm. Because the doping species and concentration for n-type or p-type FinFETs are different, the extracted results are also various.

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45

RAJAIE, TARANNOM. "BELIEF PROPAGATION DECODING OF FINITE-LENGTH POLAR CODES." Thesis, 2012. http://hdl.handle.net/1974/6996.

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Polar codes, recently invented by Arikan, are the first class of codes known to achieve the symmetric capacity for a large class of channels. The symmetric capacity is the highest achievable rate subject to using the binary input letters of the channel with equal probability. Polar code construction is based on a phenomenon called channel polarization. The encoding as well as the decoding operation of polar codes can be implemented with O(N logN) complexity, where N is the blocklength of the code. In this work, we study the factor graph representation of finite-length polar codes and their effect on the belief propagation (BP) decoding process over Binary Erasure Channel (BEC). Particularly, we study the parity-check-based (H-Based) as well as the generator based (G-based) factor graphs of polar codes. As these factor graphs are not unique for a code, we study and compare the performance of Belief Propagation (BP) decoders on number of well-known graphs. Error rates and complexities are reported for a number of cases. Comparisons are also made with the Successive Cancellation (SC) decoder. High errors are related to the so-called stopping sets of the underlying graphs. we discuss the pros and cons of BP decoder over SC decoder for various code lengths. Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2012-01-31 17:10:59.955

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46

Hsu, W. C., and 許王誠. "Fabrication and Characterization of Polysilicon Thin Film Transistors With Various Channel Length/Width Ratios." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/72276524929696062146.

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碩士 南台科技大學 電機工程系 94 Undoped α-Si films and Poly-Si films have been employed to fabricate α-Si thin film transistors (α-Si TFTs) and poly-silicon thin film transistors (poly-Si TFTs) on glass and Si wafer, respectively. This study aims to investigate the effects of different gate oxide, buffer layer and channel W/L ratios on TFT devices. The results show that TEOS-base gate oxide provides superior electric properties for Poly-Si TFTs than E-beam gate oxide, including a steeper sub-threshold slope (S.S.) and a higher Ion/Ioff current ratio (>10-4). These results reveal that the step-coverage and film density of TEOS-base oxide deposited by LPCVD are better than that of E-beam evaporation. In order to fabricate TFTs on glass substrate at low temperatures, E-beam SiO2 was used as a buffer layer. The results show that the a-Si TFTs with a SiOx buffer layer on glass have much lower leakage current because of a better interface between P-Si and the glass. Based on this result, buffer layer is considered as an important component for TFTs. Sputter SiO2 was also used as another buffer material in the structure of TFTs. Compare to sputter SiO2 buffer layer, a-Si TFT devices with an E-beam oxide buffer layer provide lower leakage (Ioff) and saturation current (Isat). The result should be due to the use of reactive Si-O2 sputter process instead of SiO2 target sputtering. Finally, the channel with various width (2μm、5μm、10μm、20μm) and various length (2μm、5μm、10μm、20μm) have been investigated. Results reveal that the Id-Vg curves of the L= 2μm TFT devices are rather poor with low saturation current. This is should be the reason for the poor layer-to-layer alignment with our photolithography system for dimensions less than 5μm. When L> 2μm, the Id-Vg curves of TFT devices are much better, including low leakage current, high and stable saturation current. For devices with W/L= 10/10μm, the TFTs exhibit the best electrical properties. When the channel width is fixed, the sub-threshold slope and saturation current of TFT devices become steeper and larger with increasing channel length. In all cases, devices with W/L= 1 was found to perform the best characteristics in this study.

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47

TSENG, CHUN-KAI, and 曾俊凱. "Fitting Simulation of FinFET with 90 Nanometer Channel Length and Broadband Class E Amplifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/8bvkdw.

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碩士 明新科技大學 電子工程系碩士班 107 Three dimensional FinFET(Fin Field Effect Transistor) devices are under high controllability at nano-meter scale because the leakage current is effectively suppressed through the fin-structural gates. Therefore, the devices are popular and feasible to the integration circuit design as the scale continues to shrink. In this paper, 90nm channel has been studied at various temperatures, in which higher temperatures correspond to more phonons and those phonons may directly scatter with the carriers. ID-VG curves demonstrate better trans-conductance at higher temperature while higher ID-VD characteristic curves are not substantially influenced. In addition, radio-frequency integrated circuit using Agilent Design System (ADS) on Power Amplifier (PA) with central frequencies, such as 5.0GHz, is promoted to be applicable to wide-band ranges. Through the impedance matching, especially on S11 and S22, various inductances and capacitances are preset and the reflective coefficients are adjusted by tuning the circuit and then reduced to be as low as zero so that the available frequency ranges can be pinned down. As for the noise figures of the PA circuit, they are also proved to low enough to be advisable to integrated circuit designs.

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48

Balaji, Chikkam Ramakrishna, and Bichitrananda Behera. "Growth of boundary layer thickness and length of fully developed flow in open channel." Thesis, 2014. http://ethesis.nitrkl.ac.in/6493/1/E-27.pdf.

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The aim of the present work was to study the growth of boundary layer thickness and length of fully developed flow in an open channel flow which has a great applications in fields like, hydrodynamics (ships, torpedoes, submarines), wind engineering (buildings, water towers, bridges), aerodynamics (airplanes, rockets, projectiles), ocean engineering (buoys, breakwaters, cables) and transportation (trucks, automobiles, cycles). Boundary layer thickness and length of fully developed flow is crucial for solving many engineering problems such as management of rivers and floodplains, it is important to understand the behavior of flows within compound channels for designing of flood control, hydraulic structure, sedimentation, water management and excavation. In pipe flow, where boundary layer thickness is equal to radius of pipe which can be obtained easily whereas one finds difficulty in obtaining boundary layer thickness in open channels due to the presence of free surface. This challenge motivated us to study the growth of boundary layer thickness and length of fully developed flow in open channel flow. Experiments were performed to measure the characteristics of a boundary layer and fully developed flow by making use of velocity profiles developing on a rough concrete surface placed in an open channel flow from bottom to close proximity to the free surface. Section wise velocity measurements were made with a pitot tube-manometer combination and Acoustic Doppler velocimeter system along the flow depth ranging from 0, 0.2h, 0.4h, 0.6h, 0.8h.

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49

Garga, Ganesh. "Flexible Constraint Length Viterbi Decoders On Large Wire-area Interconnection Topologies." Thesis, 2009. https://etd.iisc.ac.in/handle/2005/975.

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To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for ﬂexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

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50

Garga, Ganesh. "Flexible Constraint Length Viterbi Decoders On Large Wire-area Interconnection Topologies." Thesis, 2009. http://hdl.handle.net/2005/975.

Full text

Abstract:

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for ﬂexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

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