Relevant bibliographies by topics / Delay and noise modelling in VLSI circuits

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Delay and noise modelling in VLSI circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Delay and noise modelling in VLSI circuits"

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Pamunuwa, D., S. Elassaad, and H. Tenhunen. "Modelling noise and delay in VLSI circuits." Electronics Letters 39, no. 3 (2003): 269. http://dx.doi.org/10.1049/el:20030208.

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Jayanthy, S., M. C. Bhuvaneswari, and Keesarapalli Sujitha. "Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm." VLSI Design 2012 (January 19, 2012): 1–10. http://dx.doi.org/10.1155/2012/745861.

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As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG) method based on a modified Fanout Oriented (FAN) to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage,
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Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (2019): 496. http://dx.doi.org/10.3390/electronics8050496.

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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on l
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Bansal, Deepika, Bal Chand Nagar, Brahamdeo Prasad Singh, and Ajay Kumar. "Improved Domino Logic Circuits and its Application in Wide Fan-In OR Gates." Micro and Nanosystems 12, no. 1 (2020): 58–67. http://dx.doi.org/10.2174/1876402911666190716161631.

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Background: Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability. Objective: In this paper, two efficient and high-performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high-performance domino
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Duganapalli, Kishore, Ajoy K. Palit, and Walter Anheier. "Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim." Journal of Circuits, Systems and Computers 25, no. 03 (2015): 1640018. http://dx.doi.org/10.1142/s0218126616400181.

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With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have bee
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SENTHILPARI, C., K. DIWAKAR, and AJAY KUMAR SINGH. "LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 581–96. http://dx.doi.org/10.1142/s0218126609005277.

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As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI
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Kondapalli, Soumya, Arjuna Madanayake, and Len Bruton. "Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters." International Journal of Antennas and Propagation 2012 (2012): 1–19. http://dx.doi.org/10.1155/2012/234263.

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A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time through
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"Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2020): 1673–79. http://dx.doi.org/10.35940/ijitee.b7841.129219.

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FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimi
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"Performance Analysis of Karatsuba Vedic Multiplier and Computation Sharing Multiplier in the Adaptive Filter Design." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2019): 4425–29. http://dx.doi.org/10.35940/ijitee.b7454.129219.

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As real time signals change continuously, adaptive filtering is required for noise cancellation. An adaptive filter is one whose characteristics can be modified by adjusting its parameters according to an optimization algorithm The adaptive filtering operations can be implemented as a sequence of logic operations on a Digital Signal Processing (DSP) chip,Gate Arrays such as FPGA or Application Specific Integrated Circuits. There is always a tradeoff in the parameters area, power and speed in VLSI. This paper provides the implementation of adaptive LMS Filter using different types of multiplier
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Kajal and Vijay Kumar Sharma. "A Novel Low Power Technique for FinFET Domino OR Logic." Journal of Circuits, Systems and Computers, October 29, 2020, 2150117. http://dx.doi.org/10.1142/s0218126621501176.

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Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation
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Dissertations / Theses on the topic "Delay and noise modelling in VLSI circuits"

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Pamunuwa, Dinesh. "Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3659.

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<p>The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle.</p><p>This thesis address
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Jiang, Zhongwei. "Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8915.

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Test power is an important issue in deep submicron semiconductor testing. Too much power supply noise and too much power dissipation can result in excessive temperature rise, both leading to overkill during delay test. Scan-based test has been widely adopted as one of the most commonly used VLSI testing method. The test power during scan testing comprises shift power and capture power. The power consumed in the shift cycle dominates the total power dissipation. It is crucial for IC manufacturing companies to achieve near constant power consumption for a given timing window in order to keep the
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Conference papers on the topic "Delay and noise modelling in VLSI circuits"

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Raj, Riya, M. S. Bhat, and S. Rekha. "Library Characterization: Noise and Delay Modeling." In 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER). IEEE, 2018. http://dx.doi.org/10.1109/discover.2018.8674081.

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Maheshwari, V., Kapil Khare, Suvra Mukherjee, R. Kar, and D. Mandal. "Peak noise and noise width modelling for RLC global interconnects in deep submicron VLSI circuits." In 2013 IEEE Conference on Information & Communication Technologies (ICT). IEEE, 2013. http://dx.doi.org/10.1109/cict.2013.6558113.

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Bai, Geng, Sudhakar Bobba, and Ibrahim N. Hajj. "Static timing analysis including power supply noise effect on propagation delay in VLSI circuits." In the 38th conference. ACM Press, 2001. http://dx.doi.org/10.1145/378239.378489.

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Bozorgzadeh, Bardia, Shahab Shahdoost, and Ali Afzali-Kusha. "Delay variation analysis in the presence of power supply noise in nano-scale digital VLSI circuits." In 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2014. http://dx.doi.org/10.1109/mwscas.2014.6908366.

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