Relevant bibliographies by topics / Delay circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Delay circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 31 July 2024

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Journal articles on the topic "Delay circuits"

1

Hsiao, Michael S. "Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits." VLSI Design 15, no. 1 (2002): 407–16. http://dx.doi.org/10.1080/1065514021000012020.

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Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic
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Bansal, Deepika, Brahmadeo Prasad Singh, and Ajay Kumar. "Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic." Bulletin of Electrical Engineering and Informatics 6, no. 2 (2017): 122–32. http://dx.doi.org/10.11591/eei.v6i2.597.

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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s an
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Blaschenko, O. D., E. P. Razmenov, and I. M. Starkov. "Modernization of Control of Switching-on the Circuits of a Two-Circuit Pulse Current Generator." Elektronnaya Obrabotka Materialov 58, no. 1 (2022): 93–100. http://dx.doi.org/10.52577/eom.2022.58.1.93.

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A possibility of developing control devices for switching on circuits in double-circuit pulse cur-rent generators in various discharge-pulse technologies is shown. The advantages of using those devices in the technology of a high-voltage electrochemical explosion are described, which requires a specific energy input based on the time delays between switching on the circuits. A scheme is proposed for automatically starting the second circuit in a double-circuit pulse current generator, which provides smooth (non-discrete) adjustment of the time delay of operation and realizing a wider range of
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Wróblewski, Artur, Christian V. Schimpfle, Otto Schumacher, and Josef A. Nossek. "Minimizing Spurious Switching Activities with Transistor Sizing." VLSI Design 15, no. 2 (2002): 537–45. http://dx.doi.org/10.1080/1065514021000012156.

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In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows equalizing different path delays without influencing the total delay of the circuit. Unfortunately, not only the delay, but also power consumption circuits depend on the transistor sizes. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capa
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Chandrasekhar, Mandalagiri S., Robert H. McCharles, and David E. Wallace. "Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits." VLSI Design 5, no. 2 (1997): 125–40. http://dx.doi.org/10.1155/1997/30941.

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Traditionally logic synthesis and layout tools optimize designs without interaction between them. Lack of communication between the two tools often results in inferior post-layout circuit implementations. This paper presents three aspects of coupling synthesis with layout to minimize post-layout area and delay of circuits. It presents two new techniques for computing net-weights based on timing slacks, and shows how performance improvement with little overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logic equivalence information in circuits to minimize circuit
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Panda, Rajendran, and Farid N. Najm. "Post-Mapping Transformations for Low-Power Synthesis." VLSI Design 7, no. 3 (1998): 289–301. http://dx.doi.org/10.1155/1998/96768.

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We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that
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Raman and Ramnish Kumar. "Design and Performance Analysis of Inverter Using ECRL, MERL and PFAL." International Journal of Research in Informative Science Application & Techniques (IJRISAT) 1, no. 1 (2017): 27–34. http://dx.doi.org/10.46828/ijrisat.v1i1.20.

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In this paper, different low energy design techniques are analyzed to overcome the shortcoming of traditional circuits. An inverter circuit is used as a reference circuits to compare three adiabatic logic designs like ECRL, MERL and PFAL. The ECRL, MERL and PFAL designed inverter circuits are simulated by using mentor graphics VLSI design software Pyxis _v10.5_5_201606075 and the obtained results are compared in terms of rise time, fall time, transistor count, delay, slew rate etc. Finally, I calculated the delays, Slew rate and other parameter of PFAL based circuit results better as compared
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Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumpti
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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so
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Mohan, Navya, and J. P. Anita. "Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model." Cryptography 7, no. 1 (2023): 4. http://dx.doi.org/10.3390/cryptography7010004.

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The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel
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Dissertations / Theses on the topic "Delay circuits"

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Parameswaran, Nair Ravi Sankar. "Delay-insensitive ternary logic (DITL)." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Parameswaran_Nair_09007dcc803bc548.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.<br>Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).
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Rahimi, Kambiz. "Adaptive-delay sequential circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5907.

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Sayle, Roger Anthony. "Automated synthesis of delay-insensitive circuits." Thesis, University of Edinburgh, 1996. http://hdl.handle.net/1842/11374.

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The technological trend towards VLSI circuits built from increasing numbers of transistors continues to challenge the ingenuity of both designers and engineers. The use of asynchronous design techniques presents a method for taming the complexity of large concurrent VLSI system design and offers a number of attractive advantages over conventional design styles. In this thesis, we concentrate on the useful class of delay insensitive asynchronous circuits. These have the property that their correct operation is independent of the speed of the individual elements and the delays in the connecting
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Nabavi-Lishi, Abdolreza. "Delay and current evaluation in CMOS circuits." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=41166.

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An accurate and fast technique has been developed for computing the supply current as well as the delay in CMOS combinational circuits. It is based on a new analytical model of the CMOS inverter which is designed specifically to compute the maximum supply current and the delay without recourse to integration. If the current waveform is needed, integration is used only for the trailing edge. This model can be used not only to compute maximum supply current and delay in CMOS circuits, but also to detect dynamic hazards.<br>The extension to general CMOS circuits is achieved through a collapsing m
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Toms, William Benjamin. "Synthesis of quasi-delay-insensitive datapath circuits." Thesis, University of Manchester, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.488345.

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Möller, Anton. "Piezoelectric tuning of integrated photonic delay circuits." Thesis, KTH, Tillämpad fysik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-260415.

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Pham, Viet Thanh. "Memristor-based and time-delay nonlinear circuits." Doctoral thesis, Università di Catania, 2013. http://hdl.handle.net/10761/1306.

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The pioneering works of Prof. Leon O. Chua constructing electrical circuit (named Chua s circuit) which can display chaotic behaviors open a period with fruitful researches about nonlinear circuits. A considerable amount of different nonlinear circuits has been introduced and their numerous applications have developed instantaneously. Complex dynamical characteristics of nonlinear circuits are used to model complex systems, to generate random numbers or to secure informations. There are three nonlinear systems which have received much attention recently: time delay system, Cellular Neural Netw
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Özkaramanli, Hüseyin Mehmet. "Distributed circuits in integrated circuits : signal integrity, crosstalk and delay in VLSI /." Thesis, Connect to Dissertations & Theses @ Tufts University, 1995.

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Thesis (Ph.D.)--Tufts University, 1995.<br>Submitted to the Dept. of Electrical Engineering. Includes bibliographical references (leaves 237-253). Access restricted to members of the Tufts University community. Also available via the World Wide Web;
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Jia, Cheng. "A Delay-Locked Loop for Multiple Clock Phases/Delays Generation." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7470.

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A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using
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Khordoc, Karim. "A MOS switch-level simulator with delay calculation /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65461.

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Books on the topic "Delay circuits"

1

Krstić, Angela. Delay Fault Testing for VLSI Circuits. Springer US, 1998.

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Krstić, Angela, and Kwang-Ting Cheng. Delay Fault Testing for VLSI Circuits. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5597-1.

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Krstić, Angela. Delay fault testing for VLSI circuits. Kluwer Academic Publishers, 1998.

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Madsen, Jan. The impact of gate ordering on circuit delay. Technical University of Denmark, 1988.

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Jayanthy, S., and M. C. Bhuvaneswari. Test Generation of Crosstalk Delay Faults in VLSI Circuits. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-2493-2.

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Sivaraman, Mukund. A Unified Approach for Timing Verification and Delay Fault Testing. Springer US, 1998.

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Sivaraman, Mukund. A unified approach for timing verification and delay fault testing. Kluwer Academic, 1998.

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F, Sproull Robert, and Harris David, eds. Logical effort: Designing fast CMOS circuits. Morgan Kaufmann Publishers, 1999.

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Mahmoud, Magdi S. Switched time-delay systems: Stability and control. Springer, 2010.

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Vijayan, Senthilkumar Dharmapuri, and SpringerLink (Online service), eds. Dynamics of Nonlinear Time-Delay Systems. Springer-Verlag Berlin Heidelberg, 2010.

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Book chapters on the topic "Delay circuits"

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Asadi, Farzin. "Delay Circuits." In Industrial Electronic Circuits Laboratory Manual. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-50773-1_8.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Delay Models." In Asynchronous Circuits. Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_3.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Bi-Bounded Delay Models." In Asynchronous Circuits. Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_8.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Up-Bounded-Delay Race Models." In Asynchronous Circuits. Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_6.

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Islam, Mahfuzul, and Hidetoshi Onodera. "Monitor Circuits for Cross-Layer Resiliency." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_16.

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AbstractCross-layer resiliency has become a critical deciding factor for any successful product. This chapter focuses on monitor circuits that are essential in realizing the cross-layer resiliency. The role of monitor circuits is to establish a bridge between the hardware and other layers by providing information about the devices and the operating environment in run-time. This chapter explores delay-based monitor circuits for design automation with the existing cell-based design methodology. The chapter discusses several design techniques to monitor parameters of threshold voltage, temperature, leakage current, critical delay, and aging. The chapter then demonstrates a reconfigurable architecture to monitor multiple parameters with small area footprint. Finally, an extraction methodology of physical parameters is discussed for model-hardware correlation. Utilizing the cell-based design flow, delay-based monitors can be placed inside the target digital circuit and thus a better correlation between monitor and target circuit behavior can be realized.
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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Limitations of Up-Bounded Delay Models." In Asynchronous Circuits. Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_13.

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Xanthopoulos, Thucydides. "Digital Delay Lock Techniques." In Integrated Circuits and Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0261-0_6.

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Josephs, Mark B., and Jan Tijmen Udding. "The Design of a Delay-Insensitive Stack." In Designing Correct Circuits. Springer London, 1991. http://dx.doi.org/10.1007/978-1-4471-3544-9_8.

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Brown, Geoffrey M. "Towards Truly Delay-Insensitive Circuit Realizations of Process Algebras." In Designing Correct Circuits. Springer London, 1991. http://dx.doi.org/10.1007/978-1-4471-3544-9_7.

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Gammelgaard, Anders. "Implementation conditions for delay insensitive circuits." In PARLE '89 Parallel Architectures and Languages Europe. Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/3540512845_49.

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Conference papers on the topic "Delay circuits"

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Rodwell, M. J. W., K. J. Weingarten, and D. M. Bloom. "Picosecond Sampling of Integrated Circuits." In Picosecond Electronics and Optoelectronics. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/peo.1987.wa2.

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GaAs microwave integrated circuits are now being developed for operation at frequencies as high as 40 GHz, while GaAs digital IC’s have been demonstrated with ring-oscillator propagation delays of 5-10 ps, with gate delays of 50-100 ps for larger-scale circuits. Digital IC’s are currently tested only by indirect technique (multistage propagation delay or cycle times), while microwave circuits are tested only by external scattering parameter measurement; if the circuit does not perform to expectations, the cause is not easily identified. Electrooptic sampling, providing picosecond-resolution me
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Thompson, Richard A. "Optimizing Photonic Variable-Integer-Delay Circuits." In Photonic Switching. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/phs.1987.fd4.

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We present photonic circuits for temporal processing of photonic signals by a controlled variation in the delay of a photonic signal path. Since they provide variable delay in increments of some fixed elementary value, we call them variable integer delays. We present three structures, called parallel, series re-entrant, and series feed-forward. One application is in a photonic time-slot interchanged Pl in which all the data from an input time-slot experience the appropriate delay to emerge in the assigned time-slot in the output. We optimize two parameters: the total number of switches in the
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Clymer, B. D., and J. W. Goodman. "Detection of optically distributed clock signals for very large scale integrated circuits." In OSA Annual Meeting. Optica Publishing Group, 1985. http://dx.doi.org/10.1364/oam.1985.tue1.

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The miniaturization of integrated circuit elements by scaling in very large scale integrated circuits (VLSI) has created a great deal of interest in the timing skew associated with transmitting signals via circuit lines to remote locations on a chip. As device sizes decrease and chip sizes increase with technological advances, the speed of the circuits on a VLSI chip becomes limited by signal transmission delays rather than device switching delays. Of particular interest is the clock signal that allows the system operations to be timed synchronously with one another. Parasitic transmission lin
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D'Alessandro, Crescenzo, Andrey Mokhov, Alex Bystrov, and Alex Yakovlev. "Delay/Phase Regeneration Circuits." In 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07). IEEE, 2007. http://dx.doi.org/10.1109/async.2007.14.

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Li, Qinqin, Caiting Xing, and Xingyuan Tong. "Voltage Detection Circuit with Delay for Power Management Circuits." In 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2022. http://dx.doi.org/10.1109/icicm56102.2022.10011273.

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Pandita, Bupesh. "Delay calibration circuit for delay lines." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7168767.

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Wiesenfeld, J. M., R. S. Tucker, A. Antreasyan, C. A. Burrus, and A. J. Taylor. "Electro-Optic Sampling of High-Speed, InP-Based Integrated Circuits." In Picosecond Electronics and Optoelectronics. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/peo.1987.wa4.

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We report the application of electro-optic sampling[1-3] to measurements of waveforms internal to a high-speed InP integrated circuit. This is possible because InP is an electro-optic material with electro-optic coefficient comparable to that of GaAs. Waveforms and propagation delays through a two stage InGaAs/InP metal-insulator-semiconductor FET (MISFET) inverter circuit[4,5] have been measured. The observed propagation delay through an individual FET is 21±7 ps. The measurement uses an electro-optic sampling system based on a 1.3 μm InGaAsP injection laser[3] that is gain-switched. This wor
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Jang, Eun Jung, Jaeyong Chung, and Jacob A. Abraham. "Delay defect diagnosis methodology using path delay measurements." In 2011 International Symposium on Integrated Circuits (ISIC). IEEE, 2011. http://dx.doi.org/10.1109/isicir.2011.6131960.

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Wu, Kai-Chiang, Cheng-Tao Hsieh, and Shih-Chieh Chang. "Delay variation tolerance for domino circuits." In the 2006 conference. ACM Press, 2006. http://dx.doi.org/10.1145/1118299.1118389.

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Benabboud, Youssef, Alberto Bosio, Luigi Dilillo, et al. "Delay Fault Diagnosis in Sequential Circuits." In 2009 Asian Test Symposium. IEEE, 2009. http://dx.doi.org/10.1109/ats.2009.16.

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Reports on the topic "Delay circuits"

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Martin, Alain J., and Pieter J. Hazewindus. Testing Delay-Insensitive Circuits. Defense Technical Information Center, 1990. http://dx.doi.org/10.21236/ada447730.

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Pham, Anh-Vu. Development of True Time Delay Circuits. Defense Technical Information Center, 2014. http://dx.doi.org/10.21236/ada608902.

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Penzes, Paul I., Mika Nystroem, and Alain J. Martin. Transistor Sizing of Energy-Delay-Efficient Circuits. Defense Technical Information Center, 2005. http://dx.doi.org/10.21236/ada437313.

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Penzes, Paul I., Mika Nystrom, and Alain J. Martin. Transistor Sizing of Energy-Delay-Efficient Circuits. Defense Technical Information Center, 2006. http://dx.doi.org/10.21236/ada443257.

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Manohar, Rajit, and Alain J. Martin. Quasi-Delay-Insensitive Circuits are Turing-Complete. Defense Technical Information Center, 1995. http://dx.doi.org/10.21236/ada444284.

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Martin, Alain J. The Limitations to Delay-Insensitivity in Asynchronous Circuits. Defense Technical Information Center, 1990. http://dx.doi.org/10.21236/ada447737.

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Park, Hoon. Formal Modeling and Verification of Delay-Insensitive Circuits. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.2635.

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Brocato, Robert Wesley. Delay locked loop integrated circuit. Office of Scientific and Technical Information (OSTI), 2007. http://dx.doi.org/10.2172/921727.

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Izumi, N. A Minor Modification of Leading Edge Discriminator Circuitry with a Delay Line for Baseline Restoration of Scintillation Detectors. Office of Scientific and Technical Information (OSTI), 2003. http://dx.doi.org/10.2172/15005258.

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