Journal articles: 'Delay-latch'

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Hatefinasab, Seyedehsomayeh, Noel Rodriguez, Antonio García, and Encarnacion Castillo. "Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit." Electronics 10, no. 11 (2021): 1256. http://dx.doi.org/10.3390/electronics10111256.

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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Xu, Hui, Xuan Liu, Guo Yu, Huaguo Liang, and Zhengfeng Huang. "LIHL: Design of a Novel Loop Interlocked Hardened Latch." Electronics 10, no. 17 (2021): 2090. http://dx.doi.org/10.3390/electronics10172090.

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A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches.

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Xu, Hui, Le Zhou, Huaguo Liang, Zhengfeng Huang, Cong Sun, and Yafei Ning. "High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs." Electronics 10, no. 20 (2021): 2515. http://dx.doi.org/10.3390/electronics10202515.

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To avoid soft errors in integrated circuits, this paper presents two high-performance latch designs, namely LOCDNUTRL and LOCTNUTRL, protecting against double-node upset (DNU) and triple-node upset (TNU) in the harsh radiation environment. First, the LOCDNUTRL latch consists of two single-node upset (SNU) self-recovery modules and uses a C-element at the output. Next, based on the LOCDNUTRL latch, the LOCTNUTRL latch is proposed, which uses five extra inverters to fully tolerate TNU. Unlike the LOCDNUTRL latch, which uses an output level C-element as a voter, LOCTNUTRL is insensitive to the high-impedance state (HIS), making it more reliable for aerospace applications. The HSPICE simulation results, using a predictive technology model, show that the LOCTNUTRL latch saves 57.74% delay, 7.7% power consumption, 11.74% area cost, and 63.59% power delay production (PDP) on average compared with the state-of-the-art hardened latches. The process, voltage, and temperature variation analysis show that the proposed two latches are less sensitive to changes.

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Madheswaran, Sivasakthi, and Radhika Panneerselvam. "Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology." International Journal of Power Electronics and Drive Systems (IJPEDS) 15, no. 2 (2024): 1052. http://dx.doi.org/10.11591/ijpeds.v15.i2.pp1052-1060.

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Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

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Madheswaran, Sivasakthi, and Radhika Panneerselvam. "Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology." International Journal of Power Electronics and Drive Systems (IJPEDS) 15, no. 2 (2024): 1052–60. https://doi.org/10.11591/ijpeds.v15.i2.pp1052-1060.

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Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

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Rajaei, Ramin, Mahmoud Tabandeh, and Mahdi Fazeli. "Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550007. http://dx.doi.org/10.1142/s0218126615500073.

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In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

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Wu, Jin Rong, Ying Ju, Zhi Lun Lin, Chu Lian Lin, and Xiao Chao Li. "A Preamplifier-Latch Comparator with Reduced Delay Time for High Accuracy Switched-Capacitor Pipelined ADC." Applied Mechanics and Materials 303-306 (February 2013): 1842–48. http://dx.doi.org/10.4028/www.scientific.net/amm.303-306.1842.

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This paper presents a modified preamplifier-latch comparator for minimum latch delay and minimum input referred noise. The ratio of PMOS/NMOS in cross-coupled inverter is verified theoretically and optimized for minimum comparator delay. The cross-coupled load, the cascaded structure and the capacitor neutralization techniques are adopted to reduce the kickback noise and the input referred offset voltage. The comparator circuit is designed in a TSMC 0.35 um/3.3 V 2P4M CMOS process. Simulations show that the delay time of latch is declined by 18 percent after optimization and the maximum transfer delay time is only 384.5 ps. The peak to peak value of kickback noise is only 0.831uV in case of Vin,max=1.25 V, and the Monte Carlo simulation results show that equivalent input referred offset voltage is 4.56mV.

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Dai, Yanyun, Yanfei Yang, Nan Jiang, Pengjia Qi, Qi Chen, and Jijun Tong. "A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design." Electronics 11, no. 21 (2022): 3606. http://dx.doi.org/10.3390/electronics11213606.

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The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations.

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Vanak, Amin, and Reza Sabbaghi-Nadooshan. "Improvement of Power and Performance in NAND and D-Latch Gates Using CNFET Technology." Journal of Nano Research 33 (June 2015): 126–36. http://dx.doi.org/10.4028/www.scientific.net/jnanor.33.126.

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In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice. Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.

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Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over conventional comparators in noise and delay. A triple-latch feedforward (TLFF) comparator improves on the triple-tail fully dynamic comparator. The triple-latch feedforward (TLFF) dynamic comparator consists of three-stage latches and a parallel feedforward path. It has a smaller delay time than other circuit designs, especially for large differential input signals.

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Xu, Hui, Zehua Peng, Huaguo Liang, Zhengfeng Huang, Cong Sun, and Le Zhou. "HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch." Electronics 10, no. 20 (2021): 2457. http://dx.doi.org/10.3390/electronics10202457.

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A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

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S, Satheesh Kumar, and Kumaravel S. "Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 21. http://dx.doi.org/10.3390/jlpea9030021.

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Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature.

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Jiang, Jianwei, Wenyi Zhu, Jun Xiao, and Shichang Zou. "A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design." Electronics 7, no. 10 (2018): 247. http://dx.doi.org/10.3390/electronics7100247.

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Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design saves 805.24% delay-power-area product (DPAP) on average compared with other considered up-to-date double-upset tolerant latches, which means the proposed latch is a promising candidate for future highly reliable low-cost applications.

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Gupta, Kirti, Neeta Pandey, and Maneesha Gupta. "MCML D-Latch Using Triple-Tail Cells: Analysis and Design." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/217674.

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A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

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ZHAO, LEI, YINTANG YANG, and ZHANGMING ZHU. "A HIGH SPEED LOW POWER LATCHED COMPARATOR FOR SHA-LESS PIPELINED ADC." Journal of Circuits, Systems and Computers 22, no. 03 (2013): 1350004. http://dx.doi.org/10.1142/s0218126613500047.

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A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 μW at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-μm 3.3 V BiCMOS technology.

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Divi, Sathvik, Xiaotian Ma, Mark Ilton, et al. "Latch-based control of energy output in spring actuated systems." Journal of The Royal Society Interface 17, no. 168 (2020): 20200070. http://dx.doi.org/10.1098/rsif.2020.0070.

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The inherent force–velocity trade-off of muscles and motors can be overcome by instead loading and releasing energy in springs to power extreme movements. A key component of this paradigm is the latch that mediates the release of spring energy to power the motion. Latches have traditionally been considered as switches; they maintain spring compression in one state and allow the spring to release energy without constraint in the other. Using a mathematical model of a simplified contact latch, we reproduce this instantaneous release behaviour and also demonstrate that changing latch parameters (latch release velocity and radius) can reduce and delay the energy released by the spring. We identify a critical threshold between instantaneous and delayed release that depends on the latch, spring, and mass of the system. Systems with stiff springs and small mass can attain a wide range of output performance, including instantaneous behaviour, by changing latch release velocity. We validate this model in both a physical experiment as well as with data from the Dracula ant, Mystrium camillae , and propose that latch release velocity can be used in both engineering and biological systems to control energy output.

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Lin, Jin-Fa, Cheng-Yu Chan, and Shao-Wei Yu. "Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications." Electronics 8, no. 12 (2019): 1429. http://dx.doi.org/10.3390/electronics8121429.

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In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

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Cao, Menghua, and Weixun Tang. "The High-Speed Low-Power Dynamic Comparator." Journal of Physics: Conference Series 2113, no. 1 (2021): 012064. http://dx.doi.org/10.1088/1742-6596/2113/1/012064.

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Abstract This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.

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Tanusha, Beni Vyas, and Chandra Shubhash. "Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology." International Journal of Trend in Scientific Research and Development 3, no. 5 (2019): 1785–88. https://doi.org/10.5281/zenodo.3591483.

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In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Tanusha Beni Vyas | Shubhash Chandra "Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26707.pdf

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QIAO, FEI, HUAZHONG YANG, DINGLI WEI, and HUI WANG. "MODIFIED CONDITIONAL-PRECHARGE SENSE-AMPLIFIER-BASED FLIP-FLOP WITH IMPROVED SPEED." Journal of Circuits, Systems and Computers 16, no. 02 (2007): 199–210. http://dx.doi.org/10.1142/s0218126607003654.

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A modified version of conditional-precharge sense-amplifier-based flip-flop (mCP-SAFF) is proposed. By using the differential clocked CMOS (C2MOS) latch with one shared output holder and the conditional-precharge modules to simplify the sense-amplifier latch, the mCP-SAFF can achieve a much shorter input to output delay (D-to-Q delay) and more symmetrical rising/falling delays than those of the original conditional-precharge sense-amplifier-based flip-flops (CP-SAFF). Post-layout simulation results show that the mCP-SAFF, compared with the widely used conventional DFF, does not suffer neither timing nor area penalties and have achieved up to 34% of power reduction ratio and 33% of power-delay-product (PDP) reduction ratio, respectively. And the mCP-SAFF is comparable to the prevailing DFFs with regard to noise immunity performance.

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Park, Jung-Jin, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang, and Jinsang Kim. "A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design." Electronics 11, no. 15 (2022): 2465. http://dx.doi.org/10.3390/electronics11152465.

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Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches.

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Abhinav, V. Deshpande. "OFFSET REDUCTION IN THE DOUBLE TAILED LATCH-TYPE VOLTAGE SENSE AMPLIFIER." International Journal of Advanced Trends in Engineering and Technology 4, no. 2 (2019): 1–5. https://doi.org/10.5281/zenodo.3336352.

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This research paper presents an improved double tailed latch type voltage sense amplifier by using a latch load in the first stage. A latch load at the first stage provides the second stage with a large input difference voltage. Thus, completely removes the offset voltage due to the mismatch in the transistor pairs in the second stage of the Sense Amplifier. The performance of the Sense Amplifier was simulated by using the LT Spice with a threshold mismatch of 10% in between the transistor pairs of the second stage, where it achieved the offset removal at 3 GHz clock rate with V<sub>DD </sub>= 1. 2 Volts in a 90 nm CMOS technology. Since the input transistors of the first stage are in parallel with the transistor pair of the latch, it does not affect the delay.

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Priya, Nadendla Bindu, and Muralidharan Jayabhalan. "A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 41–43. http://dx.doi.org/10.35940/ijeat.a1012.1291s519.

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Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5-bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5-bit ADC operates voltage at 1.8 volts and consumes an average power.

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Zhu, Haomin. "Research on Four Different Designs of Comparator." Journal of Physics: Conference Series 2260, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2260/1/012003.

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Abstract Comparators contribute a significant role to analogue to digital converters (ADC). This paper describes and evaluates four excellent comparator optimisation schemes in recent years and analyses their advantages and disadvantages, providing ideas for the following comparator research direction. In addition, this paper introduces the design steps of each comparator optimisation scheme. It shows how the designer completes the final optimisation scheme step by step from the practical problems, which provides a specific reference for the comparator designers in the future. A double-tail latch-type comparator with dynamic bias adds a tail capacitor to the pre-amplifier to achieve low noise and high gain. Furthermore, a triple-tail dynamic comparator addresses a cascoded integrator. The new stage defines and attenuates the noise to achieve high speed and low noise. Compared to the triple-tail comparator, another design of a three-stage comparator is through adding a feedforward path between the first amplifier/latch and third latch to construct a triple-latch feedforward dynamic comparator. It is aimed to reduce delay and get low consumption in the region of the high voltage signal. Moreover, Edge-Pursuit Comparator (EPC) uses NAND gates and inverter delay cells to generate the comparison result between two input signals. Its circuit structure allows input noise tunability, automatic energy scaling, and low voltage tolerance.

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Lalitesh, Singh, and Bohra Surendra. "Design of Low Power High Speed D Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology." International Journal of Trend in Scientific Research and Development 2, no. 4 (2018): 1414–18. https://doi.org/10.31142/ijtsrd14138.

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In this paper we have proposed efficient designs of low power high speed D latch designed using stacked inverter and sleep transistor based on 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in the circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Lalitesh Singh | Surendra Bohra "Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: https://www.ijtsrd.com/papers/ijtsrd14138.pdf

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Lin, Zepeng. "Principle and performance analysis of low-power, high-speed, low-noise comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 83–93. http://dx.doi.org/10.54097/hset.v27i.3724.

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This paper studies three different structures proposed in recent years and discusses their advantages and properties respectively. A modified strong-arm latch voltage comparator is adapted to 3GHz operating frequency through additional current paths in the pre-amplifier. A latch-type comparator with a dynamic-biased pre-amplifier (DA) greatly reduces energy and improves noise performance through the stabilization of the input common-mode voltage. An FIA comparator further reduces energy and noise and greatly enhances the delay performance and the robustness of the comparator against different input common-mode voltage.

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Zhou, Jing, Jishan Zhang, and Chun Zheng. "STTSRL: Design of Triple-Node Upset Self-Recovery Latch Based on Schmidt Trigger." Journal of Physics: Conference Series 2658, no. 1 (2023): 012013. http://dx.doi.org/10.1088/1742-6596/2658/1/012013.

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Abstract With the continuous progress of semiconductor technology, the size of transistors has reduced, and the sensitivity of logic circuits to soft errors caused by radiation has enhanced. The multiple-node upset caused by radiation has affected the reliability of the circuit. This paper proposes a triple-node upset (TNU) self-recovery latch based on the Schmidt trigger (ST) for radiation hardness. The feedback loop is formed by connecting C-elements (CEs) and STs. Using the error filtering mechanism of CE and the hysteresis effect of ST is to realize the reliability of STTSRL. Under the 22 nm PTM process in HSPICE simulation, the STTSRL latch has TNU self-recoverability. Compared with the average value of the same recoverability latch proposed previously, the power consumption, delay, area, number of transistors, and PDAP are reduced by 44.85%, 53.32%, 40.34%, 19.24%, and 83.54%, respectively.

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Zghoul, Fadi Nessir, Yousra Hussein Al-Bakrawi, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 4 (2024): 3830. http://dx.doi.org/10.11591/ijece.v14i4.pp3830-3854.

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Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

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29

Ramdan, Ramdan, Lasmadi Lasmadi, and Paulus Setiawan. "Sistem Pengendali On-Off Lampu dan Motor Servo sebagai Penggerak Gerendel Pintu Berbasis Internet Of Things (IoT)." AVITEC 4, no. 2 (2022): 211. http://dx.doi.org/10.28989/avitec.v4i2.1317.

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The application of Internet of Things (IoT) technology will be one of the technologies that complements all fields along with the increasing use of smartphones. The purpose of this research is to design an on-off control system for lights and servo motors as door latch actuator based on IoT. The designed system can give commands on/off the lamp or door latch actuator and display the on/off indicators through an application on an Android smartphone. The system is designed using a Wemos D1 mini microcontroller as a processor, light sensor, infrared sensor, relay, servo motor, and RemoteXY app. Based on the test results, the system design has been successfully implemented and can be operated as an on-off controller via the internet with an Android smartphone. For each test performed, the system managed to provide an output that matches the given control input. The response time (delay) of the relay when on or off the lamp about 34,83 ms while the response time of the servo motor when opening and closing the latch takes about 38,93 ms. The notification shown corresponds to the state of the lamp and the state of the latch.

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30

You, Heng, Jia Yuan, Weidi Tang, Zenghui Yu, and Shushan Qiao. "A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS." Electronics 9, no. 5 (2020): 802. http://dx.doi.org/10.3390/electronics9050802.

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In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

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31

Wang, Shixin, Lixin Wang, Min Guo, Yuanzhe Li, and Bowang Li. "A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications." Electronics 12, no. 5 (2023): 1193. http://dx.doi.org/10.3390/electronics12051193.

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This paper presents a novel double node upset (DNU) self-recoverable and single event transient (SET) pulse filterable latch design in 28 nm CMOS technology. The loop structure formed by C-elements (CEs) ensures that the latch can self-recover from the DNUs. A Schmitt trigger at the output can filter out transient pulses from anywhere in the circuit. A clock-controlled inverter channel that connects the input to the output reduces the transmission latency. The simulation results show that the proposed design is completely immune to DNUs, and the delay power area product (DPAP) is reduced by more than 50% compared with the previous design.

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32

Dubey, Avaneesh K., and R. K. Nagaria. "Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect." Journal of Circuits, Systems and Computers 28, no. 09 (2019): 1950157. http://dx.doi.org/10.1142/s0218126619501573.

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This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[Formula: see text]nm and 180[Formula: see text]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[Formula: see text]nm result shows that the comparator has the total delay as low as 104.3[Formula: see text]ps and consumes only 0.288[Formula: see text]fJ of energy per conversion from a 0.8[Formula: see text]V supply. The mean value of input voltage error due to kickback noise is found as 306[Formula: see text]nV.

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33

Chen, Qi, Binyu He, Renjie Kong, Pengjia Qi, and Yanyun Dai. "Low-Power and High-Performance Double-Node-Upset-Tolerant Latch Using Input-Splitting C-Element." Sensors 25, no. 8 (2025): 2435. https://doi.org/10.3390/s25082435.

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Data accuracy is critical for sensor systems. As essential components of digital circuits within sensor systems, nanoscale CMOS latches are particularly susceptible to single-node upsets (SNUs) and double-node upsets (DNUs), which can lead to data errors. In this paper, a highly robust Double-Node-Upset-Tolerant Latch-Based on Input Splitting C-Elements (DNUISC) is proposed. The DNUISC latch is designed by interconnecting three sets of input-splitting C-elements to form a feedback loop, and it incorporates clock gating and fast-path techniques to minimize power consumption and delay. Simulations are conducted using the 28 nm process in HSPICE. The simulation results show that the DNUISC can self-recover from any single-node upset and is tolerant of any double-node upset. Compared with existing hardened latches, the DNUISC achieves a 55.21% reduction in area-power-delay product (APDP). Furthermore, the proposed DNUIS demonstrates high reliability and low sensitivity under varying process, voltage, and temperature conditions.

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34

Nessir, Zghoul Fadi, Al-Bakrawi Yousra Hussein, Issa Etier, and Nithiyananthan Kannan. "An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology." An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology 14, no. 4 (2024): 3830–54. https://doi.org/10.11591/ijece.v14i4.pp3830-3854.

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Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

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35

Emir, Recep, Dilek Surekci Yamacli, Serhan Yamacli, and Sezai Alper Tekin. "Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology." Electronics 13, no. 15 (2024): 2993. http://dx.doi.org/10.3390/electronics13152993.

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The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R2) values in the range of 0.86 and 0.99.

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36

Liu, Pei, Tian Zhao, Feng Liang, Jizhong Zhao, and Peilin Jiang. "A power-delay-product efficient and SEU-tolerant latch design." IEICE Electronics Express 14, no. 23 (2017): 20170972. http://dx.doi.org/10.1587/elex.14.20170972.

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37

Sahu, Kajul, and Owais Ahmad Shah. "A COMPARATIVE EVALUATION AND ANALYSIS OF D FLIP FLOP FOR HIGH SPEED AND LOW POWER APPLICATION." ICTACT Journal on Microelectronics 7, no. 1 (2021): 1062–65. https://doi.org/10.21917/ijme.2021.0185.

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This paper presents comparative analysis of various flip-flops in CMOS technology. We simulated dual dynamic node hybrid flip flop (DDFF), Hybrid latch flip-flop (HLFF), Modified hybrid latch flip flop (MHLFF), and modified transmission gate flip flop (TGFF). The average power of various flip flops are calculated at 0%, 25%, 50% and 100% data activity, at temperature 25-100 ºC and different voltages 0.7, 0.9, 1 and 1.5. The average delay is also calculated at room temperature. All of these parameters are calculated in 32nm CMOS technology with the help of TSPICE. It was observed that MHLFF is the flop-flop that consumes less power compared to other flip flops. We are comparing performance and power dissipation and also compared transistor count of each flip flop.

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38

Inoue, Keisuke, and Mineo Kaneko. "Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation." IPSJ Transactions on System LSI Design Methodology 4 (2011): 232–44. http://dx.doi.org/10.2197/ipsjtsldm.4.232.

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39

Andersson, Niklas U., and Mark Vesterbacka. "A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 10 (2014): 773–77. http://dx.doi.org/10.1109/tcsii.2014.2345289.

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40

Alioto, M., and G. Palumbo. "Power-delay optimization of D-latch/MUX source coupled logic gates." International Journal of Circuit Theory and Applications 33, no. 1 (2005): 65–86. http://dx.doi.org/10.1002/cta.305.

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41

Surbhi, Vishwakarma, and Vinod Kapse Dr. "Design of Dual Pulsating Latch Flip Flop DPLFF using Novel Pulse Generator." International Journal of Trend in Scientific Research and Development 2, no. 2 (2018): 1713–18. https://doi.org/10.31142/ijtsrd12743.

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In this paper various flip flop structures have been studied. In all designs to reduce power consumption, the Pulse Generator circuitry should be in build along with the flip flop itself. If a pulse generator is included along with DPSCRFF structure, power consumption can be reduced. In this work a new design of flip flop, Double Pulse Latch Flip flop DPLFF is proposed. DPLFF eliminates unnecessary glitches, which consume more power. DPLFF consume less power for same delay as compared with other existing techniques, which is performing one of the fastest known flip flops. In serial operation as shift register the proposed DPLFF can perform better at the higher frequency. The stacking of transistor in the latch stage cause reduction in subthreshold leakage current and thus the static power consumption is also less for DPLFF. This is better suited for low power circuits at deep submicron technology where leakages are more dominant. Surbhi Vishwakarma | Dr. Vinod Kapse "Design of Dual Pulsating Latch Flip-Flop (DPLFF) using Novel Pulse Generator" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-2 , February 2018, URL: https://www.ijtsrd.com/papers/ijtsrd12743.pdf

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42

HU, YINGBO, and RUNDE ZHOU. "LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 121–31. http://dx.doi.org/10.1142/s0218126609004971.

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In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 μm CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45–60%, 11–27% and 58–65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.

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43

Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge of the capacitors. It has a higher delay but lower the energy consumption by 30%.

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Gupta, Anshu, Lalita Gupta, and R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator." International Journal of Engineering & Technology 7, no. 2.16 (2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

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Qi, Shaozhen. "A Review of Comparators Inprovment Design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 407–17. http://dx.doi.org/10.54097/hset.v27i.3784.

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This paper reviews and analyzes the three proposed new comparators, as a indirection of future works. The first improved design is the pre-amplifier improved comparator that the input of the latch is changed to a PMOS transistor, and a pair of cross-coupled transistors are used in the preamplifier part to amplify the gain, which finally realizes the proposed circuit with better comparison speed, more less power dissipation. The switch separated latch comparator is another improved design that the latching stage with separate gate-biased cross-coupled transistors. Using this new transconductance-enhanced latching stage enables dramatic reductions in delay and power dissipation. The third type of comparator proposed is an innovative design. It adds a capacitor to the input tail current source of the preamplifier. Compared with the original Elzakker comparator, power dissipation has dropped by almost 50%.

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46

Deng, Ruichen. "Performance Analysis for Energy-Efficient Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 94–105. http://dx.doi.org/10.54097/hset.v27i.3725.

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This work studies three different comparator proposed in recent years. Compared to the strnongARM latch as well as the Elzakker’s comparator, the dynamic comparator added cross-coupled devices that keeps the pre-amplifier’s integration nodes from fully discharge to the ground and thus improves energy performance. The dynamic bias latch-type comparator is an innovative design which added a tail capacitor to the pre-amplifier in order to block off the discharge route between the internal nodes and the ground. Though this design reduced the energy consumption significantly compared with the Elzakker’s comparator, it results in longer delay and only little improvement on the input-referred noise. The FIA dynamic comparator implemented a floating inverter amplifier (FIA) that utilizes a reservoir capacitor which cuts off its charging path and discharging path significantly reduced the energy consumption and improved noise performance to power itself.

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47

Jangra, Payal, and Manoj Duhan. "Design and analysis of Voltage-Gated Spin-Orbit Torque (VgSOT) Magnetic Tunnel Junction based Non-Volatile Flip Flop design for Low Energy Applications." Journal of Integrated Circuits and Systems 19, no. 1 (2024): 1–12. http://dx.doi.org/10.29292/jics.v19i1.743.

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In this paper, a Voltage-gated Spin-Orbit Torque based non-volatile flip-flop design has been discussed. Theflip-flop consists of a conventional CMOS master latch used in normal operations, and a VgSOT-MTJ basedslave latch has been considered for interim data saving during power-gating. The current circuit uses the samewrite current to write data into two magnetic tunnel junctions, saving 50% of storing energy. The proposedNVFF circuit has been simulated using Cadence Virtuoso 45nm. The performance parameters like energyconsumption and delay during restore and store operations of VgSOT-MTJ based NVFF circuit have beenanalyzed in this paper and compared with SOT-MTJ based and STT-MTJ based NVFF circuits. Simulationresults show that for the switching delay, VgSOT-MTJ based NVFF performs 40% and 58% better than SOT-MTJ NVFF and STT-MTJ based NVFFs, respectively during storing mode and 83% and 88% better than SOT-MTJ and STT-MTJ based NVFFs during restoring mode. In terms of energy consumption, during storingmode, VgSOT-MTJ based NVFF consumes 84% less energy than SOT-MTJ NVFF and 90 % less energy thanSTT-MTJ based NVFFs. During restoring mode, VgSOT-MTJ based NVFF consumes 70% and 80% lessenergy than SOT-MTJ NVFF and STT-MTJ, respectively.

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Savugathali, Salahuddin, Muslim Mustapa, Mohammed Sharazel Razali, and Fazrul Faiz Zakaria. "Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (2019): 628. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp628-636.

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<span>A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.</span>

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49

Talebipoor, Neda, Peiman Keshavarzian, and Behzad Irannejad. "Low Power and High Speed D-Latch Circuit Designs Based on Carbon Nanotube FET." International Journal of Engineering & Technology 2, no. 1 (2012): 12. http://dx.doi.org/10.14419/ijet.v2i1.483.

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In this paper we propose low power and high speed D-latche circuits base on carbon nanotube field effect transistor. D-latches are the important state-holding elements and systems performance enhancement will be achieved by improving the flip-flop latches structure. The circuit designs are simulated by Hspice .In this paper the consumption result of the circuit parameters such as delay, power and PDP for our three different D-latch circuit design in various voltages and different temperatures.

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Verma, Shreya, Tunikipati Usharani, S. Iswariya, and Bhavana Godavarthi. "Implementation of MHLFF based low power pulse triggered flip flop." International Journal of Engineering & Technology 7, no. 1.1 (2017): 483. http://dx.doi.org/10.14419/ijet.v7i1.1.10150.

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The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

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Journal articles on the topic 'Delay-latch'

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