Relevant bibliographies by topics / Delay models for CMOS circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Delay models for CMOS circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Delay models for CMOS circuits"

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Dokic, Branko, Tatjana Pesic-Brdjanin, and Rados Dabic. "Analytic models of CMOS logic in various regimes." Serbian Journal of Electrical Engineering 11, no. 2 (2014): 269–90. http://dx.doi.org/10.2298/sjee140106022d.

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In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS) have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.
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Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.
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Jang, Ikchan, Jintae Kim, and SoYoung Kim. "Accurate delay models of CMOS CML circuits for design optimization." Analog Integrated Circuits and Signal Processing 82, no. 1 (December 5, 2014): 297–307. http://dx.doi.org/10.1007/s10470-014-0460-4.

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Hernandez, Yoanlys, Bernhard Stampfer, Tibor Grasser, and Michael Waltl. "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies." Crystals 11, no. 9 (September 21, 2021): 1150. http://dx.doi.org/10.3390/cryst11091150.

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All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.
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Esonu, M. O., D. Al-Khalili, and C. Rozon. "Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits." VLSI Design 1, no. 4 (January 1, 1994): 261–76. http://dx.doi.org/10.1155/1994/70696.

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The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or Noise Margin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalent ECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used.
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Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.
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Sharroush, Sherif. "Optimizing the Performance of MOS Stacks." Iraqi Journal for Electrical and Electronic Engineering 16, no. 1 (June 7, 2020): 85–98. http://dx.doi.org/10.37917/ijeee.16.1.11.

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CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.
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Embabi, S. H. K., and R. Damodaran. "Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 9 (1994): 1132–42. http://dx.doi.org/10.1109/43.310902.

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Długosz, Rafał, Andrzej Rydlewski, and Tomasz Talaśka. "Novel, low power, nonlinear dilatation and erosion filters realized in the CMOS technology." Facta universitatis - series: Electronics and Energetics 28, no. 2 (2015): 237–49. http://dx.doi.org/10.2298/fuee1502237d.

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In this paper we propose novel, binary-tree, asynchronous, nonlinear filters suitable for signal processing realized at the transistor level. Two versions of the filter have been proposed, namely the dilatation (Max) and the erosion (Min) one. In the proposed circuits an input signal (current) is sampled in a delay line, controlled by a multiphase clock. In the subsequent stage particular samples are converted to 1-bit digital signals with delays proportional to the values of these samples. In the last step the delays are compared in digital binary-tree structure in order to find either the Min or the Max value, depending on which filter is used. Both circuits have been simulated in the TSMC CMOS 0.18?m technology. To make the results reliable we applied the corner analysis procedure. The circuits were tested for temperatures ranging from -40 to 120?C, for different transistor models and supply voltages. The circuits offer a precision of about 99% at a typical detection time of 20 ns (for the Max filter) and 100 ns for the Min filter (the worst case scenario). The energy consumed per one input during a single calculation cycle equals 0.32 and 1.57 pJ, for the Max and Min filters, respectively.
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Karthikeyan, A., and P. S. Mallick. "Buffer for High Performance in CNT Based VLSI Interconnects." Advanced Science Letters 24, no. 8 (August 1, 2018): 5975–81. http://dx.doi.org/10.1166/asl.2018.12230.

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Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.
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Dissertations / Theses on the topic "Delay models for CMOS circuits"

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Sun, Jingyuan. "Optimization of high-speed CMOS circuits with analytical models for signal delay." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0002/MQ43548.pdf.

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Kavak, Fatih. "A Sizing Algorithm for Non-Overlapping Clock Signal Generators." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2416.

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The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.

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Mroszczyk, Przemyslaw. "Computation with continuous mode CMOS circuits in image processing and probabilistic reasoning." Thesis, University of Manchester, 2014. https://www.research.manchester.ac.uk/portal/en/theses/computation-with-continuous-mode-cmos-circuits-in-image-processing-and-probabilistic-reasoning(57ae58b7-a08c-4a67-ab10-5c3a3cf70c09).html.

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The objective of the research presented in this thesis is to investigate alternative ways of information processing employing asynchronous, data driven, and analogue computation in massively parallel cellular processor arrays, with applications in machine vision and artificial intelligence. The use of cellular processor architectures, with only local neighbourhood connectivity, is considered in VLSI realisations of the trigger-wave propagation in binary image processing, and in Bayesian inference. Design issues, critical in terms of the computational precision and system performance, are extensively analysed, accounting for the non-ideal operation of MOS devices caused by the second order effects, noise and parameter mismatch. In particular, CMOS hardware solutions for two specific tasks: binary image skeletonization and sum-product algorithm for belief propagation in factor graphs, are considered, targeting efficient design in terms of the processing speed, power, area, and computational precision. The major contributions of this research are in the area of continuous-time and discrete-time CMOS circuit design, with applications in moderate precision analogue and asynchronous computation, accounting for parameter variability. Various analogue and digital circuit realisations, operating in the continuous-time and discrete-time domains, are analysed in theory and verified using combined Matlab-Hspice simulations, providing a versatile framework suitable for custom specific analyses, verification and optimisation of the designed systems. Novel solutions, exhibiting reduced impact of parameter variability on the circuit operation, are presented and applied in the designs of the arithmetic circuits for matrix-vector operations and in the data driven asynchronous processor arrays for binary image processing. Several mismatch optimisation techniques are demonstrated, based on the use of switched-current approach in the design of current-mode Gilbert multiplier circuit, novel biasing scheme in the design of tunable delay gates, and averaging technique applied to the analogue continuous-time circuits realisations of Bayesian networks. The most promising circuit solutions were implemented on the PPATC test chip, fabricated in a standard 90 nm CMOS process, and verified in experiments.
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Nabavi-Lishi, Abdolreza. "Delay and current evaluation in CMOS circuits." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=41166.

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An accurate and fast technique has been developed for computing the supply current as well as the delay in CMOS combinational circuits. It is based on a new analytical model of the CMOS inverter which is designed specifically to compute the maximum supply current and the delay without recourse to integration. If the current waveform is needed, integration is used only for the trailing edge. This model can be used not only to compute maximum supply current and delay in CMOS circuits, but also to detect dynamic hazards.
The extension to general CMOS circuits is achieved through a collapsing method which reduces each gate to an equivalent inverter. Unlike previous attempts to solve this problem, our technique is not limited to single input transitions or to step inputs. It also takes into account the relative positions of the switching inputs in series-connected transistors.
The improvement in computation speed, for delay and maximum current in large circuits, approaches 4 orders of magnitude compared to HSPICE using the level-3 MOSFET model. For current waveforms the speed improvement approaches 3 orders of magnitude. The accuracy of computing the delay and the supply current is usually within 10% and 12%, respectively. Although the technique has been tested on static CMOS gate circuits, the extension to dynamic circuits is straightforward.
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Hamoui, Anas. "Current, delay, and power analysis of submicron CMOS circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0022/MQ50618.pdf.

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Lazzari, Cristiano. "Automatic layout generation of static CMOS circuits targeting delay and power." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/5690.

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A crescente evolução das tecnologias de fabricação de circuitos integrados demanda o desenvolvimento de novas ferramentas de CAD. O desenvolvimento tradicional de circuitos digitais a nível físico baseia-se em bibliotecas de células. Estas bibliotecas de células oferecem certa previsibilidade do comportamento elétrico do projeto devido à caracterização prévia das células. Além disto,diferentes versões para cada célula são requeridas de forma que características como atraso e consumo sejam atendidos, aumentando o número de células necessárias em uma bilioteca. A geração automática de leiautes é uma alternativa cada vez mais importante para a geracão baseada em células. Este método implementa transistores e conexões de acordo com padrões que são definidos em algoritmos sem as limitações impostas pelo uso de uma biblioteca de células. A previsibilidade em leiautes gerado automaticamente é oferecida por ferramentas de análise e estimativa. Estas ferramentas devem ser aptas a trabalhar com estimativas do leiaute e gerar informações relativas a atraso, potência e área. Este trabalho inclui a pesquisa de novos métodos de síntese física e a implementação de um gerador automático de leiautes cujas células são geradas no momento da síntese do leiaute. A pesquisa investiga diferentes estratégias de disposição dos componentes (transistores, contatos e conexões) em um leiaute e seus efeitos na ocupação de área e no atraso e de um circuito. A estratégia de leiaute utilizada aplica técnicas de otimização de atraso pela integração com uma técnicas de dimensionamento de transistores. Isto é feito de forma que o método de folding permita diferentes dimensionamentos para os transistores. As principais características da estratégia proposta neste trabalho são: linhas de alimentação entre bandas, roteamento sobre o leiaute (não são utilizados canais de roteamento) e geração de leiautes visando a redução do atraso do circuito pela aplicação da técnica de dimensionamento ao leiaute e redução do comprimento médio das conexões. O fato de permitir a implementação de qualquer combinação de equações lógicas, sem as restrições impostas pelo uso de uma biblioteca de células, permite a síntese de circuitos com uma otimização do número de transistores utilizados. Isto contribui para a diminuição de atrasos e do consumo, especialmente do consumo estático em circuitos submicrônicos. Comparações entre a estratégia proposta e outros métodos conhecidos são apresentadas de forma a validar a proposta apresentada.
The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.
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Hafed, Mohamed M. "CMOS inverter current and delay models incorporating interconnect effects." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0025/MQ50614.pdf.

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Martin, Denis. "Delay computation in switch-level models of MOS circuits." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=64038.

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Skoll, David F. (David Franklyn) Carleton University Dissertation Engineering Electronics. "Delay and power macro-models for optimizing ECL circuits." Ottawa, 1994.

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Tabrizi, Nozar. "Asynchronous control circuit design and hazard generation : inertial delay and pure delay models /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pht114.pdf.

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Books on the topic "Delay models for CMOS circuits"

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F, Sproull Robert, and Harris David, eds. Logical effort: Designing fast CMOS circuits. San Francisco, Calif: Morgan Kaufmann Publishers, 1999.

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Saibal, Mukhopadhyay, and SpringerLink (Online service), eds. Low-Power Variation-Tolerant Design in Nanometer Silicon. Boston, MA: Springer Science+Business Media, LLC, 2011.

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Chakrabarty, Krishnendu, and Sandeep K. Goel. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. Taylor & Francis Group, 2017.

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Logic-timing Simulation And the Degradation Delay Model. Imperial College Press, 2006.

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Design for Manufacturability and Yield for Nano-Scale CMOS (Series on Integrated Circuits and Systems). Springer, 2007.

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Mukhopadhyay, Saibal, and Swarup Bhunia. Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, 2014.

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Mukhopadhyay, Saibal, and Swarup Bhunia. Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, 2011.

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Book chapters on the topic "Delay models for CMOS circuits"

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Guerrero, D., G. Wilke, J. L. Güntzel, M. J. Bellido, J. Juan Chico, P. Ruiz-de-Clavijo, and A. Millan. "Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits." In Lecture Notes in Computer Science, 501–10. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39762-5_56.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Delay Models." In Asynchronous Circuits, 35–43. New York, NY: Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_3.

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Juan-Chico, Jorge, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, and Manuel Valencia. "Degradation Delay Model Extension to CMOS Gates." In Integrated Circuit Design, 149–58. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_15.

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Rezzoug, M., P. Maurine, and D. Auvergne. "Second Generation Delay Model for Submicron CMOS Process." In Integrated Circuit Design, 159–67. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_16.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Bi-Bounded Delay Models." In Asynchronous Circuits, 143–66. New York, NY: Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_8.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Up-Bounded-Delay Race Models." In Asynchronous Circuits, 83–111. New York, NY: Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_6.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "Limitations of Up-Bounded Delay Models." In Asynchronous Circuits, 255–73. New York, NY: Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_13.

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Wirnshofer, Martin. "Design of In-situ Delay Monitors." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits, 31–43. Dordrecht: Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_5.

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Suzuki, Daisuke, Minoru Saeki, and Tetsuya Ichikawa. "DPA Leakage Models for CMOS Logic Circuits." In Cryptographic Hardware and Embedded Systems – CHES 2005, 366–82. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11545262_27.

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Wirnshofer, Martin. "Adaptive Voltage Scaling by In-situ Delay Monitoring." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits, 23–30. Dordrecht: Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_4.

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Conference papers on the topic "Delay models for CMOS circuits"

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Chang, Jian, and Louis G. Johnson. "A Novel Delay Model of CMOS VLSI Circuits." In 2006 49th IEEE International Midwest Symposium on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/mwscas.2006.382318.

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Embabi and Damodaran. "Delay models for timing simulation of CMOS/BiCMOS/BiNMOS mixed digital circuits." In Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting BIPOL-93. IEEE, 1993. http://dx.doi.org/10.1109/bipol.1993.617478.

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Dartu, Florentin, Noel Menezes, Jessica Qian, and Lawrence T. Pillage. "A gate-delay model for high-speed CMOS circuits." In the 31st annual conference. New York, New York, USA: ACM Press, 1994. http://dx.doi.org/10.1145/196244.196562.

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Marranghello, Felipe S., Andre I. Reis, and Renato P. Ribas. "Design-oriented delay model for CMOS inverter." In 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2012. http://dx.doi.org/10.1109/sbcci.2012.6344424.

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Marranghello, Felipe S., Andre I. Reis, and Renato P. Ribas. "Delay model for static CMOS complex gates." In 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2013. http://dx.doi.org/10.1109/sbcci.2013.6644864.

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Marranghello, Felipe S., Andre I. Reis, and Renato P. Ribas. "CMOS inverter analytical delay model considering all operating regions." In 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2014. http://dx.doi.org/10.1109/iscas.2014.6865419.

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Ku, Ja Chun, and Yehea Ismail. "A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay." In 2007 IEEE International Symposium on Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/iscas.2007.378655.

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Messaris, Ioannis, Maria Ntogramatzi, Nikolaos Karagiorgos, and Spyridon Nikolaidis. "Equivalent inverter-based characterization tool for nano-scale CMOS digital cells: Non-linear-delay-models evaluation." In 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST). IEEE, 2018. http://dx.doi.org/10.1109/mocast.2018.8376622.

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Singh, Ashish Kumar, Jagannath Samanta, and Jaydeb Bhaumik. "Modified I–V model for delay analysis of UDSM CMOS circuits." In 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS). IEEE, 2012. http://dx.doi.org/10.1109/codis.2012.6422212.

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Jiang, Minglu, Qiang Li, Zhangcai Huang, and Yasuaki Inoue. "A non-iterative effective capacitance model for CMOS gate delay computing." In 2010 International Conference on Communications, Circuits and Systems (ICCCAS). IEEE, 2010. http://dx.doi.org/10.1109/icccas.2010.5581849.

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