Dissertations / Theses on the topic 'Delay models for CMOS circuits'

The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.

The objective of the research presented in this thesis is to investigate alternative ways of information processing employing asynchronous, data driven, and analogue computation in massively parallel cellular processor arrays, with applications in machine vision and artificial intelligence. The use of cellular processor architectures, with only local neighbourhood connectivity, is considered in VLSI realisations of the trigger-wave propagation in binary image processing, and in Bayesian inference. Design issues, critical in terms of the computational precision and system performance, are extensively analysed, accounting for the non-ideal operation of MOS devices caused by the second order effects, noise and parameter mismatch. In particular, CMOS hardware solutions for two specific tasks: binary image skeletonization and sum-product algorithm for belief propagation in factor graphs, are considered, targeting efficient design in terms of the processing speed, power, area, and computational precision. The major contributions of this research are in the area of continuous-time and discrete-time CMOS circuit design, with applications in moderate precision analogue and asynchronous computation, accounting for parameter variability. Various analogue and digital circuit realisations, operating in the continuous-time and discrete-time domains, are analysed in theory and verified using combined Matlab-Hspice simulations, providing a versatile framework suitable for custom specific analyses, verification and optimisation of the designed systems. Novel solutions, exhibiting reduced impact of parameter variability on the circuit operation, are presented and applied in the designs of the arithmetic circuits for matrix-vector operations and in the data driven asynchronous processor arrays for binary image processing. Several mismatch optimisation techniques are demonstrated, based on the use of switched-current approach in the design of current-mode Gilbert multiplier circuit, novel biasing scheme in the design of tunable delay gates, and averaging technique applied to the analogue continuous-time circuits realisations of Bayesian networks. The most promising circuit solutions were implemented on the PPATC test chip, fabricated in a standard 90 nm CMOS process, and verified in experiments.

An accurate and fast technique has been developed for computing the supply current as well as the delay in CMOS combinational circuits. It is based on a new analytical model of the CMOS inverter which is designed specifically to compute the maximum supply current and the delay without recourse to integration. If the current waveform is needed, integration is used only for the trailing edge. This model can be used not only to compute maximum supply current and delay in CMOS circuits, but also to detect dynamic hazards.
The extension to general CMOS circuits is achieved through a collapsing method which reduces each gate to an equivalent inverter. Unlike previous attempts to solve this problem, our technique is not limited to single input transitions or to step inputs. It also takes into account the relative positions of the switching inputs in series-connected transistors.
The improvement in computation speed, for delay and maximum current in large circuits, approaches 4 orders of magnitude compared to HSPICE using the level-3 MOSFET model. For current waveforms the speed improvement approaches 3 orders of magnitude. The accuracy of computing the delay and the supply current is usually within 10% and 12%, respectively. Although the technique has been tested on static CMOS gate circuits, the extension to dynamic circuits is straightforward.

A crescente evolução das tecnologias de fabricação de circuitos integrados demanda o desenvolvimento de novas ferramentas de CAD. O desenvolvimento tradicional de circuitos digitais a nível físico baseia-se em bibliotecas de células. Estas bibliotecas de células oferecem certa previsibilidade do comportamento elétrico do projeto devido à caracterização prévia das células. Além disto,diferentes versões para cada célula são requeridas de forma que características como atraso e consumo sejam atendidos, aumentando o número de células necessárias em uma bilioteca. A geração automática de leiautes é uma alternativa cada vez mais importante para a geracão baseada em células. Este método implementa transistores e conexões de acordo com padrões que são definidos em algoritmos sem as limitações impostas pelo uso de uma biblioteca de células. A previsibilidade em leiautes gerado automaticamente é oferecida por ferramentas de análise e estimativa. Estas ferramentas devem ser aptas a trabalhar com estimativas do leiaute e gerar informações relativas a atraso, potência e área. Este trabalho inclui a pesquisa de novos métodos de síntese física e a implementação de um gerador automático de leiautes cujas células são geradas no momento da síntese do leiaute. A pesquisa investiga diferentes estratégias de disposição dos componentes (transistores, contatos e conexões) em um leiaute e seus efeitos na ocupação de área e no atraso e de um circuito. A estratégia de leiaute utilizada aplica técnicas de otimização de atraso pela integração com uma técnicas de dimensionamento de transistores. Isto é feito de forma que o método de folding permita diferentes dimensionamentos para os transistores. As principais características da estratégia proposta neste trabalho são: linhas de alimentação entre bandas, roteamento sobre o leiaute (não são utilizados canais de roteamento) e geração de leiautes visando a redução do atraso do circuito pela aplicação da técnica de dimensionamento ao leiaute e redução do comprimento médio das conexões. O fato de permitir a implementação de qualquer combinação de equações lógicas, sem as restrições impostas pelo uso de uma biblioteca de células, permite a síntese de circuitos com uma otimização do número de transistores utilizados. Isto contribui para a diminuição de atrasos e do consumo, especialmente do consumo estático em circuitos submicrônicos. Comparações entre a estratégia proposta e outros métodos conhecidos são apresentadas de forma a validar a proposta apresentada.
The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Paul Hasler; Committee Member: David V Anderson; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.

The selection of adequate fault models is crucial to generating tests of high quality for complex digital VLSI circuits. This thesis presents a methodology to perform empirical validation of fault models and to get measures of effectiveness of test sets based on the targeted fault models.
The methodology is based on the automated fault diagnosis of test circuits, representative of the class of circuits being studied and designed to capture the characteristics of the fabrication process, cell libraries and CAD tools used in their development.
The methodology is applied to study the faulty behaviour of random logic environments for an experimental VLSI fabrication process. A test circuit is designed, using CMOS technology, and a statistically significant number of samples fabricated. The samples are tested and, subsequently, diagnosed, using a set of software tools developed for the purpose. Results of the ensuing analysis are presented.

Pour les nœuds technologiques avancés, la consommation statique des circuits intégrés est devenue un facteur essentiel de l'industrie microélectronique. L'efficacité énergétique des circuits est mesurée en fonction de leur performance et en fonction de leur consommation statique. Face à l'augmentation de la variabilité des paramètres physiques et environnementaux, la technologie silicium sur isolant complètement désertée (FD-SOI : Fully-Depleted Silicon-On-Insulator) permet de prolonger la loi de Moore dans le domaine nanométrique. Dans ce mémoire une étude statistique de l'énergie des circuits intégrés CMOS-FDSOI est réalisée. Des bibliothèques statistiques qui caractérisent le délai et la puissance statique des transistors CMOS-FDSOI sont mises en place. Compte tenu des avantages liés à la technologie FDSOI, des approches statistiques basées sur les bibliothèques sont appliquées pour estimer le délai et la puissance statique. En conservant l'exactitude de l'estimation, ces approches apportent un gain important en temps CPU. Suite à l'estimation du délai et de la puissance statique, les variations énergétiques des transistors CMOS-FDSOI sont étudiées en fonction de la tension d'alimentation et en fonction de la tension de polarisation. Ainsi, grâce à la détermination d'un compromis Délai-Puissance Statique efficace et l'élaboration d'un flow d'optimisation statistique, l'énergie statique d'un circuit a pu être optimisée
For advanced technology nodes, static consumption of integrated circuits has become a key factor for the microelectronics industry. Circuit energy efficiency is measured in terms of performance and static consumption. With the increase of physical and environmental parameters, the Fully-Depleted Silicon-on-Insulator technology allows to extend Moore's law in the nanometer domain. In this work, a statistical study of CMOS-FDSOI integrated circuit energy is carried out. Statistical libraries characterizing delay and static power of CMOS-FDSOI transistors are presented. Given the advantages of the FDSOI technology, statistical approaches based on the libraries are applied in order to estimate delay and static power. While maintaining the accuracy of the estimations, these approaches provide a significant gain in CPU time. Following delay and static power estimation, CMOS-FDSOI transistors energy variations are considered according to supply voltage and voltage body biasing. Thus, by determining an efficient Delay-Static Power compromise and the development of a statistical optimization flow, static energy of a circuit has been optimized

En la dècada actual, l'augment del consum energètic dels circuits integrats està tenint un impacte cada vegada més important en el disseny electrònic. Segons l'informe de la Semiconductor Industry Association de l'any 1997, es preveu que aquest impacte serà encara major en la propera dècada. En la bibliografia existeixen diversos treballs on es relaciona un consumo energètic elevat amb la degradació de les prestacions i la fiabilitat del xip. Per aquesta raó, el consum energètic ha estat incorporat com a un altre paràmetre a tenir en compte en el disseny dels circuits integrats. Es coneix com a energia de transició l'energia consumida per un circuit combinacional CMOS quan es produeix un canvi en les seves entrades. Una energia de transició excessivament elevada pot afectar a la fiabilitat del xip a través dels anomenats hot spots, i de l'electromigració. Altres efectes com el ground bouncing i la signal integrity degradation poden repercutir en les prestacions del circuit. La minimització de les degradacions esmentades anteriorment requereixen de la caracterització de l'energia de transició màxima durant la fase de disseny. A tal efecte, en aquesta tesi es proposen dues metodologies que permeten l'estimació de l'energia de transició màxima en circuits combinacionals CMOS. Donat que l'estimació del nivell màxim exacte es inviable en circuits a partir de mides mitjanes, es proposa el càlcul de dues cotes, una d'inferior i una altra de superior, que delimiten un interval de localització de l'esmentat nivell màxim. La tesi està estructurada en els següents capítols. En el capítol 1 es fa una introducció al tema investigat en aquesta tesi i es presenten els treballs existents que el tracten. En el capítol 2 s'introdueixen els models d'estimació de l'energia de transició emprats més habitualment a nivell lògic, que és el nivell de disseny considerat en aquesta tesi. Aquests models assumeixen que l'únic mecanisme de consum és la commutació de les capacitats paràsites del circuit. En els capítols 3 i 4 es tracta l'estimació de l'energia de transició màxima. Aquesta estimació es realitza a partir del càlcul de dues cotes properes, una superior i una altre inferior, a aquesta energia màxima. En el capítol 5 es presenta l'anàlisi del comportament de l'activitat ponderada front als models de retard estàtics. Finalment, en el capítol 6 s'aborden les conclusions generals de la tesis i el treball futur.
El consumo energético de los circuitos integrados es un factor cuyo impacto en el diseño electrónico ha crecido significativamente en la década actual. Según el informe de la Semiconductor Industry Association del año 1997, se prevé que este impacto será aún mayor en la próxima década. En la bibliografía existen diversos trabajos donde se relaciona un consumo energético elevado con la degradación de las prestaciones y la fiabilidad del chip. Por esta razón, el consumo energético ha sido incorporado como otro parámetro a tener en cuenta en el diseño de los circuitos integrados. Se conoce como energía de transición la energía consumida por un circuito combinacional CMOS cuando se produce un cambio en las entradas del mismo. Una energía de transición excesivamente elevada puede afectar a la fiabilidad del chip a través de los hot spots, de la electromigración. Otros efectos como el ground bouncing y la signal integrity degradation pueden repercutir en las prestaciones del circuito. La minimización de las degradaciones mencionadas anteriormente requiere de la caracterización de la energía de transición máxima durante la fase de diseño. A este efecto, se propone en esta tesis dos metodologías que permiten la estimación de la energía de transición máxima en circuitos combinacionales CMOS. Dado que la estimación del nivel máximo exacto es inviable en circuitos a partir de tamaños medios, se propone el cálculo de dos cotas, una de inferior y otra de superior, que delimiten un intervalo de localización de dicho nivel máximo. La tesis está estructurada en los siguientes capítulos. En el capítulo 1 se presenta una introducción al tema investigado en esta tesis y se resumen los trabajos existentes más importantes. En el capítulo 2 se introducen los modelos de estimación de la energía de transición más comúnmente utilizados a nivel lógico, que es el nivel de diseño considerado en esta tesis. Estos modelos asumen que el único mecanismo de consumo es la conmutación de las capacidades parásitas del circuito. En los capítulos 3 y 4 se aborda la estimación de la energía de transición máxima. Esta estimación se realiza a partir del cálculo de dos cotas cercanas, una superior y una inferior, a esta energía máxima. En el capítulo 5 se presenta el análisis del comportamiento de la actividad ponderada frente a los modelos de retardo estáticos. Finalmente, en el capítulo 6 se presentan las conclusiones generales de la tesis y el trabajo futuro.
The importance of the energy consumption on the design of electronic circuits has increased significantly during the last decade. According to the report of the Semiconductor Industry Association, of 1997, the impact in the next decade will be even greater. In the bibliography several works exist relating to the high energy consumption with the degradation of the reliability and performance of the xip. For this reason, the energy consumption has been included as another parameter to take into account during the design of integrated circuits. It is known as transition energy, the energy consumed by a CMOS combinational circuit when its inputs change their value. Excessively high transition energy may affect the reliability of the chip through the generation of hot spots and electromigration. Other effects such as ground bouncing and signal integrity degradation may reduce the performance of the circuit. In order to minimize the previously detected bad effects it is useful to characterize the maximum transition energy, during the design phase. To this objective, this thesis presents two methodologies that allow for the estimation of the maximum transition energy in CMOS combinational circuits. Given that the estimation of the maximum level is only attainable for medium size circuits, it is proposed the calculation of bounds (higher and lower) delimiting the interval where the maximum level is located. The thesis is divided into the following chapters. In chapter 1 an introduction to the topic and a review of the previous works related to this research domain is given. In chapter 2 the models most extended for the estimation of the transition energy are presented. These models are mainly used at logic level which is the level assumed in this thesis. They assume that the switching of the parasitic capacitances is the only mechanism producing energy consumption. In chapters 3 and 4 the estimation of the maximum transition energy is considered. This estimation is made from the calculation of an upper and lower bound to this maximum transition energy. In chapter 5 the analysis of the switching activity is made for different static delay models. Finally, in chapter 6 the general conclusions of the thesis and future work are discussed.

Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings from the counter and the interpolators are always consistent with very high probability. Therefore, the operation of the counter is controlled with a synchronising logic that is in turn controlled with the interpolation result. Another synchronising logic makes it possible to synchronise the timing signals with multiphase time-interleaved clock signals as if the synchronising was done with a GHz-level clock, and enables multi-stage interpolation. Multi-stage interpolation reduces the number of delay cells and registers needed. The delay line interpolators are stabilised with nested delay-locked loops, which leads to good stability and makes it possible to improve single-shot precision with a single look-up table containing the integral nonlinearities of the interpolators measured at the room temperature. A multi-channel prototype TDC was fabricated in a 0.6 μm digital CMOS process. The prototype reaches state-of-the-art rms single-shot precision of better than 20 ps and low power consumption of 50 mW as an integrated TDC.

Ce memoire traite des effets de petites dimensions du transistor metal-oxyde-semiconducteur (mos). Les principales methodes de maigrissement sont analysees et les grandes lignes de l'evolution des technologies mos sont esquissees. Un modele courant-tension du transistor, qui prend en compte ces effets physiques et qui se prete bien a une extraction de parametres rapide et facile, est adopte. Cette derniere etude est concretisee par la mise au point et la programmation d'un banc de caracterisation en continu. Une structure d'amplificateur operationnel est etudiee et realisee dans une technologie cmos reduite. Enfin, les consequences des petites dimensions sur les performances de cet amplificateur operationnel sont evaluees.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

Global optimization of high speed and high integration CMOS VLSI circuit is greatly in need in deep submicron regime with respect to signal delay, chip area and power dissipation. Accurate modeling of signal path delays is of particular importance in optimization. Although circuit level simulators like SPICE produce accurate and detailed delay information, analytical delay models are required in general because of the time consuming computation in SPICE simulations. New analytical delay models for both inverter and non-inverter stage of CMOS circuit in deep submicron regime are proposed in this work. The modeling takes into account circuit topologies and ramp input effect. The models were studied for various CMOS circuits of different complexities. Simulation results show an overall 10% difference and a considerably speed-up as compared to SPICE level 3 simulator. Based on the new analytical delay model, a circuit optimization program is developed, which is aiming to provide designer first hand information on circuit delay, area and power consumption and to help designer find the optimum design among different circuit topologies and transistor sizings, especially in submicron region. The program reads in circuit description from SIS--a multi-level logic synthesis and minimization system, maps it into CMOS circuit stages, analyzes the performance and finds the optimal circuit topology and sizing according to the design criteria.

碩士
國立清華大學
資訊工程學系
91
Transistor sizing is a timing optimization technique. We solve the transistor sizing problem by using a non-linear programming method with the SPICE Data Extracted Delay Model. The experiment result shows that the SPICE data extracted delay model is more precise than a simple RC or the Elmore delay model. The approach we proposed in this paper sized each transistor in the circuit twice at most. It is better than other approaches, such as convex programming and simulated annealing. It is because that the circuit characteristics of different circuits are much different. The parameters of the cost function could be modified in order to meet the circuit characteristics.

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.

abstract: Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
Dissertation/Thesis
M.S. Electrical Engineering 2011

Aggressive scaling of CMOS technology in sub-90nm nodes has created huge challenges. Variations due to fundamental physical limits, such as random dopants fluctuation (RDF) and line edge roughness (LER) are increasing significantly with technology scaling. In addition, manufacturing tolerances in process technology are not scaling at the same pace as transistor's channel length due to process control limitations (e.g., sub-wavelength lithography). Therefore, within-die process variations worsen with successive technology generations. These variations have a strong impact on the maximum clock frequency and leakage power for any digital circuit, and can also result in functional yield losses in variation-sensitive digital circuits (such as SRAM). Moreover, in nanometer technologies, digital circuits show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost while achieving higher performance and density. It is therefore not surprising that the International Technology Roadmap for Semiconductors (ITRS) lists variability as one of the most challenging obstacles for IC design in nanometer regime. To facilitate variation-tolerant design, we study the impact of random variations on the delay variability of a logic gate and derive simple and scalable statistical models to evaluate delay variations in the presence of within-die variations. This work provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, especially at lower supply voltages. The derived models are simple, scalable, bias dependent and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit/architecture optimization as well as technology prediction (especially in low-power and low-voltage operation). The derived models are verified using Monte Carlo SPICE simulations using industrial 90nm technology. Random variations in nanometer technologies are considered one of the largest design considerations. This is especially true for SRAM, due to the large variations in bitcell characteristics. Typically, SRAM bitcells have the smallest device sizes on a chip. Therefore, they show the largest sensitivity to different sources of variations. With the drastic increase in memory densities, lower supply voltages and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. In this research, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow accounts for the impact of bitcell read current variation, sense amplifier offset distribution, timing window variation and leakage variation on functional yield. The methodology overcomes the pessimism existing in conventional worst-case design techniques that are used in SRAM design. The proposed statistical yield estimation methodology allows early yield prediction in the design cycle, which can be used to trade off performance and power requirements for SRAM. The methodology is verified using measured silicon yield data from a 1Mb memory fabricated in an industrial 45nm technology. Embedded SRAM dominates modern SoCs and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, in the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operation and meet yield targets. We propose a new architecture that significantly reduces array switching power for SRAM. The proposed architecture combines built-in self-test (BIST) and digitally controlled delay elements to reduce the wordline pulse width for memories while ensuring correct read operation; hence, reducing switching power. A new statistical simulation flow was developed to evaluate the power savings for the proposed architecture. Monte Carlo simulations using a 1Mb SRAM macro from an industrial 45nm technology was used to examine the power reduction achieved by the system. The proposed architecture can reduce the array switching power significantly and shows large power saving - especially as the chip level memory density increases. For a 48Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it a very attractive solution for 45nm and below technologies. In addition to its impact on bitcell read current, the increase of local variations in nanometer technologies strongly affect SRAM cell stability. In this research, we propose a novel single supply voltage read assist technique to improve SRAM static noise margin (SNM). The proposed technique allows precharging different parts of the bitlines to VDD and GND and uses charge sharing to precisely control the bitline voltage, which improves the bitcell stability. In addition to improving SNM, the proposed technique also reduces memory access time. Moreover, it only requires one supply voltage, hence, eliminates the need of large area voltage shifters. The proposed technique has been implemented in the design of a 512kb memory fabricated in 45nm technology. Results show improvements in SNM and read operation window which confirms the effectiveness and robustness of this technique.

碩士
國立交通大學
生醫工程研究所
105
The semiconductor industry has become vigorous and developed for over 30 years, but now the IC industry has developed to ten nanometer level. In 2016, Intel has postponed the launch of 10-nm technology. It’s inevitable that Moore’s law has almost reached the limit. In order to get rid of the dilemma of the attenuating Moore’s law, there are two directions worth our efforts to study, “more Moore” and “more than Moore”. More Moore follows Moore’s law and continues challenging the limits by striving to reduce device’s size, such as the use of new materials, different structures, or advanced process technology. More than Moore is mainly focus on developing diversified applications. It not only improves the chip’s performance, but also promotes new features. The application of biomedical chip is the bright spot of the development. Furthermore, in the development of more Moore and more than Moore, nanowire transistor is an indispensable part in the research of biomedical sensor as a three-dimensional (3D) structure. Nowadays, the technology node has gradually extended to 10 nm from the sub-16 nm. Along with the diminishing device dimension, multi-channel structures have been proposed to maintain the high performance and high packing density. Gate-All-Around (GAA) nanowire metal-oxide-semiconductor field effect transistor (NW MOSFET) is the most promising structure for technology roadmap. In addition to the applications in IC industry, the other significant application of NW MOSFET is the device or CMOS integration circuit biomedical sensor. However, variability problems have become more serious as the device shrinking down to nanoscale regime. Hence, studying the characteristic fluctuation on 10-nm-gate GAA NW MOSFET has been an urgent issue. The fluctuation sources can be divided as: process variation effect (PVE), random dopant fluctuation (RDF), interface trap fluctuation (ITF), and work function fluctuation (WKF). Since the RDF and ITF have relatively small variations, we mainly focus on WKF and PVE. Besides, the variation of PVE is represented by the aspect ratio (AR) effect. In this work, a variety of WKF simulation methods are introduced: the average WKF method, the modified average WKF method, the localized WKF (LWKF) method, and the built-in TCAD method. After comparing the advantages and disadvantages of these methods, we adopt the LWKF method. In addition, the newly proposed application of LWKF method in different AR structures is introduced comprehensively in this thesis. In this thesis, we use an experimentally calibrated 3D quantum mechanically corrected device and circuit simulation to explore the 10-nm-gate GAA NW MOSFET impacted by WKF and AR effect. In addition to the direct current (DC) and alternate current (AC) properties, the timing and power characteristics operating in digital circuit influenced by WKF and AR effect are also investigated. For DC analysis, in n-type devices, the trends of on-state current and off-state current have both decreased as the number of high WK increases and threshold voltage Vth has positive dependency on the number of high WK. As for p-type devices, it shows reversed trend. The variations of Vth, drain-induced-barrier-lowering, and subthreshold swing are diminished with the reducing grain size for both n- and p-type devices. While considering WKF combined with AR effect simultaneously, the device of larger AR has less influence on device characteristics with the fixing metal grain size because the larger AR has large effective gate area and the grain size is relatively small. AC analysis shows that the devices with large grain size and small AR have greatest gate capacitance variation. In timing analysis, falling time is smaller than rising time owing to the larger driving capability of n-type device. Along with the increasing high WK number, high-to-low delay time and noise margin low become higher while low-to-high delay time and noise margin high decrease because both the fluctuations of delay time and NM follow the trend of σVth. All power consumption terms including static, short-circuit, and dynamic power have followed the trend that the larger the grain size is, the larger the fluctuation is. The circuit fluctuations suffered from WKF with different AR are also under estimated. In summary, the DC, AC, and digital-circuit characteristics of GAA NWFET affected by WKF and AR effect have been discussed. The results of this thesis can be a valuable reference for the development of nanowire biomedical sensors and can provide contemporary semiconductor industry to develop and improve the innovative technologies.

A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate.
Graduation date: 2003

博士
國立交通大學
電子工程研究所
78
Efficient physical timing models for complex CMOS AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS/AOI/OAI gates with wide rages of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% for the gates with commonly used device dimensions. From the timing models of CMOS AOI/OAI gates, the rules to determine the worst-case timing condition of a AOI/OAI gate and the guideline to determine th optimal gate configuration have also been explored. The developed timing models and design rules/guidelines are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a ggood accuracy and a reasonable CPU-time consumption. Reasonable accuracy, wide applicable ranges, high computation efficiency, and ability in speed optimization and autosizing make the developed timing models quite attractive in MOS VLSI/ULSI timing verification. Physical delay models and power dissipation models for small-geometry CMOS inverters with RC line and tree intercomections are presented. Through extensive comparisons with SPICE simulation results, it is shown that th maximum relative error in delay-time calculations is 15% and in power-dissipation calculations is 12% for 1.5 um CMOS inverters with RC line and tree interconnections. Moreover, the models have wide applicable ranges of circuits and device parameters. Based upon the mathematic optimization method as well as the developed power dissipation models and the delay models of CMOS inverters with RC line and tree interconnections, an experimental sizing program is constructed for improving various circuit performances like delay time, power-delay product, and delay time subject to constraint on power dissipation. In this CAD program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for optimal circuit performance. The four performance improvement techniques use minimun-size repeaters, optimal-size repeaters, cascaded input drivers, and optimal-size repeaters with cascaded input drivers to obtain the optimal circuit performance. It is found from the sizing results of the experimental program that the required tapering factor for minimum power-delay product in cascaded input drivers of interconnection lines and trees is in the range of 2-6 and in the range of 4-8 for a minimum delay. MOreover, adding a small number of drivers/repeaters with large sizes is more efficient in obtaining the optimal circuit performance. It is also shown that the technique of optimal-size repeaters with cascaded input drivers can lead to the lowest delay time and power-delay product. By applying the augmented Lagrange method, the experimental sizing program can optimize the delay time subject to constraint on power dissipation. The ability to optimize the delay time with power dissipation constratint makes the experimental sizing program more practical and versatile in improving the performace of CMOS logic gates with RC line and tree interconnections.

Delay variability poses a formidable challenge in both design and test of nanometer circuits. While process parameter variability is increasing with technology scaling, as circuits are becoming more complex, the dynamic or vector dependent variability is also increasing steadily. In this research, we develop solutions to incorporate the effect of delay variability in delay testing. We focus on two different applications of delay testing. In the first case, delay testing is used for testing the timing performance of a circuit using path based fault models. We show that if dynamic delay variability is not accounted for during the path selection phase, then it can result in targeting a wrong set of paths for test. We have developed efficient techniques to model the effect of two different dynamic effects namely multiple-input switching noise and coupling noise. The basic strategy to incorporate the effect of dynamic delay variability is to estimate the maximum vector delay of a path without being too pessimistic. In the second case, the objective was to increase the defect coverage of reliability defects in the presence of process variations. Such defects cause very small delay changes and hence can easily escape regular tests. We develop a circuit that facilitates accurate control over the capture edge and thus enable faster than at-speed testing. We further develop an efficient path selection algorithm that can select a path that detects the smallest detectable defect at any node in the presence of process variations.
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Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As the size of the devices is scales down to improve performance, the circuit becomes more sensitive to the process variations. Thus, it is necessary to have a device model that can predict the variations of device characteristics. Statistical modeling method is a potential solution for this problem. The novelty of the work is that we connect BSIM parameters directly to the underlying process parameters. This is very useful for fabs to optimize and control the specific processes to achieve certain circuit metric. This methodology and framework is extendable to any future technologies, because we used a device independent, but process depended frame work In the first part of this thesis, presents the design of nominal MOS devices with 28 nm physical gate length. The device is optimized to meet the specification of low standby power technology specification of International Technology Roadmap for Semiconductors ITRS(2012). Design of experiments are conducted and the following parameters gate length, oxide thickness, halo concentration, anneal temperature and title angle of halo doping are identified as the critical process parameters. The device performance factors saturation current, sub threshold current, output impendence and transconductance are examined under process variabilty. In the subsequent sections of the thesis, BSIM parameter extraction of MOS devices using the software ICCAP is presented. The variability of the spice parameters due to process variation is extracted. Using the extracted data a new BSIM interpolated model for a variability aware circuit design is proposed assume a single process parameter is varying. The model validation is done and error in ICCAP extraction method for process variability is less than 10% for all process variation condition in 3σ range. In the next section, proposes LUT model and interpolated method for a variability aware circuit design for single parameter variation. The error in LUT method for process variability reports less than 3% for all process variation condition in 3σ range. The error in perdition of drain current and intrinsic gain for LUT model files are very close to the result of device simulation. The focus of the work was to established effective method to interlink process and SPICE parameters under variability. This required generating a large number of BSIM parameter ducks. Since there could be some inaccuracy in large set of BSIM parameters, we used LUT as a golden standard. We used LUT modeling as a benchmark for validation of our BSIM3 model In the final section of thesis, impact of multi parameter variation of the processes in device performance is modelled using RSM method; the model is verified using ANOVA method. Models are found to be sufficient and stable. The reported error is less than 1% in all cases. Monte Carlo simulation confirms stability and repeatability of the model. The model for random variabilty of process parameters are formulated using BSIM and compared with the LUT model. The model was tested using a benchmark circuit. The maximum error in Monte Carlo simulation is found to be less than 3% for output current and less than 8% for output impedance.